JPH03154473A - Signal detection circuit for charge coupling element - Google Patents

Abstract

PURPOSE:To obtain a high quality output signal by converting an amplitude signal sent from a charge coupling element into a digital signal and extracting only the output signal representing the signal charge based on the digital signal. CONSTITUTION:A charge coupling element 1 having a charge integration type output circuit with gate is provided, which outputs an amplitude signal corresponding to a reference level and a signal charge for each period of a transfer clock pulse. Moreover, an A/D converter circuit 10 converting the amplitude signal sent from the charge coupling element 1 into a digital signal is provided. Furthermore, an orthogonal function series having a prescribed periodic orthogonal base function is selected from a storage section 12 and only an output signal representing a signal charge based on the digital signal sent from the A/D converter circuit is extracted 10 by an arithmetic processing circuit 13. Thus, a high quality output signal is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to signal processing of charge-coupled devices, and in particular to charge-coupled devices that eliminate noise in gated charge-integrating output circuits and detect only desired signal components with high precision. The present invention relates to a signal detection circuit.

Prior art A conventional charge coupled device is disclosed in Japanese Patent Application Laid-open No. 63-20
Japanese Patent No. 8375 discloses an output circuit for a charge-coupled device. This will be explained based on FIG.

A transfer channel 2 of a charge-coupled device 1 (hereinafter referred to as COD) includes a plurality of transfer electrodes 3 arranged in a straight line, and near the transfer electrode 3 at one end there is a portion of the transfer channel 2 that is transferred by the transfer channel 2. A detection diode 4 is provided to detect the incoming signal charge and convert it into an output voltage. Now, the transfer lock voltage φ1. The signal charge transferred by the transfer electrode 3 upon application of φ2 flows into the detection diode 4 every cycle of the transfer clock pulse and changes its potential. By receiving this potential change in the buffer circuit 5, the output can be taken out to the outside. A reset transistor 7 is connected to the gate 6 side of this buffer circuit 5, and a reset pulse φr is connected to the gate 8 of the reset transistor 7 at a period equal to that of the transfer pulse.
This application turns on the reset transistor 7, thereby resetting the potential of the detection diode 4 to the reference potential. Such an output circuit is generally known as a gated charge integration type output circuit, and is formed on a common semiconductor substrate together with the transfer channel 2, thereby forming the CCD 1.

The operation of this configuration will be explained.

The waveforms in FIG. 4 show the waveforms of the gated integral type output circuit in FIG. Time t. When the reset pulse φr is applied and the reset transistor 7 is turned on during the period from tl to tl, the potential of the detection diode 4 rises to the drain voltage V of the reset transistor 7. Next, when the reset transistor 7 is turned off at time t1, the potential of the detection diode 4 is increased by the capacitance 9 corresponding to the sum of the detection diode 4 and the gate capacitance of the buffer circuit 5, the gate of the reset transistor 7, and the potential of the detection diode 4.
A constant reference voltage Vo is determined by two capacitances: the capacitance between the sources and the capacitance between the sources. Next, at the same time, charge is transferred to the detection diode 4 and changes its potential, thereby obtaining the output voltage Vs.

Here, it will be described that in the gated charge integration type output circuit as described above, the reset transistor 7 generates a certain level of noise as described below.

While the reset transistor 7 is conductive from time t to time t, the reset transistor 7 generates a certain amount of noise En. The reference potential Vo is influenced by this noise En and fluctuates. For example, as shown in Figure 4,
Every time the reset pulse φr is applied, the reference potential Vo becomes E
Under the influence of n, the output S/N fluctuates as VO±Vn.
deteriorates. This Vn is generally called reset noise. Furthermore, in the circuit shown in FIG. 5, the noise source that generates the noise En is not only the reset transistor 7, but also
The buffer circuit 5 is also a noise source that generates random noise. Random noise E generated by this buffer circuit 5
r is called 1/f noise whose amplitude is proportional to the reciprocal of the frequency f.

By reducing the effects of such reset noise and l/f noise,
As one method for improving /N, a method is known as a double correlation sampling method, in which the reference potential 0 is clamped to a constant potential at time t2, and then the output voltage Vs is sampled at time 4. In addition, as a similar noise suppression method, there is a method in which the output signal is detected by performing synchronous detection using a carrier signal synchronized with the CCDI transfer lock after passing through a band pass filter whose center frequency is the CCD transfer lock frequency. Proposed.

Problems to be Solved by the Invention In the conventional device as described above, the noise that can be removed by the double correlation sampling method is equal to the reset noise.
/f noise and is limited to low frequency components. When attempting to remove noise using the double correlation sampling method, at time t2
The reference potential and the signal potential, which are clamped to a constant potential in 4 and 4, are affected by random noise that is uncorrelated with each other, and the S/N of the signal output deteriorates. The random noise at this time is 1/
f noise and other high frequency noise components.

In other words, in the double correlation sampling method, although it is possible to remove the low frequency components of the reset noise Vn and l/f noise generated by the reset transistor 7, it is not possible to remove the other high frequency components, resulting in a low S/N. The problem was that it was bad. Further, in the method using synchronous detection, there is a problem that when the detected signal waveform deviates significantly from the sine function, it becomes difficult to synchronize with the carrier, making it impossible to perform synchronous detection with high accuracy.

Means for Solving the Problems Therefore, in order to solve such problems, the present invention provides a gated charge integration type that outputs an amplitude signal corresponding to a reference potential and a signal charge every cycle of a transfer clock pulse. A charge-coupled device having an output circuit is provided, and the amplitude signal sent from the charge-coupled device is converted into a digital signal.
An /D conversion circuit is provided, and an orthogonal function sequence having a predetermined periodic orthogonal basis function is selected from this storage section, and only an output signal representing the signal charge is generated based on the digital signal sent from the A/D conversion circuit. An arithmetic processing circuit is provided to extract the

Further, in the signal detection circuit of the charge-coupled device, a storage section including a plurality of orthogonal function sequences in which periodic orthogonal basis functions are stored is provided.

As a result, it is possible to detect an output signal of a charge-coupled device that eliminates the influence of random noise such as reset noise and 1/f noise generated by a reset transistor in a charge-coupled device having a gated charge-integrating output circuit. In this case, since the signal is digitally processed by the A/D conversion circuit, processing accuracy is improved, and moreover, since detailed processing can be performed, a high-quality output signal can be obtained. In addition, by using the periodic orthogonal basis functions recorded in the orthogonal function sequence table in the storage unit, it is possible to adjust the transfer lock waveform of the charge-coupled device and the smoothing of the output waveform due to the high capacitance impedance of the charge-coupled device itself. hand,
An optimal periodic orthogonal function can be selected, thereby enabling high-quality detection of the output signal of the charge imaging element.

Embodiment An embodiment of the present invention will be explained based on FIGS. 1 to 4. Note that the same reference numerals are used for the same parts as in the prior art.

First, FIG. 1 schematically shows the overall configuration of a signal detection circuit of a charge-coupled device 1 (hereinafter referred to as COD). A CCD 1 is provided that has a gated charge integration type output circuit that outputs an amplitude signal corresponding to a reference potential and a signal charge every cycle of a transfer clock pulse. This CC
An A/D conversion circuit 10 is connected to the DI, and this has the function of converting the amplitude signal sent from the CCD 1 into a digital signal. Further, a ROM 12 is provided as a storage unit including a plurality of orthogonal function sequences 11 in which periodic orthogonal basis functions (described later) are stored.

An arithmetic processing circuit 13 is provided connected to the ROM 12 and the A/D conversion circuit 10. This arithmetic processing circuit 13 selects an orthogonal function sequence 11 having a predetermined periodic orthogonal basis function from the ROM 12, and outputs only an output signal representing a signal charge based on the digital signal sent from the A/D conversion circuit 10. It has the function of extracting.

In such a configuration, the operation of the signal detection circuit will be described based on FIG. Further, FIG. 3 shows the flow of the process, and FIG. 2 shows the state of the sampling.

FIG. 4 shows the output waveform of CCDI. C
Waveform section corresponding to each pixel (N pieces) of CDI - (section 1
~ section N). The period of this waveform matches the transfer lock period f0. Here, the output voltage of C0DI is V
f in the nth interval of (t). Let the fundamental frequency be the periodic orthogonal function Vn (t), as follows: Vn(t) = Σakφk(fo, t) =-= (1
).

Note that φ(f, t) has a period of 1. / f is a periodic orthogonal basis function.

The higher-order term in equation (1) is caused by random noise such as reset noise of the reset transistor 7 and l/f noise. The desired CCD signal output Vna(t) corresponding to the n-th pixel is the CC at the n-th pixel in FIG.
The fundamental frequency of the DCC output voltage n(t) is f. (k=1
), it corresponds to Vna(t)=:an,φ(f,,t)・12).

The amplitude V amp (n) is Vamp (n) = an, ... (
3) is an operator that takes the norm.

As a result, the desired CCD output signal amplitude amp(n
) transfers the nth section of the CCD output waveform and locks the frequency f. It can be obtained from equation (3) by determining the first-order expansion coefficient, that is, an in equation (1) when it is expanded into an orthogonal function with respect to t as a fundamental wave. fo
In principle, lower frequency components (including DC components) are also removed when formula (1) is defined.

Next, the fundamental frequency f is determined from equation (1). A method for extracting only the components will be described. From equation (1), the fundamental frequency component (f
. ) To find the expansion coefficient of
-(4)=C number δmn.

However, T=1/f C=constant δmn=Kronecker symbol Here, the interval T [t, t+1/f. ] Consider the following integral over .

C(n)=G""Vn(t)φ, (f., t)d t
・(5) However, f. : Transfer lock frequency Vn(t) : CCD output voltage in interval n Substituting equation (1) into equation (5), considering equation (4), C(n)=a n, -(6 ), that is, the desired COD output signal amplitude V amp(n ) is V
amp(n)=Ic(n)l=
−(7).

Now, if we expand t in equation (1) to a discrete value sequence and the integral in (5) to Σ, we get Vn(iΔ1)=Σank−φk(f'e+1Δt)−
(8), C(n)=ΣVn(iΔt)φ+(fe+lΔt)−(
9)-0 However, MΔt=T=3-/f.

becomes.

As mentioned above, the CCD output voltage shown in equation (1) can be set to N
M pieces of data are sampled at intervals Δ within an interval corresponding to each pixel. Vamp(n) is determined independently for each of the N pixels using equations (7) to (9). This Vamp(n) becomes the desired COD output signal.

Note that φ(f..

Since f 61 Δ is also known, the term iΔt) is V
It can be calculated as a weight function for n (iΔt). However, it is generally assumed that orthogonal basis functions are extended to complex functions. For orthogonal basis functions, CC
Considering the shape of the D output waveform, trigonometric functions, Walsh functions, etc. can be considered.

However, if trigonometric functions are chosen as orthogonal basis functions, φ−
n (t,) = e x p i (2πn f, t)
=-(LO).

Next, the operation will be explained based on a block diagram (see FIG. 1) of a signal output detection system using the method described above.

The output waveform read from the CCDI is sent to the A/D converter 10.
is converted into digital data by This digital data is sent to the arithmetic processing circuit 13. Also, ROM12
In equation (9), φ, (f., iΔt) (i=o
,l.

M-1> is stored as a table. In this embodiment, N types of orthogonal basis function sequences of φj (f., iΔt) to φ^ (f,, iΔt) are stored. Then, in the arithmetic processing circuit 13, the calculation of equation (9) can be executed using the digital data sent from the A/D converter 10 and the arbitrary orthogonal function sequence 11 read from the ROM 12, thereby eliminating reset noise. and a CCD output signal from which random noise has been removed.

Effects of the Invention The present invention provides a charge-coupled device having a gated charge integration type output circuit that outputs an amplitude signal corresponding to a reference potential and a signal charge every cycle of a transfer clock pulse. An A/D conversion circuit that converts the amplitude signal into a digital signal is provided, and an orthogonal function sequence having a predetermined periodic orthogonal basis function is selected based on the iMr digital signal sent from the A/D conversion circuit. Since an arithmetic processing circuit that extracts only the output signal representing the signal charge is provided, the influence of random noise such as reset noise and 1/f noise generated by the reset transistor in a charge-coupled device having a gated charge integration type output circuit is reduced. It is possible to detect the output signal of a charge-coupled device that eliminates the noise, and in this case, the signal is digitally processed by using an A/D conversion circuit, which improves processing accuracy and allows for detailed processing. ' It is possible to obtain a high quality output signal.

In addition, by using the periodic orthogonal basis functions recorded in the orthogonal function sequence table in the storage unit, it is possible to adjust the transfer lock waveform of the charge-coupled device and the smoothing of the output waveform due to the high capacitance impedance of the charge-coupled device itself. Accordingly, an optimal periodic orthogonal function (trigonometric function, Walsh function, etc.) can be selected, thereby enabling high-quality detection of the output signal of the charge imaging element.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing an embodiment of the present invention, Fig. 2 is a waveform diagram showing the sampling timing of the CCD output signal, Fig. 3 is a flowchart, and Fig. 4 is a waveform diagram showing the waveform of the CCD output signal. , FIG. 5 is a circuit diagram showing the output circuit of the COD. 1... Charge coupled device, 10... A/D conversion circuit, 1
1...Orthogonal function sequence, 12...Storage unit, 13...Arithmetic processing circuit Z diagram Applicant: Ricoh Co., Ltd.

Claims (1)

[Claims] 1. A charge-coupled device having a gated charge-integrating output circuit that outputs an amplitude signal corresponding to a reference potential and a signal charge every cycle of a transfer clock pulse; A/A converting the amplitude signal into a digital signal;
A D conversion circuit and an orthogonal function sequence having a predetermined periodic orthogonal basis function are selected from this storage section, and only an output signal representing the signal charge is extracted based on the digital signal sent from the A/D conversion circuit. 1. A charge-coupled device signal detection circuit comprising: an arithmetic processing circuit; 2. The signal detection circuit for a charge-coupled device according to claim 1, further comprising a storage section including a plurality of orthogonal function sequences in which periodic orthogonal basis functions are stored.