JPH0315351B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to the structure of a static type semiconductor memory device, and mainly relates to improving the characteristics of a device using a GaAs substrate.

Static RAM uses a bistable flip-flop circuit as a memory cell, and stores information by setting one of the stable states to "1" and the opposite to "0". Therefore, information is stored as long as power is supplied.

Figure 1 shows the cell configuration of static RAM. The memory cells are transistors _T1 to _T4 that form a flip-flop and an address selection transistor.
It consists of T ₅ and T ₆ elements. The figure shows an example in which a flip-flop is configured with an E/E type inverter in which the driver is an enhancement type and the load is an enhancement type. Depending on the load configuration, there is an E/D type made with a depletion type, a CMOS static type made with CMOS, and an E/R type where the load is formed with a resistor. Each cell basically consists of six elements.

The basic operation of the memory cell shown in FIG. 1 will be explained. It is assumed that this cell is selected by the address signal. At this time, T ₅ and T ₆ are conductive, and T ₁ , T ₂ , T ₃ ,
Read the state of the flip-flop (F/F) consisting of _T4 . Assuming that _T2 is now ON and _T1 is OFF, node A is at O potential and node B is at _VDD level. Therefore, H level and L level are read to the data line and data line D, respectively.

On the other hand, to invert the F/F, select this cell using the address signal as described above, write H level to D and L level to D, _T1 conducts but becomes non-conductive, F/F inverts and the address By making the line non-conductive, node B maintains L level and node A maintains H level.

T ₅ and T ₆ transistors read memory cells,
Since it functions as a write switch, it is desirable that it operate at high speed and occupy a small area in order to enable high integration.

Also, since a large number of memory cells are connected to the data lines D and D, the coupling capacitance becomes large.
The T ₅ and T ₆ transistors need to have high driving capability.

In view of the above-mentioned points, the present invention has been proposed in a static semiconductor memory device constructed using a substrate such as GaAs, in which an address selection transistor is formed in a minimum area and is made into a bipolar transistor, and data lines D and D are connected to each other. The purpose of this is to prevent the current driving ability from decreasing even when a large number of memory cells are connected.

An embodiment of the present invention is shown in FIG. In Figure 2, the memory cells have MESFETs at Q ₁ , Q ₂ , Q ₃ , and Q ₄
The address selection transistors Q ₅ and Q ₆ are bipolar transistors. It is assumed that this cell is selected by the address signal. now
When _Q2 is ON and _Q1 is OFF, node C is at O potential and node D is at _VDD level. Therefore, H level and L level are read to the data line and data line D, respectively. On the other hand, in order to invert this F/F, select this cell using the address signal as described above, write H level to D and L level to D, then node D becomes L level and node C becomes H level.
Q ₁ turns ON, Q ₂ turns OFF, F/F is inverted, and the address line becomes non-conductive, causing node D to go to L level.
Node C maintains H level.

FIG. 3 is a sectional view of an integrated circuit according to an embodiment of the present invention, focusing on Q ₂ , Q ₆ , Q ₁ , and Q ₅ . MESFETs Q ₁ and Q ₂ have sources and drains 3-1 and 3-2, gates 5, and channel regions 4, respectively. In the bipolar transistors Q ₅ and Q ₆ , 3-2 is the emitter, 3-3 is the collector, and 2 is the base. The base region of transistor 2 is connected to the address line, and the emitter 3-3 of the transistor is connected to data lines D, D.

FIG. 4 shows a method of forming the IC structure shown in FIG. In FIG. 4, 1 is a semiconductor substrate, and a P substrate having a semi-insulating resistivity is usually used. After forming the insulating film 10 on the entire surface of the substrate, a resist film 20 is applied using a mask. After patterning the region 2, the region 2 is formed by P-type ion implantation. Using the same procedure, the insulating film 10 and the resist 21 are again patterned to form the region 4, and n ^- ions are implanted to form the channel region, forming the region 4. Continuing to Figure 4 (C)
As shown in Figure 3, perform n ⁺ ion implantation 〇c.
-1, 3-2, and 3-3 areas are formed. MESFETs and bipolar transistors are formed by covering the entire area with an insulator and heat-treating it. In FIG. 4(d), ohmic contact is made, the insulating film 30 is etched, and the short key gate 50 and internal wiring are completed.

The bipolar transistor according to the present invention is 3-
These are NPN transistors with 2, 2, and 3-3 serving as an erector, a base, and an emitter, respectively.The base 2 is connected to an address line, and the emitter 3-3 is connected to a data line. The current gain, which is the figure of merit of a bipolar transistor, is determined between 3-2 and 3-3.As is clear from the structure, since the bipolar transistor is formed in self-alignment, an extremely large value can be obtained. Further, 3-2 is the drain of the MESFET and serves as the collector of the bipolar transistor. Since the address selection transistor can be constructed by simply adding 2 and 3-3, the construction area can be significantly reduced compared to the conventional construction.

Furthermore, the transistors consisting of 3-2 and 3-3 are so-called lateral NPN transistors, and even if 3-2 is used as an emitter and 3-3 is used as a collector, the basic operation remains the same, and the bidirectionality required for an address selection transistor is maintained. Needless to say, the quality is another advantage of this configuration.

As is clear from the above description, the present invention
In a static type semiconductor memory circuit using a GaAs substrate other than the above, an address selection transistor can be configured by simply adding at least two diffusion layers, and the cell area can be reduced. In addition, there is the advantage that the conventional problem of increased data line capacitance due to increased capacity can be compensated for by the driving ability of bipolar transistors, and that the symmetry of irreversible characteristics can be idealized by using lateral NPN transistors. .

[Brief explanation of drawings]

FIG. 1 is a block diagram used in a semiconductor static RAM whose substrate is mainly GaAs other than Si. FIG. 2 is a block diagram of a semiconductor static RAM showing an embodiment of the present invention, where Q ₁ , Q ₂ , Q ₃ , and Q ₄ are
MESFET, _Q5 , _Q6 bipolar transistor.
V _DD is a power supply, V _DD is ground, and D and D are data lines. FIG. 3 shows an embodiment of the present invention.
In the IC cross-sectional diagram, 1 is the first conductivity type substrate, and 2 is the first conductivity type region. 3-1, 3-2, and 3-3 are second conductivity type regions. 4 is a channel region of the second conductivity type, and 5 is a gate region. FIG. 4 is an explanatory diagram showing a specific configuration method of the present invention, 1, 2, 3-1, 3-2,
3-3, 4, and 5 are the same as in FIG. 3, 10 is an insulating film, 20 and 30 are resist films for patterning, 40 is a metal region for Schottky gate and internal wiring, and 50 is a metal region for internal wiring. Ohmic contact to the diffusion region, ○A shows P-type ○B shows n ^- type ○C shows n-type ion implantation.

Claims (1)

[Scope of Claims] 1 It has first, second, third, and fourth transistors, the gate of the first transistor is the drain of the second transistor, and the gate of the second transistor is the drain of the second transistor.
Connected to the drain of the transistor, the first and second
The sources of the transistors are commonly grounded and the third,
The source of the fourth transistor is connected to the drain of the first and second transistors, and the gate and drain are connected to the power supply in common, and the memory state of the flip-flop is transferred to the data line and the data line by an address selection signal. Fifth,
a sixth transistor, the bases of the fifth and sixth transistors are connected to the address line, the collector of the fifth transistor is connected to the drain of the first transistor and the source of the third transistor, and the collector of the sixth transistor is connected to the second transistor. A semiconductor memory device characterized in that the drain of the transistor is connected to the source of the fourth transistor, and the outputs of the emitters of the fifth and sixth transistors are connected to a data line and a data line. 2 The emitter of the fifth transistor is the drain of the first transistor and the source of the third transistor, the emitter of the sixth transistor is the drain of the second transistor and the source of the third transistor, the collector outputs of the fifth and sixth transistors are the data line, A semiconductor memory device according to claim 1, which is connected to a data line. 3. The semiconductor memory device according to claim 1, wherein the third and fourth transistors are constructed of resistors. 4 First, second, third, and fourth transistors
2. The semiconductor memory device according to claim 1, wherein the MESFET and the fifth and sixth transistors are bipolar NPN transistors. 5. The semiconductor memory device according to claim 1, wherein the drains of the first and second transistors and the emitter or collector of a bipolar transistor are shared. 6 The first, second, third, and fourth transistors
2. The semiconductor memory device according to claim 1, wherein the MESFET and the fifth and sixth transistors are bipolar lateral transistors. 7. The semiconductor memory according to claim 1, wherein GaAs is used as the semiconductor substrate, and the emitters or collectors of the fifth and sixth transistors are formed simultaneously when the drains and sources of the first and second transistors are formed. Device.