JPH0636315B2 - Semiconductor memory - Google Patents

Description

Description: FIELD OF THE INVENTION The present invention relates to a semiconductor memory, and more particularly to a memory combining bipolar and CMOS.

[Background of the Invention]

Currently, the most frequently used semiconductor static RAM (random access memory) includes a bipolar type memory and a CMOS type memory. Representative examples of those memory cells are shown in FIGS. 1 (a) and 1 (b), respectively.

Bipolar static RAM is currently the fastest RA
Although it is M, as is well known, it consumes a large amount of power. On the other hand, CM
The OS RAM has low power consumption but relatively slow access time.

[Object of the Invention]

It is an object of the present invention to provide a RAM which has an access time comparable to that of a bipolar RAM and consumes only as much power as a CMOS.

[Outline of Invention]

To achieve this object, the present invention provides a memory cell
It is composed of a bipolar transistor (hereinafter, abbreviated as bipolar T _r ) and a MOS transistor (hereinafter, MOST _r ). That is, by using the bipolar _Tr in the output stage of the memory cell, the load driving capability is increased and the stray capacitance of the bit line can be charged and discharged at high speed. Therefore, the operation of the memory cell becomes faster. Further, the flip-flop portion is constituted by MOST _r . This allows
Current flows through the bipolar T _r only when switching signal, the other time determines the current consumption of the entire memory cell flowing by the current flowing through the MOST _r, it can be suppressed power consumption low.

Example of Invention

 The principle of the present invention will be described below with reference to examples.

Although FIG. 2 generally shows the internal configuration of the memory LSI, the present invention is also configured by such an internal circuit. Reference numerals 21 and 23 are address decoder circuits, each of which is composed of an address buffer a and partial decoder circuits b and c. As a decoder circuit, a circuit including two stages of partial decoders is shown in this example.
Of course, it is also possible to configure with a single stage decoder. An example of such a decoder for 4 addresses is shown in FIG. 31 is an address input, 32 is a decoder output,
a is a buffer, and b is a decoder circuit. In FIG. 2, 22 is a memory cell array, 24 is a sense circuit, 25 is a read / write control circuit, and 26 is an output buffer circuit. As shown below, in the present invention,
A composite circuit of bipolar and CMOS is used for all of these circuits or almost all circuits except special circuits. As a result, the advantages of both high speed of bipolar and low power consumption of CMOS can be realized at the same time.

First, the memory cell will be described. FIG. 4 shows a memory cell according to an embodiment of the present invention. The storage of binary information is CM
Similar to the OS memory cell (Fig. 1 (b)), p-MOS4
1 and 42 and n-MOSs 43 and 44. The bipolar _Tr 45, 46 interfaces the memory cell with the digit lines 47, 48.

The principle of operation of this memory cell will be described with reference to FIG. Reference numeral 50 is the memory cell shown in FIG. To select one of the memory cells 50, the driver 52 sets one of the word lines 63 to a high level. The other unselected word lines are kept low. If this low level is V _EE , the lower word line 64 should be kept below V _EE . This voltage may be applied from the outside, but it may be generated on the chip as is often used in the MOS dynamic RAM. Alternatively, the lower word line may be connected to V _EE and the low level of the driver 52 may be set to a level higher than V _EE .

On the other hand, the digit lines 62 and 62 'are kept at a high level when not selected, and the current source is connected only to the selected digit line. Therefore, a high level appears on one of the selected digit lines 62 and 62 'according to the stored information of the memory cell at the intersection with the selected word line, and a low level appears on the other. This voltage level is configured by the sense circuit 53, amplified by the output buffer 54, and output outside the chip. Writing is performed by supplying a write current larger than the read current to the selected memory cell. An example of a circuit for performing such reading and writing is shown as 51, 51 '(the same circuit as 51). A circuit composed of the bipolar T _r 55, the MOST _r 57, 58, and the resistor 56 is the read circuit (of course, the upper bipolar T.
_A CMOS inverter may be added before _r and an input that is not an inverter may be added on the lower side. ). When not selected, a high level is applied to the input 65, and the digit line 62 is kept at a high level. When selected, a low level is applied to input 65, turning on bipolar _Tr 59.
At this time, a current determined by the resistor 56 flows from the high-level bipolar transistor T _{r of the} memory cell. On the other hand, on the low level side, the digit line 62 is at a low level, so that no current flows. In addition, writing is performed by the read / write circuit 5
Writing is performed by setting one of the input terminals 51 and 51 '(depending on the write information) to a low level 66 and forcibly flowing a large write current. When writing is performed, the digit line becomes low level, so that no writing current flows. Further, in writing, it is preferable to turn off the read current because writing can be performed faster if no read current is passed. Such an embodiment will be described later. Further, in order to perform writing at high speed, it is better that the potential V _EE ′ of the writing circuit is lower than the potential of the lower word line. It was but connexion, V _EE 'or a lower than V _EE, or V _EE' of V
It is better to make it equal to _EE and switch the lower word line to a slightly higher level during writing. An example of a circuit therefor is shown as 55. If an appropriate voltage is applied as V,
The lower word line 64 can be set to an appropriate level during writing. In addition, a bipolar and CMO which will be described later as this circuit.
A buffer circuit combining S may be used.

Although the basic operation of the memory of the present invention has been described above, various embodiments will be described in detail below.

FIG. 6 is another memory cell embodiment of the present invention. In this embodiment, the emitter follower transistor 6
The collectors 63, 64 of 1, 62 are connected to the voltage source, not to the word line. This voltage source may be of any design convenience, but it is usually convenient to connect it to the most positive voltage source V _CC . In that case, it is not necessary to separate the n ⁺ buried amount of the collector of the bipolar _Tr (which is connected to the n layer of the pMOS) from the n ⁺ buried layer of the memory cell belonging to the adjacent word line, and the area of the memory cell can be reduced. Can be made smaller. Further, since the n ⁺ layer is not connected to the word line, the load on the word line is lightened and the speed can be increased.

FIG. 7 and FIG. 8 are the memory cells of FIG. 4 and FIG. 6, respectively.
This is an example replaced with 441. In these embodiments, the p-well for the nMOS is not necessary, so that the entire cell array can be configured with only the n-well, and the memory cell can be miniaturized. Particularly, in the embodiment shown in FIG. 8, it is not necessary to separate n wells between adjacent words, so that the entire cell array can be formed in one n well, which is suitable for high integration. Similarly, a memory cell in which the pMOS is replaced with a resistor is possible, but it is more convenient to configure the pMOS and the resistor to sufficiently supply the base current of the bipolar _Tr and reduce the power consumption.

9 and 10 show an embodiment of a memory cell in which the memory cell of FIGS. 4 and 7 is improved to facilitate writing. In these embodiments, the bipolar T
Resistors 451 and 461 are connected to the collectors of _r 45 and 46, respectively. The values of the resistors 451 and 461 are set so that the read current has a small voltage drop, and the write current having a larger value causes a voltage drop such that the bipolar _Tr is almost saturated or completely saturated. Therefore, at the time of writing, a sufficiently large base current flows, so that the writing characteristics are improved. Of course, although not shown, the improvements shown in FIGS. 9 and 10 can be similarly made to the embodiment shown in FIG. 6 or 8.

Figure 11 and Figure 12 is a ninth view and a tenth further embodiment having an improved memory cell of Figure, bipolar T _r
Shottky barrier diodes 400 and 401 are connected between the collectors and bases of 45 and 46, respectively.
Therefore, although the bipolar _Tr is not saturated with respect to the write current, a sufficient write current is supplied to the MOST _r , so that the write time can be shortened. Further, since the saturation of the bipolar _Tr is prevented, the write cycle time can be shortened. This improvement is also shown in FIG. 6 or 8.
It goes without saying that the embodiment shown in the figure can be similarly applied.

FIG. 13 shows an embodiment in which the memory cell of FIG. 4 is actually laid out. The numbers in the figure correspond to the numbers in FIG.

Further, the area (a) in the drawing is metal wiring (first layer), and the area (b) is polycrystalline silicon.

Thick line 51 is an n-type well of the silicon, two pMOS41,42 therein and two bipolar _T r 45,4
6 is formed. On the other hand, a thick line 52 indicates a p-type well, in which two nMOSs 43 and 44 are formed. G _P is the gate of the pMOS and is made of polycrystalline silicon. pMOS41 is formed with a central source region _{S P,} of the left gate and drain region _{D P,} whereas, PMOS 42 is formed in the center of the source region _{S P} and the gate _{G P} and the right drain region _{D P} ing. Word lines 40, the common source region _{S P} output both pMOS
And an n ⁺ buried layer (not shown in the drawing, which exists from the left to the right in the drawing with the thickness of the arrow on the left side of the drawing) disposed below the n well 51. The bipolar T _r 45 is formed by using the n ⁺ buried layer below the n well as a collector, sharing the drain of the pMOS 41 as a base region, and forming the emitter region E therein.
The base is pulled out through the base contact hole B on the lower side of the emitter E in the drawing. On the other hand, the bipolar _Tr 46
Are similarly formed in the drain region of the pMOS 42. Although not shown, the digit line is a second-layer wiring and is arranged in the vertical direction in the figure, and is connected to the emitter of the bipolar transistor _Tr through an interlayer connection hole. on the other hand,
The nMOS 43 has a source region S _n and a drain region D on the left side.
_The nMOS 44 is formed between the source region S _n and the right drain region D _n . The connections between each device are made with polycrystalline silicon and first as shown.
It is made of metal wiring.

FIG. 14 shows the memory cell of FIG. 13 on the lines aa 'and b-.
A sectional view taken along the line b'is shown. The metal wiring and polycrystalline silicon are indicated by the same symbols (a, b) as in FIG. Region B is an insulating layer, C is an n ⁻ layer, D is an n ⁺ buried layer, and E is a substrate. The second layer wiring and the insulators between the first and second layers are omitted. The plan view of the embodiment of FIG. 6 is also similar to that of FIG. 13, except that only the layout of the n ⁺ buried layer d is different from that of the embodiment of FIG. 4, and the n ⁺ buried layer is only under the p well 52. not exist. In cross section,
In the n ⁺ buried layer D, a broken line portion is added in addition to the solid line portion in FIG. 14b. That is, since the n ⁺ buried layer D is connected to the entire lower portion of the memory cell array, a region for isolation is unnecessary, and the memory cell area can be reduced.

FIG. 15 shows an embodiment in which the memory cell shown in FIG. 7 or 8 is actually laid out. In this figure, the pMOS is arranged similar to that of FIG. 13, except that the resistors (indicated by the symbol of resistance) 300 and 301 are formed of polycrystalline silicon instead of the nMOS. It is connected. Although the n ⁺ buried layer is not shown,
In the case of the figure, only below the pMOS as in FIG. 13, and in the case of FIG. 8, the entire lower surface of the memory cell (in this case,
Unlike the case of the memory cell of FIG. 6, the p-well is unnecessary, so that the window is not necessary in the n ⁺ buried layer.

FIG. 16 is another embodiment of the memory cell of the present invention. In this embodiment, pMOSs 160 and 161 are respectively connected to the bases of the bipolar _Tr 61 and 62,
The word line 40 is selected when a low level signal is applied. Further, nMOS may be used instead of the pMOSs 160 and 161, and in that case, the word line is selected by a high level signal. The collector of the bipolar T _r is connected to a voltage source (V _CC is preferred).

FIG. 17 is an improved circuit of the memory cell of FIG.
When bipolar _T r 61, 62 is turned off, respectively nMOS162,163 is added to rapidly discharge the electric charge accumulated on the base region and the like. Of course, 16
Even if the pMOS and nMOS of 0 to 163 are replaced with each other (as long as the selection level is changed to the high level), the same operation can be performed.

FIG. 18 shows an nMOS4 forming a flip-flop.
In this embodiment, the resistors 3, 441 are replaced with resistors 3, 441, respectively. Also in this case, the pMOSs 160 and 161 are n
It can be replaced with a MOS, but if it is a pMOS, the pMOS and the bipolar T which form the flip-flop are replaced.
_Since it can be formed in the same well as _r , a very small memory cell can be realized.

FIG. 19 shows a memory cell which is an improvement of that of FIG. 18, in which the nMOS 16 is used for the charge discharge of the bipolar _Tr 61, 62, respectively.
2,163 have been added.

FIG. 20 shows an embodiment in which the writing speed of the memory cell shown in FIG. 16 or 17 is increased, and the bipolar _Tr 61,6 is used.
Resistors 164 and 165 are added to the second collector.
Further, in order to prevent the saturation of the bipolar _Tr 61,62, the Schottky barrier diodes 166,167 may be connected. These operations are the same as those described with reference to FIGS. 9 to 12.

FIG. 21 shows an embodiment in which the writing speed of the memory cell shown in FIG. 18 or 19 is increased, and the function thereof is the same as that of FIG.

Next, an embodiment of the peripheral circuit will be described with reference to the drawings.

In FIG. 2, the input buffer decoder part (21, 23)
May use any known circuit. For example, as an input buffer circuit, when the input level is ECL, a conversion circuit from ECL to CMOS (for example, IS
SCC Dig.Tech.Papers. Pp248-249, 192
8), and when the input is TTL, one or two stages of ordinary CMOS gates may be used. Further, other gates can be configured by using, for example, a CMOS gate or a gate circuit in which CMOS and bipolar are combined (see, for example, Japanese Patent Application No. 57-116771 or Japanese Patent Application No. 57-135143). To drive a line having a particularly large load capacitance in a memory circuit, it is convenient to use a circuit combining bipolar and CMOS.

Next, an embodiment of the read / write circuit (a part of 24 in FIG. 2 and 51 in FIG. 5) will be described.

FIG. 22 is a practical embodiment of the circuits 51 and 51 'of FIG. 5 and associated circuits. As for the circuit 51, only the circuit selected by the address decoder output 67 is operated in this embodiment. Therefore, the buffer circuit composed of the CMOS 57, 58 and 61, 62 in FIG. 5 is configured to have a 2-input gate in this embodiment. The decoder output 67 becomes high level when not selected and low level when selected, and the circuit 51 performs the same operation as described with reference to FIG. 5 when selected. As long as the signal 67 is at the non-selected high level, the digit line 62 is kept at the high level regardless of the levels of the signals R (65) and W0 (66), and the memory cell connected to 62 is It is kept unselected. Circuit 51 '
Also has exactly the same configuration as 51, but the input is W1 (6
6 ') is different. Signals R, W0, W1
In the read state, R is at low level and W0 and W1 are at high level. In the written state, R is at a high level (although it may be a low level as described above, but a high level is preferable for high-speed writing), and either W0 or W1 is set according to 1,0 of the write information. High level and the other is set to low level. Circuit 68 is part of the decoder circuit,
Shown as a CMOS 3-input gate, with 6 inputs
An input address signal 69, which has been partially decoded in advance, is applied as 9. However, circuit 6
No. 8 is not included in the present invention. For example, any input gate may be used (this is a design problem), and a gate circuit combining bipolar and CMOS may be used. Good.

By the way, in the read state, one of the digit lines 62 and 62 'is at a high level and the other is at a low level according to the stored information in the memory cell. In the embodiment of FIGS. 5 and 22, a read current flows through the transistor 59 of the circuit 51 connected to the high level during the read period. FIG. 23 shows an embodiment in which this point is improved.
The gate consisting of S57 and S58 has been changed to a 3-input gate, one of which has a buffer (inverter) 7
Inversion information of the digit line 62 'is applied via 2'. Now, it is assumed that the memory cell of the information in which the digit line 62 is high level and 62 'is low level is read.

If the digit line 62 is at a high level, the output of the buffer 72 will be at a low level, and T _r 59 'in 71' will be turned on, so that the digit line 62 'will be rapidly discharged to a low level. If the digit line 62 'goes low, the buffer 7
The 2'output goes high and the bipolar _Tr 59 is turned off. Therefore, if one of the digit lines becomes completely high level and the other becomes low level, the read current no longer flows. Note that, in FIG. 23, the read circuit portions 71 and 71 'of the circuits 51 and 51' of FIG.
Although shown only, it goes without saying that a write / write circuit (not shown) is also required as a read / write circuit.

FIG. 24 shows an embodiment of the sense circuits 53 and 53 'and the output buffer 54 shown in FIG. In this embodiment, the sense circuit includes an inverter composed of CMOS 531, 532, an emitter follower transistor 533 and its current source 5.
35, and a level clamp transistor 534 (this transistor is not necessary for CMOS or TTL output). Date lines 62, 62 '
Since only one of the selected pairs is low and all the others are high, an inverter is required for wired or OR in the EMITA follower.
In addition, this inverter also has a role of amplification. Because of the inverter, the output of the emitter-follower transistor 533 is wired-or because only one of the selected digit lines has a high level and the rest have a low level.

The output circuit 54 is a circuit that generates an ECL output, and is the same circuit as an ECL output circuit of a normal bipolar memory. An output inhibit signal at the time of writing is applied to the input 541. Further, the clamp circuit 534 clamps the sense output to the input amplitude required for the current switch of the output circuit to increase the speed, but it is not always necessary.

FIG. 25 is an embodiment of the current source 535 used in FIG. a) is a current source based on the bipolar _Tr 301, and b) is a current source based on the MOS _Tr 302.
c) is a current source that is a combination of a bipolar 303 and CMOSs 304 and 305, and is a sense line (53 in FIG. 24).
When 0) becomes a low level, no current flows, and power consumption can be reduced. The resistor 300 is for determining the current when the sense line is at a high level.

FIG. 26 shows TTL or CMOS (Bi CMO
It is an embodiment of a circuit for outputting the S) level. Although bipolar _T r 542 and 543 are cascaded to a totem pole type, one high-level sense lines 530, 530 ', since the other is at a low level, the transistor 541 is not turned on simultaneously . The transistors 541 and 542 are CMOSs 544 and 545, respectively.
And 546 and 547.

In FIG. 27 (a), the transistors 542 are replaced with 542-1, 5
42-2 is an example in which the Darlington-Emitta-follower of 2-2 is brought close to the conventional TTL output.

FIG. 27B shows a CMOS 544 instead of using the Darlington emitter resistor 540 of FIG.
545 and Darlington first stage 542-1 to Bi-C
The MOS composite circuit (542-1, 551 to 554) is replaced with the inverter 550. By adopting this circuit form, the current constantly flowing through the resistor can be saved, and the accumulated charge can be rapidly drawn from the base of the output transistor when it is turned off, and the speed can be increased.

In FIG. 27 (c), the lower transistor 543 of the output stage totem pole transistor is replaced by the MOS transistor 54.
3'replacement to lower the output level to a more original T
Can approach TL levels.

The inverter circuit 550 shown in FIGS. 27 (b) and (c),
It goes without saying that any known inverter circuit may be used as 551 (for example, Japanese Patent Application No.
-116771 or Japanese Patent Application No. 57-135142). Further, it goes without saying that any non-inverter type buffer circuit (for example, Japanese Patent Application No. 57-135143) may be used instead of the inverter.

FIG. 28 shows an embodiment in which the output is tri-stated. Therefore, the bipolar circuit of the output circuit is used as a two-input gate, and the chip select signal 590 is applied to one of the two inputs. If the chip select signal 590 is at low level, a signal is output as in FIG. 26.
If the signal 590 is high, the sense lines 530, 53
Transistor 542 regardless of 0'level
Both 543 are turned off. This feature is needed when ORing multiple memory outputs together. It is also possible to prohibit output during writing during writing. To realize this function, a CM that drives a bipolar _Tr
The output inhibition signal may be applied by setting the OS gate to three inputs, or a necessary signal may be generated by applying logic to the chip select signal and the WE signal and applied as the signal 544.

In the embodiments shown in FIGS. 24 to 28, both or one of the emitter-follower currents of the sense circuit is always flowing, but the twenty-ninth embodiment is an embodiment in which the emitter-follower current is not supplied in a steady state. Considering the case where the sense line 530 is at the high level and 530 is at the low level, the bipolar _Tr 535-3 '.
On is 535-3 'is off. But transistor 5
Since the collector of 35-3 'is low level, no current flows in the steady state.

However, in FIG. 29, the CMOS 535-1, 535-
Since the buffer composed of 2 has no amplifying action, there is a possibility that current will flow if the threshold voltage varies. It was improved this point is Figure 30, to prevent this disadvantage by connecting two stages of amplification degree of a high inverter 537-1,537-2 and 536-1,536-2 bipolar _{T r} to drive I'm out.

The read / write control circuit 25 shown in FIG.
It is composed of a combination circuit of CMOS or bipolar CMOS, and generates the R, W0 and W1 signals described in connection with FIG. This circuit can be easily configured by those skilled in the art by appropriately connecting the gates logically, and the configuration itself is not included in the scope of the present invention, and therefore a detailed description thereof will be omitted here.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a conventional type memory cell, FIG. 2 is a diagram showing an internal configuration of a memory LSI, FIG. 3 is a configuration example of a buffer decoder, and FIG. 4 is one embodiment of the memory cell of the present invention. Example, FIG. 5 is an embodiment of the memory structure of the present invention, FIGS. 6 to 12 are diagrams showing other embodiments of the memory cell of the present invention, and FIG. 13 is a diagram of the memory cell of the present invention. Out figure, first
FIG. 4 is a sectional view of the embodiment shown in FIG. 13, FIGS. 15 to 21 are views showing embodiments in which the memory cell of the present invention is laid out, and FIGS. 22 and 23 are read / write of the present invention. FIG. 24 is a diagram showing an embodiment of a circuit, FIG. 24 is an embodiment of a sense circuit and an output circuit of the present invention, FIG. 25 is a view showing an embodiment of the current source of FIG. 24, FIGS. Each of the figures is a circuit diagram showing an output circuit.

Claims (3)

[Claims] 1. A plurality of word lines, a plurality of digit lines provided to intersect the plurality of word lines, and a plurality of memory cells provided at intersections of the plurality of word lines and the plurality of digit lines. A read circuit connected to the digit line, and a write circuit for inputting information to the memory cell by giving desired information to the digit line, wherein the memory cell is composed of a MOS transistor. What is claimed is: 1. A semiconductor memory including a flip-flop having a pair of information storage nodes, for interfacing between the pair of information storage nodes and a pair of digit lines, the base being connected to the pair of information storage nodes, and the pair of digits. The read circuit further comprises a pair of bipolar transistors to which line emitters are connected. At least a first MOS transistor and a first bipolar transistor;
The collector-emitter path of the bipolar transistor is connected to the digit line, the base of the first bipolar transistor is driven by the first MOS transistor, and a read control signal is applied to the gate of the first MOS transistor. During reading, a current drawing operation from the digit line is performed by the collector-emitter path of the first bipolar transistor, and the write circuit includes at least a second MOS transistor and a second bipolar transistor.
The collector-emitter path of the bipolar transistor is connected to the digit line, the base of the second bipolar transistor is driven by the second MOS transistor, and a write signal is applied to the gate of the second MOS transistor, At the time of writing, a current drawing operation from the digit line is performed by the collector-emitter path of the second bipolar transistor, and at the time of non-selection, the read circuit and the write circuit use the first and second MOS transistors to perform the above operation. A semiconductor memory characterized in that the first and second bipolar transistors are cut off. 2. The flip-flop of the memory cell comprises a pair of driving M of a first conductivity type having a gate and a drain cross-coupled with respect to the pair of information storage nodes.
The conductor memory according to claim 1, comprising an OS transistor and a pair of load elements connected between the operating potential point and the pair of information storage nodes. 3. The semiconductor memory according to claim 2, wherein the pair of load elements are a pair of load MOS transistors having a conductivity type opposite to the first conductivity type.