JPH03148921A - Power saving type error correction decoder - Google Patents

Abstract

PURPOSE:To reduce power consumption by providing a detection control part controlling a table in a standby state when all '0' showing the absence of an error by means of a syndrome is detected. CONSTITUTION:The syndrome from a syndrome generator 11 comes to all '0' when an error bit is not included in data. When the detection control part 14 detects all '0', it controls the table 12 in the standby state. If a memory part 17 consists of a non-volatile memory such as a read only memory(ROM), for example, power supplied from a power source part 19 to respective parts is interrupted. Then, the memory part 17 comes to a low power consumption state in a state where error bit position information is stored. if the memory part 17 consists of a dynamic random access memory(DRAM), the supply of power for a decoder 16 and a sense part 18 is stopped and comes to the low power consumption state.

Description

[Detailed Description of the Invention] [Summary] Regarding a power-saving error correction decoder using a table decoding method, the purpose is to reduce the power consumption of a table consisting of a large capacity memory. The error correction decoder reads the error position information from the table using the syndrome as an address, and corrects the error bits of the data in the correction circuit. The present invention is configured by providing a detection control unit that controls the table to be in a standby state when O is detected.

[Industrial application field]

The present invention relates to a power-saving error correction decoder using a table decoding method.

BCH code (Bose-Chaudhuri-Hocq
The ``uenghen+ code'' has the advantage of a large degree of freedom in selecting the coding rate and the number of correctable error bits, but its decoding is performed using algebraic operations and is relatively complex, so it is not suitable for TDMA communication lines, etc. It was thought that it would be difficult to apply it to high-speed communication lines. However, with the development of high-speed memory, a table decoding method that uses a table that stores syndrome patterns and error patterns in correspondence can be applied to BCI (using codes) even in high-speed communication lines. It has become possible to transmit data.Since such a table decoding method uses a relatively large capacity memory, it is desired to reduce its power consumption.

[Conventional technology]

A conventional error correction decoder based on the BCH code table decoding method has, for example, the configuration shown in FIG. 3, where 31 is a syndrome generator, and 32 is a read-only memory (ROM).
33 is a correction circuit, and 34 is a delay circuit.

Input data is applied to a syndrome generator 31 and a delay circuit 34, a syndrome is determined by the syndrome generator 31 according to a generating polynomial, and this syndrome is added to a table 32 as an address. This table 32 is made up of a read-only memory (ROM) and stores bit error position information corresponding to syndromes. The bit error position information read out according to the syndrome from the syndrome generator 31 is sent to the correction circuit
3, and the input data delayed by the delay circuit 34 according to the delay time of each part is applied to the correction circuit 33, and the error bits are corrected. The correction circuit 33 is constituted by, for example, an exclusive OR circuit, and since a pattern with °I°° at the error bit position is read from the table 32, the bit of the input data at the error bit position is inverted and corrected. That will happen.

The BCH code is (a) 1 error correction code, (b) 1 error correction, 2 error detection code, (C) 2 error correction code, (d)
It can be classified into 2 error correction codes, 3 error detection codes, etc. Further, the capacity of the table 32 increases depending on the code length, etc., and for example, in the case of code length 2)5.2 error correction, a capacity of approximately IM bits is required.

[Problem that the invention seeks to solve]

The table 32 is constantly accessed using the syndrome from the syndrome generator 31 as an address. Therefore, even if the input data does not contain a bit error, the table 32 is in an active state and power is consumed. It turns out.

The present invention aims to reduce the power consumption of a table consisting of a large-capacity memory.

[Means to solve the problem]

The power-saving error correction decoder of the present invention puts the table in a standby state when there is no error, and will be explained with reference to FIG.

In an error correction decoder, a syndrome is obtained from data by a syndrome generator 1, error position information is read from a table 2 using this syndrome as an address, and error bits of the data are corrected in a correction circuit 3. A detection control section 4 is provided which controls the table 2 to be in a standby state when the syndrome from "all 0" indicating no error is detected, and 5 is a delay circuit.

[Effect]

If the syndrome from the syndrome generator 1 is all 0'' indicating no error, there is no need to make any errors in the input data, so when the detection control unit 4 detects this all OII, it controls the table 2 to standby state. Since table 2 consumes less power in the standby state, power consumption can be reduced.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 2 is a block diagram of an embodiment of the present invention, in which 10 is a data input terminal, 11 is a syndrome generator, 12 is a table, 13 is a correction circuit, 14 is a detection control section, 15 is a delay circuit, and 16 is a 17 is a memory section, 18 is a sense section, 19 is a power supply section, and 20 is an output terminal.

Data such as data received on a high-speed communication line is applied to the input terminal IO, and is applied to the syndrome generator 11 and the delay circuit 15. Table 12 also shows a case where the decoder 16, memory section 17, sense section 18, and power supply section 19 are configured, and the syndrome from the syndrome generator 11 is reso-coded by the decoder 16, and the memory section 17 is accessed to generate an error. The bit position information is read by the sense section 18 and applied to the correction circuit 13. Further, operating power is supplied from the power supply section 19 to each section.

The syndrome from the syndrome generator 11 is "all 0°" when the data does not contain any error bits, and when the detection control unit 14 detects this all 0°,
Control table 12 to standby state. For example, if the memory section 17 is made of a nonvolatile memory such as a read-only memory (ROM), the power supplied from the power supply section 19 to each section is cut off. As a result, the memory unit 17 enters a low power consumption state while storing the error bit position information. Further, when the memory section 17 is composed of a dynamic random access memory (DRAM), the power supply to the decoder 16 and the sense section 18 can be stopped to achieve a low power consumption state.

Furthermore, when the memory section 17 is composed of a static random access memory (SRAM), the power supply to the decoder 16 and the sense section 18 is stopped, and the memory By lowering the supply voltage to such an extent that the storage contents of the storage section 17 are not lost, a low power consumption state can be achieved.

If the code length of the BCH code is 2)5 and it is a 2 error correction code, the memory section 17 will require a capacity of IM bits, and the power consumption when configured with random access memory (ROM) is , approximately 200 mW. Furthermore, since the error rate of high-speed communication lines is less than 10-'', by setting table 12 to the operating state only when error bits are included, the power consumption becomes less than 2mW.If the line condition is good, , power consumption will be further reduced.

Syndrome generator 11 excluding table 12 in error correction decoder, correction circuit 13. The power consumption of the integrated circuit such as the delay circuit 15 is approximately 200 mW. Therefore, the power consumption as an error correction decoder is about 400 mW, but according to the embodiment of the invention described above, the power consumption can be reduced to about half, about 200 mW.

The present invention is not limited only to the above-mentioned embodiments (
, - can be added and changed, for example,
The present invention can be applied not only to BCH codes but also to Fire codes as block codes that can easily perform burst error correction.

(Effects of the Invention) As explained above, the present invention provides the syndrome generator 1
This system is equipped with a detection control unit 4 that controls the table 2 to standby state when all O's are detected indicating that there is no error in the syndrome from . Since the table 2 is controlled to be in a standby state, such as by turning off the operating power, power consumption can be reduced. In particular, when the error rate of the communication line is small, the number of error bits included in the data is reduced, so the time that Table 2 is in the operating state is greatly reduced, which has the advantage of further reducing power consumption. be.

[Brief explanation of the drawing]

FIG. 1 is a diagram explaining the principle of the present invention, FIG. 2 is a block diagram of an embodiment of the present invention, and FIG. 3 is a block diagram of a conventional example. 2 is a syndrome generator, 2 is a table, 3 is a correction circuit, 4 is a detection control section, and 5 is a delay circuit.

Claims (1)

[Claims] A syndrome is determined from data by a syndrome generator (1), and the syndrome is used as an address to create a table (
In the error correction decoder which reads the error position information from 2) and corrects the error bits of the data in the correction circuit (3), the syndrome from the syndrome generator (1) indicates that there is no error. a detection control unit (4) that controls the table (2) to be in a standby state when detecting 0'';
A power-saving error correction decoder characterized by being provided with.