JPH03148836A - Manufacture of thin film transistor - Google Patents
Manufacture of thin film transistorInfo
- Publication number
- JPH03148836A JPH03148836A JP28756689A JP28756689A JPH03148836A JP H03148836 A JPH03148836 A JP H03148836A JP 28756689 A JP28756689 A JP 28756689A JP 28756689 A JP28756689 A JP 28756689A JP H03148836 A JPH03148836 A JP H03148836A
- Authority
- JP
- Japan
- Prior art keywords
- laser
- polycrystalline silicon
- impurity
- film transistor
- thin film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010409 thin film Substances 0.000 title claims description 13
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 239000012535 impurity Substances 0.000 claims abstract description 17
- 238000000034 method Methods 0.000 claims abstract description 15
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 15
- 239000010408 film Substances 0.000 claims description 17
- 230000007547 defect Effects 0.000 abstract description 8
- 239000000758 substrate Substances 0.000 abstract description 7
- 239000013078 crystal Substances 0.000 abstract description 5
- 238000009792 diffusion process Methods 0.000 abstract description 5
- 239000004065 semiconductor Substances 0.000 abstract description 4
- 238000010438 heat treatment Methods 0.000 abstract description 3
- 238000009413 insulation Methods 0.000 abstract description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract 1
- 229910052710 silicon Inorganic materials 0.000 abstract 1
- 239000010703 silicon Substances 0.000 abstract 1
- WTEOIRVLGSZEPR-UHFFFAOYSA-N boron trifluoride Chemical compound FB(F)F WTEOIRVLGSZEPR-UHFFFAOYSA-N 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 229910015900 BF3 Inorganic materials 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000001678 irradiating effect Effects 0.000 description 2
- 239000000155 melt Substances 0.000 description 2
- 230000015654 memory Effects 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000010410 layer Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000001953 recrystallisation Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Landscapes
- Thin Film Transistor (AREA)
Abstract
Description
【発明の詳細な説明】
【産業上の利用分野〕
本発明は、多結晶シリコンを用いた薄膜トランジスタの
製造方法に関し、レーザドーピング技術を用いた薄膜ト
ランジスタに関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a thin film transistor using polycrystalline silicon, and more particularly to a thin film transistor using laser doping technology.
本発明は、薄膜トランジスタのソース領域およびドレイ
ン領域をセルファライン法によって形成し、レーザドー
ピング技術によって接合を形成する方法である。まず、
ゲート酸化膜とその上に多−結晶シリコンのゲート領域
を形成し、このゲート領域をマスクとして、三弗化硼素
を含むガスの雰囲気中で、短波長のパルスレーザである
エキシマレーザを照射することによって、ソース領域お
よびドレイン領域を形成する工程を含む薄膜トランジス
タの製造方法である。薄膜トランジスタのソース領域お
よびドレインN域の膜厚は500オングストローム以下
にもかかわらず、欠陥の少ない低抵抗の領域を形成する
ことができる。The present invention is a method of forming a source region and a drain region of a thin film transistor by a self-line method, and forming a junction by a laser doping technique. first,
A gate oxide film and a polycrystalline silicon gate region are formed on it, and using this gate region as a mask, an excimer laser, which is a short wavelength pulsed laser, is irradiated in an atmosphere of a gas containing boron trifluoride. This is a method of manufacturing a thin film transistor including a step of forming a source region and a drain region. Even though the thickness of the source region and drain N region of the thin film transistor is less than 500 angstroms, it is possible to form low resistance regions with few defects.
(従来の技術〕
半導体単結晶基板上に、レーザ、特に短波長のパルスレ
ーザであるエキシマレーザを照射して不純物を導入する
、いわゆるレーザドーピング技術を用いて浅い接合を形
成する方法が提案されていた。例えば、CI L D
(Gas Immersion Laser Dopi
n1)と呼ばれるPチャンネルMOSFETの製造方
法があった(IEIEE I!lectron Dev
ice Letters、V。(Prior art) A method has been proposed for forming shallow junctions on a semiconductor single crystal substrate using a so-called laser doping technique, in which impurities are introduced by irradiating a laser, particularly an excimer laser, which is a short-wavelength pulsed laser. For example, C.I.L.D.
(Gas Immersion Laser Dopi
There was a method for manufacturing P-channel MOSFETs called n1) (IEEE I!electron Dev
ice letters, V.
1.9 No、10.1988年542ないし544頁
)。1.9 No. 10. 1988, pp. 542-544).
その製造方法の概略を、第2図aないしCに示す、まず
、第2図aに示すように、半導体単結晶基板1の表面に
、絶縁分離のためのバンド酸化膜2aと窒化膜2bを所
定の領域に形成する。次に、第2図すに示すように、フ
ィールド酸化膜3を形成後、ゲート酸化膜4を形成し、
さらに多結晶シリコンのゲート電極5を形成する。多結
晶シリコ ンのゲート電極の側面を含めて酸化してシリ
コン酸化膜の側壁6を形成してお(,この側壁は、不純
物導入の際、横方向の拡散距離に見合う厚さにしておく
、次に、第1図Cに示すようにソース・ドレインとなる
べき領域の酸化膜を除去した後、例えば三弗化硼素のよ
うな不臓物ガスフを含む雰[気中て、波長が308ナノ
メートルのXeClのエキシマレーザ8を照射しつつ、
ソース領域9aおよびドレイン領域9bにP型の不臓物
を導入する。An outline of the manufacturing method is shown in FIGS. 2a to 2C. First, as shown in FIG. 2a, a band oxide film 2a and a nitride film 2b for insulation isolation are formed on the surface of a semiconductor single crystal substrate 1. Formed in a predetermined area. Next, as shown in FIG. 2, after forming a field oxide film 3, a gate oxide film 4 is formed.
Furthermore, a gate electrode 5 of polycrystalline silicon is formed. The polycrystalline silicon including the side surfaces of the gate electrode is oxidized to form a silicon oxide film sidewall 6 (this sidewall is made to have a thickness commensurate with the lateral diffusion distance when introducing impurities). Next, as shown in FIG. While irradiating with the XeCl excimer laser 8,
P-type impurities are introduced into source region 9a and drain region 9b.
このエキシマレーザを用いた不純物の導入によって浅い
接合を形成することができる。しかし、基板が単結晶の
シリコン基板を用いた場合、浅い接合部分や、フィール
ド酸化膜と接合の境界部分において欠陥が発生しやすい
おそれがあった。A shallow junction can be formed by introducing impurities using this excimer laser. However, when a single-crystal silicon substrate is used as the substrate, there is a risk that defects are likely to occur at shallow junctions or at the boundary between the field oxide film and the junction.
近年、メモり装置の大容量化を実現するために、メモり
回路の負荷抵抗として薄膜トランジスタをすでに形成さ
れたIC素子の上に絶縁膜を設けてその表面にPチャン
ネルのMOSFET等を形成する、いわゆるスタックド
薄膜トランジスタ(以下スタックドTETという)を形
成する構造のメモり装置が提案されていた。In recent years, in order to increase the capacity of memory devices, an insulating film is provided on an IC element on which a thin film transistor has already been formed as a load resistor for a memory circuit, and a P-channel MOSFET or the like is formed on the surface of the insulating film. A memory device having a structure forming a so-called stacked thin film transistor (hereinafter referred to as stacked TET) has been proposed.
(発明が解決しようとする課題〕
前記スタックドTPTのソース領域およびドレイン領域
を形成するには、接合近傍の欠陥が少なく、かつチャン
ネル長に影響を及ぼす接合の移動ができるだけ小さい必
要があった。従来のイオン注入法による不純物の注入を
行えば、非晶質化した注入領域の活性化と再結晶化のた
めに熱処理を必要とし、そのためにランプアニール等が
行われていた。(Problems to be Solved by the Invention) In order to form the source and drain regions of the stacked TPT, it is necessary to have as few defects as possible near the junction and to minimize movement of the junction that affects the channel length. When impurities are implanted using the ion implantation method described above, heat treatment is required to activate and recrystallize the amorphous implanted region, and lamp annealing or the like is required for this purpose.
しかしながら、サブミクロン以下のチャンネル長の短い
スタックドTPTを実現するには、下部に構成したtC
素子への熱の影響を避けるために、低温で局所的な輻射
エネルギーを短時間加え、かつ接合近傍の結晶性を向上
させる必要があった。However, in order to realize a stacked TPT with a short channel length of submicron or less, it is necessary to
In order to avoid the effects of heat on the device, it was necessary to apply local radiant energy at low temperatures for a short period of time and to improve the crystallinity near the junction.
本発明による薄膜トランジスタの製造方法では、短波長
のパルスレーザであるエキシマレ−ザラ用いて、局所的
にソース領域およびドレイン領域をメルトさせてドーピ
ングし、熱処理も同時に行うことによって横方向への拡
散が小さいスタックドTPTを実現することができる。In the method for manufacturing a thin film transistor according to the present invention, an excimer laser, which is a short-wavelength pulsed laser, is used to locally melt and dope the source and drain regions, and heat treatment is also performed at the same time, thereby minimizing lateral diffusion. Stacked TPT can be realized.
本発明による薄膜トランジスタの製造方法では、短波長
のパルスレーザを用いてソースNNiおよびドレイン領
域を照射するとき、ソース領域およびドレイン領域の多
結晶シリコンの膜厚は500オングストローム以下であ
り、レーザ照射によってメルトする深さは、およそ40
0オングストロームであるから、再結晶化に伴う欠陥の
発生も少なく、接合の移動も500オングストローム以
下にすることができる。In the method for manufacturing a thin film transistor according to the present invention, when the source NNi and drain regions are irradiated with a short wavelength pulsed laser, the film thickness of the polycrystalline silicon in the source and drain regions is 500 angstroms or less, and the laser irradiation melts the polycrystalline silicon. The depth is approximately 40
Since the thickness is 0 angstrom, defects caused by recrystallization are less likely to occur, and movement of the junction can be kept to 500 angstrom or less.
本発明の実施例を第1図ahよび第1図すを用いて説明
する。Embodiments of the present invention will be described with reference to FIGS. 1-ah and 1-s.
第1図aに示すように、メモリ等のIc素子をすてに形
成した(図示せず)半導体単結晶基板1の表面に絶縁膜
11を形成する。この絶縁1111は下部のIC素子と
の分離や配線を行うための層間絶縁膜で、通常Sing
膜を用いる。次に、絶縁millの表面にCVD法等に
よって多結晶シリコンli12をおよそ400オングス
トローム成長させる。次に、ゲート酸化114とゲート
電極となるべき多結晶シリコン13を形成して所定のチ
ャンネル長に対応した幅の多結晶シリコンのパターンを
形成する。次に、第1図すに示すように、例えば三弗化
硼素のようなP型の不純物ガスフの雰囲気中で、XeC
lのエキシマレーザ8を照射する。エキシマレーザ8の
照射によって、多結晶シリコン層12はメルトし、ソー
ス領域14aおよびドレイン領域14bに不純物がメル
ト領域以内に導入される。所定のエキシマレーザの走査
時間によって不純物導入領域の再結晶化が行われるので
、接合部の欠陥の発生は少なくz低抵抗のソース領域1
4aとドレイン領域14bを形成することができる。接
合の深さは、多結晶シリコン膜12の厚さによって制限
されるので、レーザのパワーやパルス幅の変化による影
響は、単結晶基板へのレーザドーピングに比し少ない。As shown in FIG. 1a, an insulating film 11 is formed on the surface of a semiconductor single crystal substrate 1 (not shown) on which IC elements such as memories have been formed. This insulator 1111 is an interlayer insulating film for separating and wiring the IC elements below, and is usually used for Sing.
Use a membrane. Next, approximately 400 angstroms of polycrystalline silicon Li12 is grown on the surface of the insulating mill by CVD or the like. Next, a gate oxide 114 and polycrystalline silicon 13 to become a gate electrode are formed to form a polycrystalline silicon pattern having a width corresponding to a predetermined channel length. Next, as shown in Figure 1, in an atmosphere of a P-type impurity gas such as boron trifluoride,
1 of excimer laser 8 is irradiated. Polycrystalline silicon layer 12 is melted by irradiation with excimer laser 8, and impurities are introduced into the melt regions of source region 14a and drain region 14b. Since the impurity-introduced region is recrystallized by a predetermined scanning time of the excimer laser, defects at the junction are less likely to occur, and the source region 1 with low resistance is formed.
4a and a drain region 14b can be formed. Since the depth of the junction is limited by the thickness of the polycrystalline silicon film 12, the influence of changes in laser power and pulse width is smaller than in laser doping of a single crystal substrate.
不純物ガスフをゲートの多結晶シリコン13へ同時に導
入し、ゲート電極15とすれば、1度のレーザドーピン
グでソースとドレインおよびゲートを形成することがで
きる。If an impurity gas is simultaneously introduced into the polycrystalline silicon 13 of the gate to form the gate electrode 15, the source, drain, and gate can be formed by one laser doping.
本発明の実施例においては、P型の不純物ガスを用いて
説明したが、N型の不純物ガスであってもよい。Although the embodiments of the present invention have been described using P-type impurity gas, N-type impurity gas may also be used.
〔発明の効果)
本発明による薄膜トランジスタの製造方法によれば、ソ
ース領域およびドレイン領域の膜厚を500オングスト
ローム以下としているので、不純物の横方向拡散が膜厚
以下に抑制され、かつ欠陥の発生が少なく低抵抗のソー
ス領域およびドレイン領域を形成することができるので
ー、リーク電流の小さいfiII膜トランジスタを実現
することができる。[Effects of the Invention] According to the method for manufacturing a thin film transistor according to the present invention, since the film thickness of the source region and the drain region is set to 500 angstroms or less, the lateral diffusion of impurities is suppressed to the film thickness or less, and the generation of defects is prevented. Since it is possible to form a source region and a drain region with a small amount of low resistance, it is possible to realize a fiII film transistor with a small leakage current.
第1図aおよび第1図すは本発明の薄膜トランジスタを
製造する工程図、第2図a乃至第2図Cは従来のMOS
FETを製造する工程図である。1A and 1A are process diagrams for manufacturing the thin film transistor of the present invention, and FIGS. 2A to 2C are conventional MOS
It is a process diagram of manufacturing FET.
Claims (1)
成し、該ゲート領域を不純物導入に対するマスクとして
、不純物ガスの雰囲気中で短波長のパルスレーザを照射
することによって、ソース領域およびドレイン領域を形
成する工程を含む薄膜トランジスタの製造方法。A gate region is formed on the surface of a polycrystalline silicon layer on an insulating film, and the source region and drain region are irradiated with a short wavelength pulsed laser in an atmosphere of impurity gas, using the gate region as a mask for impurity introduction. A method for manufacturing a thin film transistor, including a step of forming it.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP28756689A JPH03148836A (en) | 1989-11-06 | 1989-11-06 | Manufacture of thin film transistor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP28756689A JPH03148836A (en) | 1989-11-06 | 1989-11-06 | Manufacture of thin film transistor |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH03148836A true JPH03148836A (en) | 1991-06-25 |
Family
ID=17718999
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP28756689A Pending JPH03148836A (en) | 1989-11-06 | 1989-11-06 | Manufacture of thin film transistor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH03148836A (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06104196A (en) * | 1991-10-04 | 1994-04-15 | Semiconductor Energy Lab Co Ltd | Manufacturing method for semiconductor device |
US5938839A (en) * | 1991-10-04 | 1999-08-17 | Semiconductor Energy Laboratory Co., Ltd. | Method for forming a semiconductor device |
US6323069B1 (en) | 1992-03-25 | 2001-11-27 | Semiconductor Energy Laboratory Co., Ltd. | Method of manufacturing a thin film transistor using light irradiation to form impurity regions |
US6424008B1 (en) | 1992-10-30 | 2002-07-23 | Semiconductor Energy Laboratory Co., Ltd. | Memory device having a floating gate |
US6683350B1 (en) | 1993-02-05 | 2004-01-27 | Semiconductor Energy Laboratory Co., Ltd. | Transistor and method for manufacturing the same |
-
1989
- 1989-11-06 JP JP28756689A patent/JPH03148836A/en active Pending
Cited By (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06104196A (en) * | 1991-10-04 | 1994-04-15 | Semiconductor Energy Lab Co Ltd | Manufacturing method for semiconductor device |
US5938839A (en) * | 1991-10-04 | 1999-08-17 | Semiconductor Energy Laboratory Co., Ltd. | Method for forming a semiconductor device |
US6660575B1 (en) | 1991-10-04 | 2003-12-09 | Semiconductor Energy Laboratory Co., Ltd. | Method for forming a semiconductor device |
US6919239B2 (en) | 1991-10-04 | 2005-07-19 | Semiconductor Energy Laboratory Co., Ltd. | Method for forming a semiconductor device |
US6323069B1 (en) | 1992-03-25 | 2001-11-27 | Semiconductor Energy Laboratory Co., Ltd. | Method of manufacturing a thin film transistor using light irradiation to form impurity regions |
US6569724B2 (en) | 1992-03-25 | 2003-05-27 | Semiconductor Energy Laboratory Co., Ltd. | Insulated gate field effect transistor and method for forming the same |
US6887746B2 (en) | 1992-03-25 | 2005-05-03 | Semiconductor Energy Lab | Insulated gate field effect transistor and method for forming the same |
US6424008B1 (en) | 1992-10-30 | 2002-07-23 | Semiconductor Energy Laboratory Co., Ltd. | Memory device having a floating gate |
US7622343B2 (en) | 1992-10-30 | 2009-11-24 | Semiconductor Energy Laboratory Co., Ltd. | Laser processing method, method for forming a flash memory, insulated gate semiconductor device and method for forming the same |
US6683350B1 (en) | 1993-02-05 | 2004-01-27 | Semiconductor Energy Laboratory Co., Ltd. | Transistor and method for manufacturing the same |
US7011993B2 (en) | 1993-02-05 | 2006-03-14 | Semiconductor Energy Laboratory Co., Ltd. | Transistor and method for manufacturing the same |
US7394130B2 (en) | 1993-02-05 | 2008-07-01 | Semiconductor Energy Laboratory Co., Ltd. | Transistor and method for manufacturing the same |
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