JPH03145820A - Pll circuit - Google Patents

Abstract

PURPOSE:To prevent a fault of a VCO by providing separately a frequency comparator to a PLL circuit and using a frequency comparator to pull in a said oscillating frequency into a lock range when the oscillating frequency is largely deviated. CONSTITUTION:A frequency comparator 4 compares the frequency of a reference signal Ss with the frequency of an output signal Sv and outputs a control voltage CV2 in response to the difference to a gate circuit 5. When the frequency fIN and the oscillating frequency fV of an input signal SIN is deviated largely in excess of a lock range, a gate circuit 5 supplies selectively a control voltage CV2 outputted from a frequency comparator 4 to a loop filter 3. Thus, the circuit of loop L2 controls so that the frequency fV approaches the reference frequency fS. When the fV enters the lock range, the gate circuit 5 applies the control voltage CV1 outputted from the phase comparator 2 selectively to the loop filter 3.

Description

[Detailed Description of the Invention] "Industrial Application Field" This invention is a P
Regarding the LL circuit.

"Prior Art" PLL circuits have traditionally been used in communication equipment, control equipment, etc., and operate so that the oscillation frequency of the VCO (voltage controlled oscillator) in the circuit is always equal to the frequency of the input signal. This is a circuit that does this.

The conventional PLL circuit described above will be explained with reference to the block diagram shown in FIG. In this figure, first, when the input signal SIN is not supplied, vco t
oscillates at a free-running frequency (oscillation frequency fV), and this oscillation signal Sv is supplied to the phase comparator 2. Next, when the input signal SIN of frequency f rw is supplied to the phase comparator 2, the phase or frequency of the input signal Srs and the oscillation signal Sv are compared, and a control voltage Cv corresponding to the difference is output. . After high frequency components and noise are removed from this control voltage Cv by a loop filter (for example, L P F , low-pass filter) 3,
Supplied to VCOI. Then, the oscillation frequency fv of VCOf is controlled by this control voltage C■,
Oscillation signal S equal to frequency f'+N of human input signal S IN
v is supplied to the phase comparator 2 mentioned above.

By the above operation, the vCOILy3 oscillation frequency fv always follows the frequency f+N of the input signal.

In addition, in order to improve frequency tracking (pulling), a phase frequency comparator (PFC) is used as the phase comparator 2. , circuits etc. In this case, human power signal 5
The comparison between i11 and the oscillation signal Sv is performed based on phase and frequency.

"Problem to be solved by the invention" By the way, in the conventional PLL circuit shown in Fig. 2, ■CO
No equivalent countermeasures have been taken for abnormalities (stopping of oscillation, occurrence of side lock, etc.). Another problem is that convergence to the frequency of the input signal is relatively slow.

Further, in the PL[7 circuit using the above-mentioned phase frequency comparator, the design of the phase frequency comparator is difficult to put into practical use, and the circuit configuration becomes extremely complicated.

This invention was made in view of the above-mentioned problems, and
It can prevent CO abnormalities and has a simple circuit configuration.
Another object of the present invention is to provide a PLL circuit that can be easily designed and that can efficiently shorten convergence time.

"Means for Solving the Problems" In order to solve these problems, the present invention provides an oscillator that generates an oscillation signal with a frequency that corresponds to a supplied control signal, and an externally supplied input signal. A phase comparator that compares the phase with the oscillation signal and outputs a first control signal according to the difference; and a second control signal that compares the frequency of the reference signal and the oscillation signal and outputs a first control signal according to the difference. a frequency comparator that outputs a signal; a switching device that selectively outputs either the first control signal or the second control signal;
a filter means for filtering the first control signal or the second control signal outputted by the switching means and then supplying the filtered signal to the oscillator, and when the frequency of the oscillation signal is within a lock range, The switching means selectively outputs the first control signal, and when the frequency of the oscillation signal is outside the lock range, the switching means selectively outputs the second control signal. do.

[“Operation”] When the frequency of the oscillation signal is outside the lock range, a loop circuit consisting of a frequency comparator, a switching means, a filter means, and an oscillator adjusts the frequency of the oscillation signal so that it matches the frequency of the reference signal. Control the frequency of the oscillation signal.

Also, if the frequency of the oscillation signal is within the lock range,
A loop circuit including a phase comparator, a switching means, a filter means, and an oscillator controls the frequency of the oscillation signal so that the frequency of the oscillation signal matches the frequency of the input signal.

F Embodiment J Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In this figure, parts corresponding to the parts of the conventional example shown in FIG. 2 are designated by the same reference numerals, and the explanation thereof will be omitted.

In this figure, 4 is a frequency comparator, and one input terminal of the comparator is supplied with a constant frequency reference signal S5 outputted from an oscillation circuit (not shown). Here, the frequency of this reference signal Ss is set as the reference frequency fs, and the frequency of the human signal SIN is f
It shall be equal to IN. Note that this reference signal Ss is
A system clock or the like may also be used. Further, the other input terminal of the frequency comparator 4 is connected to the output signal S from the vcoi.
v is supplied. This frequency comparator 4 uses a reference signal Ss
and the output signal Sv, and outputs a control voltage CVt to the gate circuit 5 according to the difference.

This gate circuit 5 is also supplied with a control voltage CVI from the phase comparator 2. Gate circuit 5 selectively outputs either control voltage CV + or control voltage CV t to loop filter 3 . Here, phase comparator 2 -> gate circuit 5 - loop filter 3
-VCOI→Loop circuit consisting of loop filter 3
It is assumed that the circuit is 1. Also, the frequency comparator 4-gate circuit 5
A circuit consisting of -.loop filter 3 -.VCOI and frequency comparator 4 is assumed to be a loop L2 circuit.

Next, in the above-described configuration, if the human input signal S is not supplied, the VCOI first oscillates at a free-running frequency. Next, when the human input signal S++i is supplied, the phase comparator 2 compares the phases of the human input signal S IN and the oscillation signal Sv, and outputs a control voltage CV to the gate circuit 5. Further, the frequency comparator 4 compares the frequencies of the reference signal S5 and the oscillation signal Sv, and outputs the control voltage CVt to the gate circuit 5. In this case, the frequency flN of the human input signal SIN and the oscillation frequency fv greatly deviate beyond the lock range, so the gate circuit 5
is the control voltage CV output by the frequency comparator 4
t is selectively supplied to the loop filter 3.

Therefore, if it is outside the lock range, loop L 2
The circuit controls the oscillation frequency fv to approach the reference frequency fs. Then, when the oscillation frequency fv approaches the reference frequency fs and enters the lock range, the gate circuit 5 outputs the control voltage CV output from the phase comparator 2.
+ is selectively supplied to the loop filter 3. Therefore, when the oscillation frequency fv falls within the lock range, the oscillation frequency fv is controlled by the circuit of the loop Ll and is finally locked to the frequency frs.

Next, when the lock state is released due to a disturbance or the like and the oscillation frequency fv deviates from the lock range, the gate circuit 5 controls the control voltage Cv from the frequency comparator 4,
is selectively supplied to the loop filter 3. Therefore, when it is out of the lock range, the circuit of loop L2 operates the oscillation frequency f of the VCOI in the same manner as described above.
v is controlled and brought back into lock range. Then, when the oscillation frequency fv returns to within the lock range, the locked state is maintained again by the loop L+ circuit.

Further, in the abnormal stop state of the vcoi, the loop L2 circuit using the frequency comparator 4 performs a recurrent oscillation operation.

"Effects of the Invention" As explained above, according to the present invention, a frequency comparator is separately provided in the PLL circuit consisting of a phase comparator, a loop filter, and a VCO, and when the oscillation frequency deviates significantly, the frequency comparison is performed. In order to pull the oscillation frequency into the lock range using a device and control the VCO using a phase comparator when the oscillation frequency falls within the lock range,
It is possible to prevent vCO abnormalities, to have a simple circuit configuration, to facilitate design, and to efficiently shorten the convergence time.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.
FIG. 2 is a block diagram showing the configuration of a conventional PLL circuit. 1... VCO (oscillator), 2... Phase comparator, 3... Filter means (loop filter), 4... Frequency comparator, 5... ...Switching means (gate circuit).

Claims (1)

[Claims] An oscillator that generates an oscillation signal with a frequency corresponding to a supplied control signal, and a phase that compares the phase of an externally supplied input signal with the oscillation signal and outputs a first control signal according to the difference. a comparator; a frequency comparator that compares the frequencies of the reference signal and the oscillation signal and outputs a second control signal according to the difference; a switching means for selectively outputting either a first control signal or a second control signal outputted by the switching means;
filter means for filtering the first control signal and then supplying the first control signal to the oscillator, and when the frequency of the oscillation signal is within a lock range, the switching means selectively outputs the first control signal. The PLL circuit is characterized in that, when the frequency of the oscillation signal is outside the lock range, the switching means selectively outputs the second control signal.