JPH03131035A - Large scale integrated circuit - Google Patents

Abstract

PURPOSE:To prevent the mixing of noises and a malfunction due to currents of an internal logic gate by using a separate system as the power supply of an input buffer and the internal logic gate. CONSTITUTION:A NOR gate composed of P channel MOS transistors P1, P2 and N channel MOS transistors N1, N2 represents an input buffer circuit, an input terminal IN is connected to a bonding pad for an input, and another input CONT represents a control input from internal logic gates. An output from the NOR gate is input to an inverter consisting of P3 and N3 at a CMOS level, and an output from the inverter is buffered by inverters at two stages made up of P4 and N4 and P5 and N5, and connected to the internal logic gates. The gate bonded with a power supply V1 and a ground wiring G1 thereof in these gates is shaped only in the NOR gate, and the logic gates after an inverter at the next stage is connected to a power supply V2 and a ground wiring G2 thereof.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to large-scale integrated circuits, and in particular to a method for wiring power and ground thereof.

[Conventional technology]

Semiconductor memory devices, which have a large number of logic gates and memory cells mounted on a chip, are increasing in capacity year by year, and as a result, high circuit density and low power consumption are required, and circuit configurations based on CMO3 are attracting attention. This semiconductor memory device usually has memory cells arranged in the center of the chip, and an address decoder circuit, a control circuit, and a buffer for input/output with external circuits arranged around the chip. In particular, the external input buffer has a logic threshold determined according to the TTL output voltage on the assumption that it will be interfaced with TTL, and its output is connected to an internal logic gate whose input and output are CMOS levels, and a high-power buffer The power supply and ground wiring for both logic gates were common.

[Problems to be Solved by the Invention] However, in the above-mentioned conventional technology, when a large number of logic gates switch simultaneously, a large current flows from the power supply wiring through the logic gates to the ground wiring, the potential of the former wiring decreases, and conversely, the potential of the latter wiring decreases. The potential of increases. If the input voltage of the input buffer is specified at the TTL level, especially when the latter ground wiring potential increases, the signal potential will decrease relatively.
In some cases, it may be determined that the input signal has changed from the "H" level to the "L" level, which may result in malfunction.

The present invention is intended to solve these problems, and its purpose is to suppress malfunctions of high-power buffers caused by fluctuations in the potential of the power supply wiring and ground wiring due to the operation of internal logic gates. The company provides integrated circuits.

[Means to solve the problem]

In the large-scale integrated circuit of the present invention, the power supply wiring and the ground wiring of the input buffer are provided independently from the power supply wiring and the ground wiring of the logic gate, and the same types of wiring of each power supply wiring and each ground wiring are separated from each other. It is characterized in that it is connected at a bonding pad portion around the chip, and is connected from the pad to an external power supply circuit.

[Function] According to the above configuration of the present invention, the power supply for the input buffer is separated from the power supply for the internal logic gates, so that a large number of logic gates simultaneously change from "H" level to "L" level or vice versa. Even if there is a reverse change, the power supply power and ground level of the input buffer do not change, and malfunctions can be suppressed.

[Example] FIG. 1 shows an example of the present invention, and FIG. 2 shows a part of FIG. 1 in an enlarged manner.

In FIG. 1, reference numeral 1 denotes a semiconductor chip, in which a memory cell 2 is formed in most of its center, and a power supply bonding pad 3, a grounding bonding pad 4, and other input/output bonding pads are formed around the periphery. . Also the second
In the figure, 9 is an input buffer circuit, 10 is a logic gate such as an address decoder, 5 and 6 are the power supply and ground wiring for the input buffer, 7 and 8 are the power supply and ground wiring for the logic gate, and 4 is the ground. The ground wires are connected to each other at the bonding pad.

As can be seen from Figure 1, the power supply wiring for the input buffer and logic gate are also connected in the same way at the power supply bonding pad, and the power supply and ground wiring for the input buffer are different from the power and ground wiring for the logic gate. The circuit components are separated.

An example of the circuit from the input buffer to the first stage of the internal logic gate is shown in Figure 3.
The NOR gate composed of P2 and N-channel MOS transistors N1 and N2 is a large-power buffer circuit, and its input terminal IN is connected to an input bonding pad, and the other input C0NT is a control input from an internal logic gate. The input threshold voltage of the NOR gate is its MO
Due to the size of the S transistor, the input IN is set to the TTL level, and the input C0NT is similarly set to the CMOS level because the internal logic circuit operates at the CMOS level. NO
The output of the R gate is at CMOS level and is input to the impark formed by P3 and N3, and the output is further input to P
4.N4 and P5.N5 are buffered by a two-stage inverter and connected to an internal logic gate. Only the NOR gate, which is an input buffer, is connected to the power supply 1 and its ground wiring G, and the logic gates after the inverter in the next stage of the NOR gate are connected to the power supply v2 and its ground wiring G2. connected to.

According to the present invention, the power supply for the logic gates, which are composed of a large number of gates, is separated from the power supply for the input buffer.
Even if the level or vice versa changes, the power and ground levels of the large-capacity buffer do not change, and there is no risk of malfunction.

[Effect of the Invention 1] As described above, according to the present invention, by providing separate power supplies for the input buffer and the internal logic gate, it is possible to prevent noise intrusion and malfunction due to the current of the internal logic gate. By providing means for avoiding the adverse effects of the current of the internal logic gates in this manner, a simple circuit can be used for the input buffer, and the input buffer itself can achieve lower power consumption and faster operation.

Furthermore, when the power supply or ground wiring is routed, one side is shielded from the other, and there is an effect that crosstalk does not occur. Further, by applying a configuration in which the power supply and ground wiring are separated, the degree of freedom in the layout, which has been limited by the malfunction of the input buffer, is greatly improved.

[Brief explanation of the drawing]

FIG. 1 is a schematic plan view showing an embodiment of the present invention, FIG. 2 is an enlarged plan view of a portion thereof, and FIG. 3 is a circuit diagram showing a circuit example of a portion of an input buffer and an internal logic gate. l...Semiconductor chip 2...Memory cell 3...4...4...5...6...7...7...8...9...・ ・ ・ 10 ・ ・ ・ ・ P 1 to P5 N 1 to N5 ・Ponding pad for ti source ・Bonding pad for ground ・Power supply wiring for input buffer ・Ground wiring for large power buffer ・Power supply wiring for internal logic gate ・Internal logic Gate ground wiring, large power buffer circuit section, internal logic gate section, P channel MOS transistor, N channel MOS transistor and above

Claims (1)

[Claims] In a large-scale integrated circuit that is composed of a large number of logic gates and includes a semiconductor chip provided with an input buffer between the logic gates and an external circuit, the power supply wiring and ground wiring of the input buffer are connected to the power supply of the logic gates. Each wiring and ground wiring are provided independently, and the same type of wiring of each power wiring and each ground wiring is connected to each other at the bonding pad part around the chip, and from this pad to the external power supply circuit. Features large-scale integrated circuits.