JPH029449B2 - - Google Patents
Info
- Publication number
- JPH029449B2 JPH029449B2 JP57223052A JP22305282A JPH029449B2 JP H029449 B2 JPH029449 B2 JP H029449B2 JP 57223052 A JP57223052 A JP 57223052A JP 22305282 A JP22305282 A JP 22305282A JP H029449 B2 JPH029449 B2 JP H029449B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- substrate
- sio
- silicon oxide
- oxide film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000000758 substrate Substances 0.000 claims description 29
- 238000010438 heat treatment Methods 0.000 claims description 20
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 7
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 7
- 238000004519 manufacturing process Methods 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 4
- 239000011229 interlayer Substances 0.000 claims description 3
- 230000008021 deposition Effects 0.000 claims 2
- 239000010408 film Substances 0.000 description 52
- 229910004298 SiO 2 Inorganic materials 0.000 description 27
- 238000004544 sputter deposition Methods 0.000 description 22
- 239000010410 layer Substances 0.000 description 10
- 238000000034 method Methods 0.000 description 10
- 238000010586 diagram Methods 0.000 description 4
- 238000001755 magnetron sputter deposition Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 238000005224 laser annealing Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 238000001552 radio frequency sputter deposition Methods 0.000 description 1
- 238000005546 reactive sputtering Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
- C23C14/06—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the coating material
- C23C14/10—Glass or silica
Landscapes
- Chemical & Material Sciences (AREA)
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Materials Engineering (AREA)
- Mechanical Engineering (AREA)
- Metallurgy (AREA)
- Organic Chemistry (AREA)
- Formation Of Insulating Films (AREA)
Description
【発明の詳細な説明】
〈技術分野〉
本発明はスパツタリング法によつて酸化シリコ
ン(以下SiO2と略記する)膜を作成するための
製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION <Technical Field> The present invention relates to a manufacturing method for forming a silicon oxide (hereinafter abbreviated as SiO 2 ) film by a sputtering method.
〈従来技術〉
集積回路が高密度化するにつれて、パターンが
微細化すると共に多層配線や積層構造が用いられ
るようになり、半導体回路素子の構造が非常に複
雑になつて、絶縁膜としてのSiO2や窒化膜にも
厳しい特性が要求されるようになつてきた。この
ような高密度集積回路素子に用いるSiO2は最近
ではスパツタリング法によつて作成することが多
い。しかし従来から行われているスパツタリング
法によつて作成したSiO2膜は、作成後の熱処理
で膜の内部応力が大きく変化したり、またSiO2
膜を堆積している基板にソリを生じさせ、なかに
は基板から剥離して所期の目的を達成し得ない事
態がしばしば生じていた。<Prior art> As the density of integrated circuits increases, patterns become finer and multi-layer wiring and laminated structures are used, making the structure of semiconductor circuit elements extremely complex, and the use of SiO 2 as an insulating film. Strict properties are now being required for nitride films and nitride films. Recently, SiO 2 used in such high-density integrated circuit elements is often produced by a sputtering method. However, SiO 2 films created by the conventional sputtering method may have a significant change in the internal stress of the film due to heat treatment after creation, or the SiO 2
This often causes the substrate on which the film is deposited to warp, and some films peel off from the substrate, making it impossible to achieve the intended purpose.
SiO2膜が単に半導体基板表面を被う保護膜と
してや、1〜2層程度の比較的少ない積層構造か
らなる多層配線用の層間絶縁膜として利用してい
る限りでか、上記のような従来方法によつて作成
した膜でも利用することができる。しかし集積度
の飛躍的な向上のもとに開発が進められている積
層高密度集積回路素子のデバイス間に介挿する絶
縁膜としては、上記従来方法によつて作成した
SiO2膜では問題がある。 As long as the SiO 2 film is used simply as a protective film covering the surface of a semiconductor substrate or as an interlayer insulating film for multilayer interconnection consisting of a relatively small stacked structure of one or two layers, the above-mentioned conventional Membranes prepared by this method can also be used. However, the insulating film inserted between the devices of laminated high-density integrated circuit elements, which are being developed due to the dramatic increase in the degree of integration, cannot be fabricated using the conventional method described above.
There are problems with SiO 2 films.
即ち第1図は従来から提案されている積層高密
度集積回路素子の断面図で、実際には更に多層に
積層されるが、図が複雑になるのを避けるため集
積回路デバイス10,20を2層に積層した例を
示す。シリコン基板11に不純物拡散領域12,
12等を作成し、適宜配線13によつて電気的接
続を施こした第1層目のデバイス10上に、第2
デバイス20を積層するが、両デバイス10,2
0間にはデバイス間の電気的絶縁を図るために絶
縁膜30を介挿する。回路を作成した第1層目デ
バイス10上に絶縁膜30を被着した後、第2層
目デバイス20のためのポリシリコン膜21を形
成し、該ポリシリコン膜21内の一部の領域にレ
ーザー光を照射してレーザーアニールによつて上
記ポリシリコンを単結晶化する。単結晶化した領
域にP或いはN型の不純物を導入して回路素子を
作成し、第2層目デバイス20を作成する。同様
に第2層目デバイス20上にも絶縁膜を介して順
次集積回路デバイスを積層し、少なくとも5層以
上にデバイスを積層して非常に集積度の高い三次
元回路素子とする。 That is, FIG. 1 is a cross-sectional view of a laminated high-density integrated circuit device that has been proposed in the past.In reality, it is laminated in many more layers, but in order to avoid complicating the diagram, the integrated circuit devices 10 and 20 are separated by two. An example of stacked layers is shown. Impurity diffusion region 12 in silicon substrate 11,
12, etc., and the second
Although the devices 20 are stacked, both devices 10 and 2
An insulating film 30 is inserted between 0 and 0 in order to electrically insulate the devices. After depositing the insulating film 30 on the first layer device 10 on which the circuit has been created, a polysilicon film 21 for the second layer device 20 is formed, and some areas within the polysilicon film 21 are The polysilicon is made into a single crystal by irradiation with laser light and laser annealing. A P or N type impurity is introduced into the single crystallized region to create a circuit element, and a second layer device 20 is created. Similarly, integrated circuit devices are sequentially stacked on the second layer device 20 via an insulating film, and the devices are stacked in at least five layers to form a three-dimensional circuit element with a very high degree of integration.
上記積層高密度集積回路素子において、各層の
デバイスを作成する過程でしばしば熱工程や熱処
理が必要になる。しかしデバイス間に介挿する絶
縁膜は上記ような熱処理やその他の作業環境に晒
しても変形したりデバイス表面から剥離してはな
らない。そのためにはデバイス表面に作成した絶
縁膜は、膜作成後の熱工程や熱処理によつて内部
応力が変化しないことが望ましい。しかし従来の
スパツタリング方法によつて作成したSiO2膜は
薄膜中の内部応力が熱処理中に変化し、そのため
に膜自身に亀裂が入つたり、SiO2膜を堆積した
シリコン基板が変形する等の不都合があつた。 In the above-described laminated high-density integrated circuit element, a thermal process or heat treatment is often required in the process of creating devices in each layer. However, the insulating film interposed between the devices must not be deformed or peeled off from the device surface even when exposed to the above-mentioned heat treatment or other working environments. To this end, it is desirable that the internal stress of the insulating film formed on the device surface does not change due to thermal processes or heat treatments after the film is formed. However, in SiO 2 films created by conventional sputtering methods, the internal stress in the thin film changes during heat treatment, resulting in cracks in the film itself or deformation of the silicon substrate on which the SiO 2 film is deposited. There was an inconvenience.
〈発明の目的〉
本発明は上記従来の製造方法によつて作成した
SiO2膜の問題点に鑑みてなされたもので、熱工
程や熱処理に拘わらずスパツタリング時の内部応
力はほとんど変化しない熱的に安定なSiO2膜を
得ることができる製造方法を提供することであ
る。<Object of the Invention> The present invention is directed to the manufacturing method produced by the above-mentioned conventional manufacturing method.
This was done in view of the problems with SiO 2 films, and by providing a manufacturing method that can obtain a thermally stable SiO 2 film whose internal stress hardly changes during sputtering regardless of the heat process or heat treatment. be.
〈実施例〉
マグネトロンスパツタリング装置の反応槽に設
けられた相対向する電極の一方にSiO2を含む、
SiO2基板等の被スパツタ材料をセツトし、他方
の電極に、SiO2膜を堆積すべき集積回路デバイ
ス基板をセツトする。集積回路デバイス基板をセ
ツトした電極側は加熱手段を備え、スパツタリン
グ中の基板を所定温度に加熱保持する。各電極に
材料をセツトした後反応槽内に所定の不活性ガス
を導入し、電極間に電源を供給する。スパツタリ
ング装置の稼動によつて高周波電圧が電極間に印
加され、被スパツタリング材料から飛び出した
SiO2膜作成のための分子或いは原子が基板表面
に堆積し、基板表面にSiO2薄膜を作成する。<Example> One of the opposing electrodes provided in the reaction tank of a magnetron sputtering device contains SiO 2 ,
A material to be sputtered such as a SiO 2 substrate is set, and an integrated circuit device substrate on which a SiO 2 film is to be deposited is set on the other electrode. The electrode side on which the integrated circuit device substrate is set is equipped with a heating means to heat and maintain the substrate at a predetermined temperature during sputtering. After setting the materials on each electrode, a predetermined inert gas is introduced into the reaction tank, and power is supplied between the electrodes. When the sputtering equipment operates, a high frequency voltage is applied between the electrodes and the voltage is ejected from the sputtering material.
Molecules or atoms for creating a SiO 2 film are deposited on the substrate surface, creating a SiO 2 thin film on the substrate surface.
第2図は、マグネトロンスパツタリング法によ
つて作成したSiO2膜の内部応力とスパツタリン
グ時の基板温度との関係を、スパツタリング後の
熱処理条件をパラメーターとして図示したもので
ある。ただしスパツタリング時の高周波パワー密
度はいずれも5.5W/cm2に設定してSiO2膜が作成さ
れている。図において曲線Aはスパツタリングに
よつて基板上に堆積した後特に熱処理を施こして
いないSiO2膜について、曲線Bはスパツタリン
グ後600℃で1時間の熱処理を施こしたSiO2膜、
曲線Cはスパツタリング後800℃で1時間の熱処
理を施こしたSiO2膜について、夫々スパツタリ
ング中の基板保持温度によつてどのように膜の内
部応力が変化するかを測定したものである。図か
ら明らかなように、曲線A,B,Cは基板温度約
200℃近傍でほぼ同程度の内部応力を示し、これ
は基板温度を選ぶことによつてスパツタリング後
の熱処理に拘わらず膜の内部応力が変化しないこ
とを示し、熱的に安定なSiO2膜が得られたこと
を示す。熱的に安定な内部応力をもつSiO2膜を
作成する基板温度は、上述の約200℃に限られる
ものではなく、スパツタリング時のRFパワー密
度によつて変化する。RFパワー密度によつて選
ぶべき基板温度は変化するが、スパツタリング時
の電気的条件に対応して基板温度を選ぶことによ
り、熱処理による膜の内部応力の変化はほとんど
なく、安定したSiO2膜になる。 FIG. 2 illustrates the relationship between the internal stress of a SiO 2 film produced by magnetron sputtering and the substrate temperature during sputtering, using the post-sputtering heat treatment conditions as parameters. However, the high-frequency power density during sputtering was set at 5.5 W/cm 2 to create the SiO 2 film. In the figure, curve A is for a SiO 2 film that has been deposited on a substrate by sputtering and has not been subjected to any particular heat treatment, and curve B is for a SiO 2 film that has been heat treated at 600°C for 1 hour after sputtering.
Curve C is a measurement of how the internal stress of the SiO 2 film that was heat-treated at 800° C. for 1 hour after sputtering changes depending on the substrate holding temperature during sputtering. As is clear from the figure, curves A, B, and C are at approximately the substrate temperature.
The internal stress of the film was approximately the same at around 200℃, which indicates that the internal stress of the film does not change regardless of the heat treatment after sputtering, depending on the substrate temperature . Show what you got. The substrate temperature for creating a thermally stable SiO 2 film with internal stress is not limited to the above-mentioned approximately 200°C, but varies depending on the RF power density during sputtering. The substrate temperature that should be selected changes depending on the RF power density, but by selecting the substrate temperature according to the electrical conditions during sputtering, there is almost no change in the internal stress of the film due to heat treatment, and a stable SiO 2 film can be obtained. Become.
上記のような結果に基づいて、マグネトロンス
パツタリング法によりRFパワー密度5.5W/cm2、
基板温度200℃で形成したSiO2膜を、温度を変え
て1時間熱処理したところ、第3図に示すように
熱処理温度に拘わらず膜の内部応力は変化せずほ
ぼ一定値のままであつた。このように熱によつて
内部応力が変化しないSiO2膜は、高密度集積回
路素子のデバイス間絶縁膜として非常に好都合で
ある。 Based on the above results, the RF power density was 5.5W/cm 2 by magnetron sputtering method,
When a SiO 2 film formed at a substrate temperature of 200°C was heat-treated for 1 hour at different temperatures, the internal stress of the film did not change and remained at a nearly constant value, regardless of the heat treatment temperature, as shown in Figure 3. . The SiO 2 film, whose internal stress does not change due to heat, is very suitable as an inter-device insulating film for high-density integrated circuit elements.
尚上記実施例はマグネトロンスパツタリング法
を用いてSiO2膜を作成する場合を挙げたが、DC
スパツタ法、RFスパツタ法、或いは反応性スパ
ツタ法でも同様に本発明を適用することができ
る。 In the above example, the SiO 2 film was created using the magnetron sputtering method, but DC
The present invention can be similarly applied to the sputtering method, the RF sputtering method, or the reactive sputtering method.
〈効果〉
以上、本発明のようにスパツタリング反応槽内
のRFパワー密度とスパツタ膜形成用基板の温度
を設定することにより、基板上に堆積したSiO2
膜は、スパツタリング後の熱工程や熱処理等加熱
によつて内部応力が変化することのない安定した
膜となるため、堆積した基板にも無理な力が作用
せず、また、膜自体に亀裂が生じることも無くな
り、高密度集積回路素子のデバイス間絶縁膜とし
て非常に優れた膜を提供でき、ひいては信頼性の
高い素子の製造を可能にできる。<Effects> As described above, by setting the RF power density in the sputtering reaction tank and the temperature of the substrate for sputtering film formation as in the present invention, SiO 2 deposited on the substrate can be reduced.
The film becomes a stable film whose internal stress does not change due to heat treatment or heat treatment after sputtering, so no excessive force is applied to the substrate on which it is deposited, and no cracks occur in the film itself. This eliminates the occurrence of this phenomenon, making it possible to provide an extremely excellent film as an inter-device insulating film for high-density integrated circuit devices, thereby making it possible to manufacture highly reliable devices.
従つて、積層される集積回路素子のデバイス間
の層間絶縁膜として、後工程の加熱による悪影響
を受けない膜を供給することが可能となつて、信
頼性の高い積層高密度集積回路素子を提供するこ
とが可能になる。 Therefore, it is possible to provide a film that is not adversely affected by post-process heating as an interlayer insulating film between devices of stacked integrated circuit elements, providing a highly reliable stacked high-density integrated circuit element. It becomes possible to do so.
第1図は積層高密度集積素子の概略断面図、第
2図は本発明を説明するための熱処理条件をパラ
メーターにして測定した基板温度と内部応力との
関係図、第3図は本発明を説明するための膜の内
部応力と熱処理温度との関係を示す図である。
Fig. 1 is a schematic cross-sectional view of a laminated high-density integrated device, Fig. 2 is a diagram of the relationship between substrate temperature and internal stress measured using heat treatment conditions as parameters to explain the present invention, and Fig. 3 is a diagram showing the relationship between substrate temperature and internal stress measured using heat treatment conditions as parameters to explain the present invention. FIG. 2 is a diagram showing the relationship between internal stress of a film and heat treatment temperature for explanation.
Claims (1)
路素子のデバイス間に層間絶縁膜として酸化シリ
コン膜を形成する際、 設定されたRFパワー密度及び種々の基板温度
下において、酸化シリコン膜を基板上に堆積し、
この酸化シリコン膜に更に種々の温度下で熱処理
を施して、いずれの熱処理温度においても前記酸
化シリコン膜の内部応力がほぼ同一となる堆積温
度を予め特定し、 該特定された堆積温度及び上記の設定された
RFパワー密度下にて所望基板上に酸化シリコン
膜を形成することを特徴とする酸化シリコン膜の
製造方法。[Claims] 1. When forming a silicon oxide film as an interlayer insulating film between devices of integrated circuit elements stacked on a substrate in multiple layers, under a set RF power density and various substrate temperatures. , depositing a silicon oxide film on the substrate,
This silicon oxide film is further subjected to heat treatment at various temperatures, and a deposition temperature at which the internal stress of the silicon oxide film is almost the same at any of the heat treatment temperatures is determined in advance, and the deposition temperature is set
A method for producing a silicon oxide film, comprising forming a silicon oxide film on a desired substrate under RF power density.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57223052A JPS59114827A (en) | 1982-12-21 | 1982-12-21 | Formation of silicon oxide film |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57223052A JPS59114827A (en) | 1982-12-21 | 1982-12-21 | Formation of silicon oxide film |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS59114827A JPS59114827A (en) | 1984-07-03 |
JPH029449B2 true JPH029449B2 (en) | 1990-03-02 |
Family
ID=16792077
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP57223052A Granted JPS59114827A (en) | 1982-12-21 | 1982-12-21 | Formation of silicon oxide film |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS59114827A (en) |
-
1982
- 1982-12-21 JP JP57223052A patent/JPS59114827A/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS59114827A (en) | 1984-07-03 |
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