JPH0290795A - Time divisional switch control system - Google Patents

Abstract

PURPOSE:To improve flexibility with simple constitution by reading out address information in which data performing the write or readout of a first memory circuit is stored from a second memory circuit, and performing the write/readout of the address information in the first memory circuit stored in the second memory circuit from a control circuit. CONSTITUTION:The second memory circuit 104 performs the readout while the output of a selector 106 is set as that from a counter 108, and performs the write/readout of a content by a controller 109 while the output of the selector 106 is set as that from the controller 109. Also, the write on a temporary memory circuit 105 which designates the addresses of the first memory circuits 100-103 is performed when the address of the second memory circuit 104 is designated by the counter 108. Thereby, it is possible to perform both a sequential write/random read operation and a random write/sequential read operation with simple constitution, and furthermore, to reduce the number of selectors to select the address information to be inputted to the first memory circuits 100-103.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a control method for a time division switch in an exchange.

[Conventional technology]

Conventionally, this type of time-division switch includes first memory circuits OO-103 and 200-203, and second memory circuits 304 and 4, as shown in FIGS. 3 and 4, respectively.
04, first selectors 305 and 405, second selectors 306 and 406, and first counter 307
and 407, second counters 308 and 408, control circuits 309 and 409, signal lines 110 to 113 and 210 to 213 with low multiplicity, and signal lines 114 and 214 with high multiplicity. .

First, in the case of FIG. 3, signals with low multiplicity are sent from the signal lines 110 to 113 to the first storage circuit 10, respectively.
Written to 0-103. Next, each memory circuit 100~
The output from 103 has its multiplicity increased and is further subjected to time slot conversion before being output to signal line 114. Memory circuit 1
Writing and reading control of 00 to 103 is determined by the selection condition of the first selector 305.
When the output is from the first counter 307, the first memory circuits 100 to 103 are in the write state, and
When the output of the selector 305 is the output from the second memory circuit 304, the first memory circuits 100 to 10B are in a read state. Writing and reading control of the second memory circuit 304 is determined by selection conditions of the second selector 306.
When the output of the second selector 306 is the output from the second counter 308, the second storage circuit 304 is in a read state. Further, the output of the second counter 308 becomes the address information of the second memory circuit 304,
The output of 4 becomes address information of the first storage circuits 100 to 103. On the other hand, when the output of the second selector 306 is the output from the control circuit 309, the control circuit 309 reads and writes the contents of the second memory circuit 304, and
Change the contents of 4.

Next, in the case of Fig. 4, the signal with high multiplicity is connected to the signal line 21.
4 to the first storage circuits 200 to 203. At this time, each memory circuit 200 to 20
The internal address of 3 is specified, preparations are made for time slot conversion at the time of output, and the multiplicity is lowered at the time of output and the signal line 2
10 to 213. Writing and continuous output control of the memory circuits 200 to 203 are determined by the selection conditions of the first selector 405. The output of the first selector 405 is
When the output is from the counter 407, the first storage circuits 200 to 203 are in the read state, and the first selector 4
When the output of 05 is the output from the second memory circuit 404, the first memory circuits 200 to 203 are in a write state.

The write/read control of the second memory circuit 404 is determined by the selection condition of the second selector 406, and when the output of the second selector 406 is the output from the second counter 408, the second memory circuit 404 performs read/write control. state. The output of the second counter 408 becomes the address information of the second memory circuit 404, and the output of the second memory circuit 404 becomes the address information of the first memory circuits 200-203. On the other hand, when the output of the second selector 406 is the output from the control circuit 409, the control circuit 409 reads and writes the contents of the second memory circuit 404 and changes the contents of the memory circuit 404.

[Problem that the invention seeks to solve]

In the conventional circuit described above, the first memory circuits 100 to 10
B or 200 to 203, by the time the address information is transmitted, a second counter 308 or 408, respectively,
The delay between the second storage circuit 304 or 404 and the first selector 305 or 405 must be taken into consideration.
As the degree of multiplicity increases, time setting becomes difficult.Although the circuit components are the same in Figures 3 and 4, the first memory circuit in Figure 3 is sequential. However, in the case of Fig. 4, it is a random write/sequential read, so the control of the first selector and second selector is different between the case of Fig. 3 and the case of Fig. 4. It has the disadvantage of being inflexible as it has to be changed.

[Means for solving problems]

The time division switch control method of the present invention includes a first storage circuit that temporarily stores digital audio signals or data, a second storage circuit that stores address information of the first storage circuit, and a second storage circuit that stores address information of the first storage circuit. a temporary storage circuit that temporarily stores the address information output from the second storage circuit and outputs it to the first storage circuit after a predetermined delay time; and a counter that generates the address information of the second storage circuit. , a control circuit that generates address information of the first storage circuit to be sent to the second storage circuit, and a selector that selects either the output of the counter or the address information from the control circuit. It consists of:

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

1 and 2 are block diagrams of embodiments of the present invention, respectively, and FIG. 1 is a case in which the time slots of the plurality of signals with low multiplicity shown in FIG. 3 are exchanged and output as a signal with high multiplicity. , and FIG. 2 corresponds to the case where the high multiplicity signal in FIG. The same reference numerals in FIGS. 3 and 4 indicate the same components. In FIGS. 1 and 2, first memory circuits 100 to 103 and 20 are shown, respectively.
0 to 203, second memory circuits 104 and 204. selectors 106 and 206, counters 108 and 208
, control circuits 109 and 209, and time storage circuits 115 and 215.

The operation of FIGS. 1 and 2 will be explained below. In FIG.
While the output of selector 6 is the output from the counter 108, it is read, and the output of the selector 106 is the output from the control device 109.
The control device 109 reads and writes the contents while the output is being output from the first memory circuits 100 to 10.
The temporary storage circuit 115 that specifies the address No. 3 is written when the address of the second storage circuit 104 is specified by the counter 108.

FIG. 5 is a timing diagram of the operation of FIG. 1, and the address 500 of the memory circuit 104 in FIG.
The case where the address output from the control circuit 109 is used as the address of the control circuit 109 and the case where the address output from the counter 108 is used are respectively indicated by CPU and C. Data 501 of the memory circuit 104 indicates when data is read/written between the second memory circuit 104 and the control circuit 109 as R/W, and the second memory circuit 104 indicates the address specified by the counter 108. W indicates that the address is a write address of the first memory circuits 100 to 103 by reading the address, and R indicates that the address is a read address. Furthermore, the state 502 of the selector 106 is the state of the memory circuit 10.
Corresponding to the address 500 of No. 4, whether the output of the selector 106 is address information from the control circuit 109 or the output of the counter 108 is indicated by CPU and C, respectively. In the state 0503 of the memory circuits 100 to 103, the selector 106 from the second memory circuit 104 is connected to the counter 10.
5 offered for sale by the address specified by 8, -
W and R indicate when data stored in the time storage circuit 115 is written and read as an address. This - hour memory circuit 115 causes the first memory circuit 1
For numbers 00 to 103, all time can be allocated to writing and reading.

The operation in FIG. 2 is the same as in FIG. 1, and the control circuit 209
Depending on how the contents are written to the second storage circuit 204, it is possible to decide whether to perform sequential write/random read or random write/sequential read.

〔Effect of the invention〕

As explained above, the present invention includes a first memory circuit, a second memory circuit that stores address information of the first memory circuit,
A circuit that temporarily stores address information output from the second storage circuit, a counter that generates address information of the second storage circuit, a control circuit that generates address information of the second storage circuit, and a counter or control circuit. and a selector for selecting either address information from the control circuit, and a selector for selecting either address information from the control circuit, and reads address information in which data to be written or read from the first memory circuit is stored from the second memory circuit, and selects address information from the control circuit. By reading and writing the address information of the first memory circuit stored in the second memory circuit, it is possible to perform either sequential write/random read or random write/sequential read operations with the same circuit configuration. The number of selectors that select the address information input to the memory circuit can be reduced, making it relatively easy to design considering element delay, and also helping to reduce the circuit scale.

[Brief explanation of drawings]

Figures 1 and 2 are block diagrams of one embodiment of the present invention, Figures 3 and 4 are typical block diagrams of time-division switch control systems, and Section 5 shows the operation of Figure 1. FIG. 100-103, 200-203...first memory circuit, 104,204,304,404...second memory circuit, 106,206,305,306,405.406
...Selector, 108,208,307.308,4
07,408...Counter, 109°209.309
,409...control circuit, 110-113.210-2
13...Signal line with low multiplicity, 114.214...
Signal lines with high multiplicity, 115, 215... - time memory circuit.

Claims (1)

[Claims] a first storage circuit that temporarily stores digital audio signals or data; a second storage circuit that stores address information of the first storage circuit; and a second storage circuit that stores address information of the first storage circuit; a temporary storage circuit that temporarily stores address information and outputs it to the first storage circuit after a predetermined delay time; a counter that generates address information of the second storage circuit; a control circuit that generates address information of the first storage circuit;
A time division switch control system comprising: a selector for selecting either the output of the counter or the address information from the control circuit.