JPH0290592A - Multilayer printed wiring board - Google Patents
Multilayer printed wiring boardInfo
- Publication number
- JPH0290592A JPH0290592A JP24276888A JP24276888A JPH0290592A JP H0290592 A JPH0290592 A JP H0290592A JP 24276888 A JP24276888 A JP 24276888A JP 24276888 A JP24276888 A JP 24276888A JP H0290592 A JPH0290592 A JP H0290592A
- Authority
- JP
- Japan
- Prior art keywords
- prepreg
- multilayer
- glass cloth
- inner layer
- weft
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 239000011521 glass Substances 0.000 claims abstract description 18
- 239000004744 fabric Substances 0.000 claims abstract description 15
- 238000000465 moulding Methods 0.000 claims description 11
- 238000010030 laminating Methods 0.000 claims description 2
- 239000004020 conductor Substances 0.000 abstract description 14
- 238000000034 method Methods 0.000 abstract description 10
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract description 7
- 229920001721 polyimide Polymers 0.000 abstract description 7
- 239000011889 copper foil Substances 0.000 abstract description 6
- 239000009719 polyimide resin Substances 0.000 abstract description 6
- 239000004642 Polyimide Substances 0.000 abstract 1
- 238000005520 cutting process Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 238000010438 heat treatment Methods 0.000 description 3
- 239000011347 resin Substances 0.000 description 3
- 229920005989 resin Polymers 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 2
- 229920001187 thermosetting polymer Polymers 0.000 description 2
- 239000011230 binding agent Substances 0.000 description 1
- 238000004364 calculation method Methods 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000008602 contraction Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
- 238000009941 weaving Methods 0.000 description 1
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は多層印刷配線板に係シ、特に多層化成型時に使
用するプリプレグに関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a multilayer printed wiring board, and particularly to a prepreg used in multilayer molding.
従来、多層印刷配線(以下多層PWBと略す)の製造方
法は、一般的に次のとおりである。基板材料としては、
ガラス布を基材として熱硬化性樹脂(エポキシ樹脂やポ
リイミド樹脂等)t−結合剤とする銅張積層板に、内層
導体パターンな工、チング法によシ形成し、これを複数
枚のプリプレグ(ガラス布に半硬化の熱硬化性樹脂を含
浸したシー) )t−介し、最外側に外層基板(片面の
銅張積層板ま九は銅はく)を配して加熱加圧し、一体化
成型して多層化基板とする。この多層化基板に、内層導
体パターンに接続させる貫通孔および部品搭載用の貫通
孔をドリルによシ孔あけし、次いで貫通孔内を金属めり
きしてスルホールを形成する。Conventionally, a method for manufacturing multilayer printed wiring (hereinafter abbreviated as multilayer PWB) is generally as follows. As a substrate material,
An inner conductor pattern is formed on a copper-clad laminate using a glass cloth as a base material and a thermosetting resin (epoxy resin, polyimide resin, etc.) as a T-binder, and this is then formed into multiple sheets of prepreg. (A sheet made of glass cloth impregnated with semi-hardened thermosetting resin.) An outer layer substrate (one-sided copper-clad laminate (copper foil) is placed on the outermost side) and heated and pressurized to integrate. It is molded into a multilayer substrate. Through-holes to be connected to the inner layer conductor pattern and through-holes for mounting components are drilled in this multilayered substrate, and then the insides of the through-holes are plated with metal to form through-holes.
更に、エツチング法等により外層導体パターンを形成し
て、多層PWBを完成するものである。Furthermore, an outer layer conductor pattern is formed by etching or the like to complete the multilayer PWB.
前述した従来の多層PWBは、基板材料としてガラス布
をベースとした積層板およびプリプレグを使用するため
、内層導体パターン形成工程および多層化成型工程にお
いて寸法変化することが避けられない。Since the conventional multilayer PWB described above uses glass cloth-based laminates and prepregs as substrate materials, dimensional changes are inevitable in the inner layer conductor pattern forming process and the multilayer molding process.
このため各工程での内層基板の寸法変化を定量化し、内
層導体パターン形成用マスクフィルムに一定の寸法補正
を加え、多層化成型後目的とする一定の内層導体パター
ン寸法を得る方法が取られている。For this reason, a method has been adopted in which the dimensional changes of the inner layer substrate in each process are quantified, a certain dimensional correction is made to the mask film for forming the inner layer conductor pattern, and the desired constant inner layer conductor pattern dimensions are obtained after multilayer molding. There is.
更に、前記内層基板の寸法変化を小さく、バラツキ幅を
小さくするため、内層基板に使用する銅張積層板を予め
多層化成型時の温度条件を越える条件で加熱し、基板に
内在しているひずみを除去する方法や、また内層導体パ
ターン形成工程における熱処理9機械研磨条件の軽減お
よびコントロールする試みがなされている。Furthermore, in order to reduce the dimensional change and width of variation in the inner layer substrate, the copper-clad laminate used for the inner layer substrate is heated in advance to a temperature that exceeds the temperature conditions during multilayer molding to reduce the inherent strain in the substrate. Attempts have been made to reduce and control the heat treatment 9 mechanical polishing conditions in the inner layer conductor pattern forming process.
また、多層化成型時において内層基板はその上下面に接
するプリプレグの熱収縮のため内層導体パターン形成工
程中の寸法変化をはるかに上回る寸法変化をおこすため
、多層化成型時の加熱加圧のコントロールが重要となっ
てきている。In addition, during multilayer molding, the inner layer substrate undergoes dimensional changes that far exceed the dimensional changes during the inner layer conductor pattern formation process due to thermal contraction of the prepreg in contact with the top and bottom surfaces, so it is necessary to control heating and pressure during multilayer molding. is becoming important.
しかしながら、プリプレグ自体の熱収縮を定量化するこ
とは困難であシ、かつプリプレグの原材料であるガラス
クロスの九て糸、よこ糸を織布する工程で発生するひず
みおよびガラスクロスに樹脂を含浸する際に発生するひ
ずみを解放する手段はない。However, it is difficult to quantify the thermal shrinkage of the prepreg itself, and the strain that occurs during the process of weaving the nine warps and wefts of the glass cloth, which is the raw material for the prepreg, and the strain that occurs during the process of impregnating the glass cloth with resin. There is no way to release the strain that occurs.
近年、コンピュータ等の大盤システムにおいては、よシ
ー層の高性能化(演算スピードの高速化等)′t−図る
ため、多層PWBK対してよシ高密度化、高多層化が要
求されている。このため、10層乃至20層の多層PW
Bでは内層基板の厚さは多層化成型後の多層化基板の厚
さを出来るだけ抑えるため、0.1〜0.2 mmの厚
さが必要となっている。In recent years, in large-scale systems such as computers, in order to improve the performance of the layers (increasing the calculation speed, etc.), there has been a demand for higher density and higher multilayer multilayer PWBK. For this reason, a multilayer PW of 10 to 20 layers
In B, the thickness of the inner layer substrate is required to be 0.1 to 0.2 mm in order to suppress the thickness of the multilayer substrate after multilayer molding as much as possible.
また、内層導体パターンの高密度化要求に伴ない、スル
ホール間に多数の配線パターンを形成するため、スルホ
ールと内層導体パターンとの絶縁間隙が狭くなりてきて
いる。In addition, with the demand for higher density inner layer conductor patterns, a large number of wiring patterns are formed between through holes, so the insulation gap between the through holes and the inner layer conductor patterns is becoming narrower.
この結果、内層基板の厚さが薄くなるほど多層化成型時
のプリプレグの熱収縮の影響が寸法変化として大きく現
われ、またバラツキも大きくなシ、システムの要求を満
足する高密度な高多層PWBを製造することは困難とな
ってきている。As a result, as the thickness of the inner layer substrate becomes thinner, the effect of heat shrinkage of the prepreg during multilayer molding becomes more pronounced as a dimensional change, and the variation becomes larger.As a result, we can manufacture high-density, high-multilayer PWBs that satisfy the system requirements. It is becoming difficult to do so.
本発明の目的は、前記問題点を解決し、プリプレグの熱
収縮による歪みがなく、高密度な配線ができるようにし
た多層印刷配線板を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems and provide a multilayer printed wiring board that is free from distortion due to heat shrinkage of the prepreg and allows for high-density wiring.
本発明の構成は、内層基板および外層基板を、ガラスク
ロスから構成されるプリプレグを介して、積層成型して
なる多層印刷配線板において、前記ガラスクロスのたて
糸およびよこ糸は、所定位置で各々切断されていること
を特徴とする。The structure of the present invention is a multilayer printed wiring board formed by laminating and molding an inner layer substrate and an outer layer substrate via a prepreg made of glass cloth, in which the warp and weft of the glass cloth are each cut at a predetermined position. It is characterized by
次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第1図は本発明の第1の実施例の多層PWBの多層化構
成を示す断面図である。同図において、本実施例の多層
PWBは、表裏最外側に、厚さ18μmの銅は<it配
し、その内側に内層導体パターン2を表裏両面に形成し
た厚さQ、 l mmのガラス布−ポリイミド樹脂基材
の内層基板3t−多数配し、前記銅はく1.内層基板3
の間に、厚さ0.1mmのガラス布−ポリイミド樹脂プ
リプレグ4を2枚づつで介挿し次ものである。FIG. 1 is a sectional view showing a multilayer structure of a multilayer PWB according to a first embodiment of the present invention. In the same figure, the multilayer PWB of this example is made of a glass cloth with a thickness of Q, 1 mm, with copper of 18 μm thick disposed on the outermost sides of the front and back, and inner layer conductor pattern 2 formed on both the front and back sides. - A large number of inner layer substrates 3t made of a polyimide resin base material are arranged, and the copper foil 1. Inner layer substrate 3
Two glass cloth-polyimide resin prepregs 4 each having a thickness of 0.1 mm were inserted between the two sheets.
第2図は第1図のプリプレグ4を拡大して示した平面図
である。同図において、本実施例のプリプレグ4は、太
さ7μのモノフィラメントを約200本収束してたて糸
5、及びよこ糸6となし、1インチ平方当りたて50本
、よこ60本の密度に平織りした後、Bステージ(半硬
化)のポリイミド樹脂を含浸させたものてあ)、たて糸
5.よこ糸6それぞれ長さ10mm当りに1箇所だけ、
第2図に示すように、不規則に直径9.4mmのドリル
により孔あけして、切断ポイント7(図中x印の部分)
を形成する。FIG. 2 is an enlarged plan view of the prepreg 4 shown in FIG. 1. In the same figure, the prepreg 4 of this example is made by converging approximately 200 monofilaments with a thickness of 7μ to form warp yarns 5 and weft yarns 6, and is plain woven at a density of 50 yarns in the warp and 60 yarns in the weft per square inch. After that, the warp yarn is impregnated with B-stage (semi-cured) polyimide resin.5. Only one place per 10mm length of each weft thread 6,
As shown in Figure 2, holes are drilled irregularly with a drill of 9.4 mm in diameter, and cutting point 7 (portion marked x in the figure) is made.
form.
次いで、第1図に示す多層構成に組込み、温度170℃
乃至200℃、圧力30 kg/cm’ で、90分乃
至150分間加熱加圧し、多層基板を完成する。Next, it was assembled into the multilayer structure shown in Fig. 1 and heated to a temperature of 170°C.
The multilayer substrate is completed by heating and pressing at a temperature of 200° C. and a pressure of 30 kg/cm’ for 90 minutes to 150 minutes.
第3図は本発明の第2の実施例の多層印刷配線板のプリ
プレグ部分を拡大して示す平面図である。FIG. 3 is an enlarged plan view showing a prepreg portion of a multilayer printed wiring board according to a second embodiment of the present invention.
同図において、本実施例のプリプレグ4は、たて糸5.
よこ糸6それぞれの切断ポイン)(X印)7を、1本と
びに設けたもので、前記第1の実施例に比べてさらに生
産性が向上する利点がある。In the figure, the prepreg 4 of this example has warp yarns 5.
A cutting point (X mark) 7 is provided for each of the weft threads 6, which has the advantage of further improving productivity compared to the first embodiment.
これら本発明の第1.第2の実施例の効果を示す。厚さ
Q、1mmのガラス布−ポリイミド樹脂積層板による内
層導体パターンの多層化成形前後の寸法変化を、従来の
プリプレグと比較すると次の表のようになる。The first of these aspects of the present invention. The effects of the second embodiment will be shown. The following table compares the dimensional changes before and after multilayer molding of the inner layer conductor pattern of a glass cloth-polyimide resin laminate with a thickness Q of 1 mm with that of a conventional prepreg.
この表に示すように、本発明により、寸法変化。As shown in this table, the dimensional changes according to the present invention.
バラツキ共に従来の172乃至1/3に抑えることが出
来、高密度、高精度な多層PWBが得られる。Both variations can be suppressed to 172 to 1/3 of the conventional level, and a high-density, high-precision multilayer PWB can be obtained.
以上説明したように、本発明は、プリプレグのガラスク
ロスを部分的に切断することによシ、プリプレグの熱収
縮量およびバラツキを抑える効果がある。As explained above, the present invention has the effect of suppressing the amount of heat shrinkage and variation in the prepreg by partially cutting the glass cloth of the prepreg.
第1図は本発明の第1の実施例の多層PWBの多層化構
成を示す断面図、第2図は第1図のプリプレグの平面図
、第3図は本発明の第2の実施例の多層PWBのプリプ
レグの拡大平面図である・l・・・・・・銅はく、2・
・・・・・内層導体パターン、3・・・・・・内層基板
、4・・・・・・プリプレグ、5・・・・・・(ガラス
クロスの)たて糸、6・・・・・・(ガラスクロスの)
よこ糸、7・・・・・・(ガラスクロスの)切断ポイン
ト。
代理人 弁理士 内 原 晋FIG. 1 is a sectional view showing the multilayer structure of a multilayer PWB according to the first embodiment of the present invention, FIG. 2 is a plan view of the prepreg shown in FIG. 1, and FIG. It is an enlarged plan view of the prepreg of multilayer PWB.L... Copper foil, 2.
...Inner layer conductor pattern, 3...Inner layer substrate, 4...Prepreg, 5...Warp thread (of glass cloth), 6... glass cloth)
Weft thread, 7... Cutting point (of glass cloth). Agent Patent Attorney Susumu Uchihara
Claims (1)
るプリプレグを介して、積層成型してなる多層印刷配線
板において、前記ガラスクロスのたて糸およびよこ糸は
、所定位置で各々切断されていることを特徴とする多層
印刷配線板。A multilayer printed wiring board formed by laminating and molding an inner layer substrate and an outer layer substrate via a prepreg made of glass cloth, characterized in that the warp and weft of the glass cloth are each cut at a predetermined position. multilayer printed wiring board.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP24276888A JPH0290592A (en) | 1988-09-27 | 1988-09-27 | Multilayer printed wiring board |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP24276888A JPH0290592A (en) | 1988-09-27 | 1988-09-27 | Multilayer printed wiring board |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0290592A true JPH0290592A (en) | 1990-03-30 |
Family
ID=17093991
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP24276888A Pending JPH0290592A (en) | 1988-09-27 | 1988-09-27 | Multilayer printed wiring board |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0290592A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7319407B2 (en) | 2003-12-19 | 2008-01-15 | Lg Electronics Inc. | Display unit for refrigerator |
-
1988
- 1988-09-27 JP JP24276888A patent/JPH0290592A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7319407B2 (en) | 2003-12-19 | 2008-01-15 | Lg Electronics Inc. | Display unit for refrigerator |
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