JPH0285960A - Information processing system - Google Patents

Abstract

PURPOSE:To attain high efficiency in a scalar data load processing by performing the nullifying processing of all the contents of registration in a tag storage means replying to an area detecting signal when receiving the area detecting signal from an area detecting means. CONSTITUTION:An area detection circuit 12, when receiving a scalar load command, compares a scalar load address sent with the command with the output 105 of a vector store address area register circuit 7 and the output 119 of an area address reception circuit 15 which holds a vector store area address corresponding to the vector store operation of another information processor sent from another information processor via a bus 120. And it is compared whether or not the scalar load address is included in a vector store address area, and the area detecting signal is sent to a nullification circuit 19 via a bus 107 when it is included in the area, and the processing of a tag registration nullification circuit 11 is cancelled by the output of the nullification circuit 19, and also, all the tags of a tag memory circuit 8 are nullified by controlling a tag control circuit 9. In such a way, it is possible to improve the efficiency of a vector store processing.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to an information processing system that controls and executes vector arithmetic processing and scalar arithmetic processing, and particularly relates to a parallel processing device that shares a main storage device and has a cache memory. The present invention relates to a cache matching process control method for efficiently performing scalar data load processing during vector data store processing in .

[Conventional technology]

In an information processing system that has a scalar arithmetic processing unit with a cache memory circuit and a parallel vector arithmetic processing unit that has multiple interfaces to the main memory and can access multiple vector element data simultaneously, vector arithmetic processing is performed. In order to guarantee the contents of the cache memory circuit of the scalar arithmetic processing unit in response to the store operation of vector elements to the main memory performed by the processing unit, the vector store address is stored in the tag storage circuit and the cache memory is stored. The conventional method is to have an invalidation circuit that checks whether data corresponding to a vector store address is registered in the circuit and invalidates the corresponding address registered in the tag storage circuit if it is registered. Are known.

Generally, this invalidation operation is performed independently of the actual vector element store operation to the main memory, and in order to improve the processing efficiency of the invalidation operation, there are methods such as providing multiple invalidation circuits. is also known.

However, in a parallel processing device configuration that shares a main memory, when a vector store operation is performed on the main memory from another information processing device, the data in the cache memory circuit of the own information processing device and the main memory are In order to guarantee data consistency with the device, it is checked whether data at the corresponding address is registered in the cache memory circuit of the own information processing device by receiving a vector store address from another information processing device to the main storage device. It is necessary to perform cache invalidation processing to check whether the

Conventionally, this type of processing is performed sequentially, so the scalar load instruction to the cache memory circuit of the own information processing device is executed after the cache invalidation processing for the vector store operation of the other information processing device is completed. are doing.

[Problem to be solved by the invention]

In the conventional method described above, a scalar load instruction subsequent to a vector store instruction from the own information processing device or another information processing device is not executed even if the requested scalar data exists in the buffer memory circuit of the own information processing device. However, since execution is suspended until the data guarantee of the buffer memory circuit ends, there is a drawback that the speed of the scalar load instruction cannot be increased.

[Means to solve the problem]

One of the information processing systems of the present invention includes a main storage device and a plurality of information processing devices that share the main storage device, and has a data transmission/reception path with the main storage device, a vector arithmetic processing means for accessing vector element data stored in the main memory; a scalar arithmetic processing means having a data transmission/reception path with the main memory; and the vector arithmetic processing means in accordance with program instructions. or a command means for issuing load/store operation commands for vector data or scalar data to the scalar arithmetic processing means, and a data transmission/reception path between the main storage device and a part of the data with the main storage device; buffer memory means for storing a copy of the block data stored in the buffer memory means; and tag storage means for registering block address information of the main storage device corresponding to block data stored in the buffer memory means together with a valid bit indicating validity/invalidity of the block address information. , a tag control means for controlling new registration of block address information in the tag storage means or invalidation processing of registered addresses; and a tag control means for controlling new registration of block address information in the tag storage means or invalidation processing of registered addresses; a tag that checks whether or not each store address for a plurality of vector elements generated by the vector element is registered in the tag storage means, and if registered, instructs the tag control means to invalidate the registered address; an invalidation instruction means; a vector store address means for outputting a store start address and a store end address on the main storage device as an address area in response to the vector store operation command; Address area output means for outputting to a plurality of information processing devices whether or not vector store processing is in progress together with a valid/invalid indication bit; and output of the vector store address means from the plurality of information processing devices to each valid/invalid indication bit. and an address area receiving means that receives the data at the same time, and in response to the vector data store operation command, the tag registration invalidation instructing means completes its operation and before turning off the valid/invalid indication bit, or the plurality of When a subsequent scalar data load operation command is received from the command means before each valid/invalid display bit is turned off from the information processing device, the scalar data load address received along with the scalar data load operation command is is within the address area indicated by the vector store address means, and whether a valid bit during a vector store operation from another information processing device to the main storage device indicated by the address area receiving means is on. area detection means for checking whether or not the area is within an address area, and outputting an in-area detection signal if it is within the area; When the within-area detection signal is output, all registered contents of the tag storage means are invalidated in response to the within-area detection signal, and the valid/invalid display bit within the address area receiving means is turned off. and invalidation means for canceling the operation of the invalidation instruction means.

Another information processing system of the present invention is an information processing system including a main storage device and a plurality of information processing devices that share the main storage device, in which a data transmission/reception path is established between the main storage device and the main storage device. a scalar arithmetic processing means having a data transmitting/receiving path between the main memory and the main memory; or a command means for issuing load/store operation commands for vector data or scalar data to the scalar arithmetic processing means, and a data transmission/reception path between the main storage device and a copy of a part of the data in the main storage device; buffer memory means for storing block data stored in the buffer memory means; and tag storage means for registering block address information of the pre-fertilization storage device corresponding to the block data stored in the buffer memory means together with a valid bit indicating validity/invalidity of the block address information. , a tag controller that controls new registration of block address information in the tag storage means or invalidation processing of registered addresses; It is checked whether the store address on the main storage device for each data of a plurality of vector element data generated in accordance with the above is registered in the tag storage means, and if it is registered, the tag is tag invalidation instruction means for instructing a control means to invalidate a registered address; outputting a store start address and a store end address on the main storage device corresponding to the vector store operation command as an address area; A vector store address means that operates to reduce 111 in the address area each time each element data is stored, and an output of the vector store address means and an indication of whether vector store processing is in progress. address area output means for sending store processing display bits to the plurality of information processing devices; a plurality of address area reception means for receiving outputs from the address area output means sent from the plurality of information processing devices, respectively; and the vectors. In response to a data store operation command, the tag registration invalidation instructing means completes the operation and before turning off the store process display bit, or the store process display is sent from the plurality of information processing devices. When a subsequent scalar data load operation command is received from the command means before all bits are turned off, the vector store address means indicates a scalar data load address received in conjunction with the scalar data load operation command. Whether it is within the address area or not, and if the store processing display bit for the main storage device of the other information processing device indicated by the plurality of address area receiving means is turned on, the data is sent from the corresponding other information processing device. area detection means for checking whether or not the scalar data load address is within the address area where the scalar data load address is being received, and outputting an in-area detection signal if it is within the area; While processing the data load operation command, 2c in front of the area detection means mentioned above! Upon receiving an in-area detection signal, in response to the in-area detection signal, invalidate all registered contents of the tag storage means, turn off a valid/invalid display bit in the address area receiving means, and and invalidation means for canceling the operation of the invalidation instruction means.

〔Example〕

Next, the present invention will be explained in detail with reference to the drawings.

First, a first embodiment of the present invention will be explained using FIG.

In this embodiment, in order to simplify the explanation, a case will be described in which two information processing apparatuses 1.2 share one main storage device 5.

In the information processing device 2, when a vector data store command is sent from the command circuit 3 to the vector arithmetic processing device 14 and the tag registration invalidation circuit 11 via the path 101, the vector arithmetic processing device 14 sends the vector data store instruction via the path 102. A vector store operation is executed on the main storage device 5. The vector store address area register circuit 7 receives the vector store start address (B) and vector element distance (
D) and the number of vector store elements (E), vector store start address (B) and end address - (B
)±(D)X(E) and save the result. Here, the equation (2) indicates whether the upper address direction of the store data is the lower address direction.

Further, the tag registration invalidation circuit 11 uses vector store addresses (B), (B±D), (B±2D), . . . from vector store information sent via the path 101.
B+EX[)) is created and sent to the cache control circuit 6 via a path 117 along with a cache invalidation request (not shown).

Upon receiving the scalar load command, the reconnaissance area detection circuit 12 sends the scalar load address sent together with the output 105 of the vector store address area register circuit 7 and the other information processing device 1 via the path 120. area address receiving circuit 1 that holds a vector store area address corresponding to the vector store operation of the information processing device;
The output 119 of 5 is compared to see if the scalar load address is within the vector store address area, and if it is within the area, the in-area detection signal is
7 to the invalidation circuit 19, and the invalidation circuit 19
This output cancels the processing of the tag registration invalidation circuit 11, controls the tag control circuit 9, and invalidates all tags in the tag storage circuit 8.

On the other hand, in the cache control circuit 6, the corresponding scalar load command results in a cache miss due to the above operation.
It is sent directly to main memory 5 via path 118. The override data from the main storage device 5 in response to the scalar load command is registered in the cache memory 10 via the path 111, and is also returned to the scalar arithmetic processing circuit 13. If the area detection signal is not output, first check whether the scalar load address is registered in the tag storage circuit 8. If it is registered, the scalar data read from the cache memory 10 is transferred via the path 113. and sent to the scalar arithmetic processing circuit 13. Further, if the scalar load address is not registered in the tag storage circuit 8, the block data including the scalar load address data is registered in the cache memory 10 from the main storage device 5 via the path 111, and the scalar load address data is also registered in the tag storage circuit 8. A block address including the load address is registered according to instructions from the tag control circuit 9, scalar load data is read again from the cache memory 10, and the load data is sent to the scalar arithmetic processing circuit 13.

The above operation is a description of a specific example according to the first embodiment.

Next, with reference to FIG. 2, the tag storage circuit 8 and the tag registration invalidation instruction circuit 11 will be described in more detail.

When a vector store command is sent from the command circuit 3 to the tag registration invalidation circuit 11 via the path 101, - the start address (B) of the vector store, the distance between vector elements M (D), and the vector store Uprime number, (
E) are set in the start address 201, vector element distance register 202, and element number register 203, respectively.

The output of the start address register 201 is sent to the switching circuit 204.
The output of vector element distance register 2.02 is sent to adder 206. The adder 206 is an adder manual register 205
The output of the vector element register 202 is added to the output of the vector element register 202, and the result is sent to the switching circuit 204 and the vector store address register 207.

The output of the vector store address register 207 is sent as a cache invalidation request to the cache control circuit 6 via the path 117 every time the result of the adder 206 is set. It is set in the tag search address register 502 via the switching circuit 501.

Further, the vector store address is set in the vector store address register 207 the number of times equal to the number of elements (E), and is transferred to the cache control circuit 6 as the vector store address (E) times.

Here, although the switching control of the switching circuit 501 is not shown in detail in this embodiment, the timing when a scalar load store request is sent from the scalar request register 500 via a path 505, and the timing when a scalar load store request is sent from the scalar request register 500 via a path 117, If the timing at which cache invalidation requests are sent from the address register 207 coincides, the swash load/store request shall be processed with priority, and the processing of the tag registration invalidation circuit 11 must be interrupted during this time. However, since these controls may be performed using a generally considered request contention control method and are not directly related to the present invention, detailed explanations will be omitted.

In the tag registration invalidation circuit 11, the creation and transfer of the vector store address is executed by passing the output of the element number register 203 through the subtracter 209 until the vector store address control circuit 211 detects zero. On the other hand, the first
As explained in the figure, the control signal 12 from the invalidation circuit 19
When the subtraction result register is reset by 1, zero is detected by the vector store address control circuit 211, and the operation of the tag registration invalidation circuit 11 is forcibly terminated.

When a vector store address is set in the tag search address register 502, the lower block internal address part of the address is sent to the tag memory 301 and the tag V bit memory 305 via the path 110, and the corresponding block address and V bit are The comparison circuits 401, 40
The signal is sent to 2AND/NAND gates 403 and 404.

In this embodiment, the buffer memory has two compartments (
level).

Comparison circuits 401 and 402 compare the output of the tag memory circuit 301 and the upper block address information of the tag search address register 502, and the comparison result is AND/NAN.
Tag V bit memory circuit 30 with D gates 403 and 404
An AND condition is taken for each output and level of 5. If a comparison is found in the comparison circuit 401 or 402, and the output of the tag V bit memory circuit 305, which indicates the validity of the corresponding program address, is in the on state, the OR of the match signals of both levels is determined by the NAND gate 405. The hit signal is set in the hit display flag 407, and if the hit level at that time is 0 level, the level 0 match flag 408 is set.

When the hit display flag 407 is set, the address information in the lower block of the tag search address register 502 is set in the invalidation address register 406, and the output is sent to the tag storage circuit 8.

The output of the hit display flag 407 is output from the AND gate 409.
The AND condition is taken with the timing signal 506 from the quick timing control unit 503 of the cache control circuit 6, and the V of the tag V bit memory 305 in the tag storage circuit 8 is
The output of the 0'' level signal 303 is selected by the switching circuit 304 as the writing force for setting the bit to O.

On the other hand, the control signal 121 from the invalidation circuit 19 is input to the all tag invalidation address circuit 411.

The output is sent to the tag V bit memory 305 via the switching circuit 412, and all tag pits are cleared.

The above is an explanation of the vector store address invalidation processing method of the tag storage circuit 8.

Next, a vector store address area register circuit 7, an area detection circuit 12, and an area address transmission/reception circuit 15.
16 will be explained with reference to the 1-process diagram in FIG.

When a vector data store command from the command circuit 3 of the information processing device 2 is issued to the vector store address area register circuit 7 via the path 115 via the tag registration invalidation circuit 11, the start of vector store is sent together with the vector data store command. The address (B), the distance between vector elements (D), and the number of elements of the vector store (E) are set in the start address register 600, the distance between vector elements register 601, and the number of elements register 602, respectively. The output of starting address register 600 is sent to adder 604 and vector store starting address register 606.

The outputs of the inter-element distance register 601 and the number of elements register 602 are input to the multiplier 603, the output of DXE is input to the adder 604, and from the adder 604, the operation result of B+DxE is input to the vector store end address register 605.
is set to

The contents of these two registers 605 and 606 are valid until the vector store address control circuit 211 (FIG. 2) detects that the number of remaining vector elements is zero. That is, the contents of the vector store start register 606 and the vector end address register 605 are valid only while the tag registration invalidation process for the vector data store command is being executed. On the other hand, the outputs of registers 605 and 606 are
The contents are sent to 60 vector store end address transmission registers and a vector store start address transmission register 610, but these contents remain valid until the vector store operation from the information processing device 2 to the main storage device 5 is completed. .

Similarly, vector store end address reception register 60
7 and vector store start address reception register 608
The contents of ' are held as valid values until the vector store operation from the information processing device 1 to the main storage device 5 is completed.

When certain values are set in the area address receiving circuit 15, the vector store end address register 605, and the vector store start address register 506, and a scalar data load command is issued from the command circuit 3 to the cache control circuit 6 during the valid period, the The scalar data load address information transferred from the scalar request register 500 to the area detection circuit 12 and the tag search address register 502
sent to.

In the area detection circuit 12, a subtracter 702 subtracts the scalar load address information 116 from the output of the vector end address register 605, and if the result is a positive value, subtraction is possible (
A carry-out) signal 70G is output, and the subtracter 703 subtracts the output of the vector store start address register 606 from the scalar load address information 116. Similarly, if the result is a positive value, a subtraction possible (carry-out) signal 707 is generated. is output. That is, if the signal 706 and signal 707 meet the conditions at the gate 709, it means that the scalar load address is between the vector store start address and the vector store end address.

In this case, there is a possibility that the scalar data load address and the vector data store address match, and if the scalar data is loaded from the cache memory 10 before the tag registration invalidation process is completed, the vector store will cause the main memory 5 The result is that even though the contents of the cache memory 10 are about to be changed, the contents of the cache memory 10 before the change are loaded.

Therefore, if the condition is met at the gate 709, the control signal 107 is sent to the invalidation circuit 19, and as already explained, the processing of the tag registration invalidation circuit 11 is canceled.
It also controls the tag control circuit 9 and invalidates all tags in the tag storage circuit 8.

On the other hand, similarly, the contents of the area address receiving circuit and the contents of the scalar load address are compared using subtracters 700 and 701, and the scalar load address is stored in the vector store area for the main memory 5 of the other information processing device 1. If it is within the area, there is a possibility that the contents of the cache memory 10 and the main storage device 5 will not match, so the same process is performed for one invalidation circuit. A control signal 107 is sent out.

In this way, it is possible to process subsequent scalar load instructions without interrupting the main memory shared by a plurality of information processing devices during vector store execution.

Referring to FIG. 4, the information processing system according to the second embodiment of the present invention includes a vector store address area circuit 20
The configuration is similar to that of the first embodiment shown in FIG. 1, except that .

Therefore, parts having the same functions as those in the first embodiment are given the same reference numerals, and their explanations will be omitted.

Upon receiving the scalar load command, the area detection circuit 12 performs the following:
- The scalar load address sent together with the output 123 of the vector store address area circuit 20 and the vector store address corresponding to the vector store operation of another information processing device sent from the other information processing device 1 via the path 120 Area address receiving circuit 1 that holds area addresses
The output 119 of 5 is compared to see if the scalar load address is within the vector store address area, and if it is within the area, the in-area detection signal is
7 to the invalidation circuit 19, and the invalidation circuit 19
With the output of , the processing of the tag invalidation circuit 11 is canceled, the tag control circuit 9 is controlled, and the entire tag storage circuit 8 is invalidated.

Next, the vector store address area register circuit 7, the vector store address area circuit 20, the area address receiving circuit 15, and the area detection circuit 12 will be explained with reference to the block diagram of FIG.

When a vector data store command from the command circuit 3 of the information processing device 2 is issued to the vector store address area register circuit 7 via the path 115 via the tag registration invalidation circuit 11, the The start address (B), the distance between vector elements (D), and the number of elements of the vector store (E) are set in the start address register 600, the distance between vector elements register 601, and the number of elements register 602, respectively. The output of starting address register 600 is sent to adder 604 and vector store starting address register 606. The outputs of the inter-element distance register 601 and the number of elements register 602 are input to the multiplier 603, the output of DXE is input to the adder 604, and from the adder 604, the calculation result of B+DXE is set in the vector store end address register 605. be done. Furthermore, the outputs of the registers 605 and 605 are sent to the vector store end address register 801 and the vector store base register 803 in the vector store address area circuit 20, but the contents of the register 803 are processed by the tag registration invalidation circuit 11. Each time each element data of the vector data is stored, the contents of the vector element distance register 804 are added to the adder 806, and the result is set in the vector store base address register 811.

That is, the vector store address area indicated by the register 801 and the register 811 is narrowed each time invalidation processing and vector data element data storage processing is performed, and these contents are stored in the main memory from the information processing device 2. Device 5
Indicates a valid value until the vector store operation for is completed.

On the other hand, vector store end address reception register 607
The contents of the vector store start address reception register 608 also hold valid values until the vector store operation from the information processing device 1 to the main storage device 5 is completed.

When certain values are set in the area address receiving circuit 15, the vector store end address register 801, and the vector store base address register 811, and a scalar data load command is issued from the command circuit 3 to the cache control circuit 6 during the valid period, -The scalar data load address information transferred at the same time is stored in the scalar request register 50.
0 to the area detection circuit 12 and tag search address register 502. Vector store address area circuit 2
The contents of the element number register 805 at 0 are the contents of the subtracter 80
In β, each time the contents of vector store address register 811 are updated, it is decremented by 1, the result is set in remaining element register 809, and the subtraction control circuit 810 executes until zero is detected.

In the area detection circuit 12, a subtracter 702 subtracts the scalar load address information 116 from the output of the vector end address register 801, and if the result is a positive value, subtraction is possible (
A carry-out) signal 70G is output, and the subtracter 703 subtracts the contents of the vector store base address register 811 from the scalar load address information 116. Similarly, if the result is a positive value, a subtraction possible (carry-out) signal 707 is generated. is output. That is, if the signals 706 and 707 meet the conditions at the gate 709, it means that the scalar load address is between the vector store start address and the vector store end address.

In this case. There is a possibility that the scalar load address and the vector data store address match, and if the scalar data is loaded from the cache memory 10 before the tag registration invalidation process is completed, the contents of the main memory 5 will be changed by the vector store. However, the contents of the cache memory 10 before the change are loaded.

Therefore, if the conditions are met at the gate 709, the control signal 107 is sent to the invalidation circuit 19, and as already explained, the processing of the tag registration invalidation circuit 11 is canceled.
It also controls the tag control circuit 9 and invalidates all tags in the tag storage circuit 8.

On the other hand, similarly, the contents of the area address receiving circuit and the contents of the scalar load address are compared using the subtracters 700 and 701, and the scalar load address is stored in the vector store area for the main memory 5 of the other information processing device 1. If it is within the area, there is a possibility that the contents of the cache memory 10 and the main storage device 5 will not match, so a control signal is similarly sent to the invalidation circuit 19. 1'07 is sent.

In this way, during vector store execution, subsequent scalar load instructions can be processed without interruption in a main memory shared by a plurality of information processing devices.

〔Effect of the invention〕

As explained above, in the present invention, vector element store operations in vector operation instructions include: ■ store operations to consecutive addresses, ■ store operations at every fixed distance (D) address, and ■ store operations to random addresses. However, taking advantage of the fact that most of the store operations in ■ and ■ are performed, the start and end addresses of the store address are held in advance in the vector store address area register during the store operations in ■ and ■. By referencing the contents between devices that share the main memory, if the load address of the subsequent scalar load instruction is not within the vector store address area, it is possible to overtake the vector store process, improving performance. The effect is that it can be improved. Also, during the store operations of (1) and (2), the start address and end address of the store address are held in advance in a vector store address area register, and each time a vector element is stored, the register narrows the area accordingly. By referencing the contents between devices that share the main memory, if the load address of the subsequent scalar load instruction is not within the vector store address area, it is possible to overtake the vector store processing and improve performance. This has the effect of being able to improve efficiency.

Furthermore, in the present invention, when the load address of a scalar load instruction falls within the vector store address area, by completely clearing the cache memory, control can be simplified and speed can be increased.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an information processing system according to a first embodiment of the present invention, and FIG. 2 shows the tag registration invalidation circuit, tag storage circuit, tag control circuit, and cache control shown in FIG. 1. Block diagram showing the detailed configuration of the circuit, Part 3
The figure is a block diagram showing the detailed configuration of the vector store address area register circuit, area detection circuit, area address reception circuit, area address transmission circuit, and cache control circuit shown in FIG. 1. A block diagram showing the configuration of the information processing system according to the second embodiment, FIG. 5 shows the vector store address area register circuit, area detection circuit, area address receiving circuit, vector store address area circuit, and cache shown in FIG. 4. FIG. 2 is a block diagram showing a detailed configuration of a control circuit. 1.2... Information processing device, 3... Command circuit, 4...
・Vector arithmetic processing unit, 5...Main storage device, 6...
- Cache control circuit, 7... Vector store address area register circuit, 8... Tag storage circuit, 9...
Tag control circuit, 10... Cache memory, 11...
・Tag registration invalidation circuit, 12...Area detection circuit, 13
... Scalar arithmetic processing circuit, 14... Vector arithmetic processing device, 15... Area address receiving circuit, 16...
Area address transmitting circuit, 17... Area address receiving circuit, 18... Area address transmitting circuit, 19... Invalidation circuit, 20... Vector store address area circuit,
101-124...Signal lotus, 201...Start address register, 202...Vector element distance register, 203...Element number register, 204...Switching circuit, 205...Adder manual register , 206... Adder, 207... Vector store address register,
208...Switching circuit, 209...Subtractor, 210...
...Subtraction result register, 211...Vector store address control circuit, 212, 213...Signal path, 30
1... Tag memory circuit, 302...'1# level signal, 303... "0" level signal, 304... Switching circuit, 305... Tag V bit memory circuit, 401,
402... Comparison circuit, 403... AND/NAND
Gate, 404°405...NAND gate, 406
... Invalidation address register, 407 ... Hit display flag, 408 ... Level 0 match flag, 409.
...AND gate, 410...AND gate, 411
...All tag invalidation address circuit, 412...Switching circuit, 500...Scalar request register, 501
...Switching circuit, 502...Tag search address register, 503...Cache timing control unit, 504
...Switching circuit, 505...Signal path, 506...
Timing signal, 600...start address register,
601... Vector element distance register, 602...
・Element number register, 603... Multiplier, 604...
Adder, 605... Vector store end address register, 606... Vector store start address register, 607... Vector store end address reception register, 608... Vector store start address reception register, 609... Vector Store end address transmission register, 610...Vector store start address transmission register, 700-703...Subtractor, 704-7
07...Each signal path, 708 709...NAND
Gate, 710...AND gate, 711...Signal path, 801...Vector store end address register, 802...Switching circuit, 803...Vector store base register, 804...Vector element distance register , 805...Element number register, 806...Adder, 807...Switching circuit, 808...Subtractor, 80
9... Remaining element register, 810... Subtraction control circuit,
811...Vector store base address register.

Claims (1)

[Scope of Claims] 1. An information processing system comprising a main storage device and a plurality of information processing devices that share the main storage device, the information processing system having at least one data transmission/reception path with the main storage device; at least one vector arithmetic processing means for accessing vector element data stored in a main memory; a scalar arithmetic processing means having a data transmission/reception path between the main memory; and the vector arithmetic processing means in accordance with a program instruction. or a command means for issuing load/store operation commands for vector data or scalar data to the scalar arithmetic processing means, and a data transmission/reception path between the main storage device and a copy of a part of the data in the main storage device; buffer memory means for storing block data stored in the buffer memory means; tag storage means for registering block address information of the main storage device corresponding to block data stored in the buffer memory means together with a valid bit indicating validity/invalidity of the block address information; tag control means for controlling new registration of block address information in the tag storage means or invalidation processing of registered addresses; tag invalidation for checking whether or not each store address for a plurality of vector elements to be stored is registered in the tag storage means, and instructing the tag control means to invalidate the registered address if it is registered; instruction means; vector store address means for outputting a store start address and a store end address on the main storage device as an address area in response to the vector store operation command; address area output means for outputting to an information processing device together with a valid/invalid indication bit indicating whether vector store processing is in progress; and output of the vector store address means from the plurality of information processing devices together with respective valid/invalid indication bits In response to the address area receiving means and the vector data store operation command, the tag registration invalidation instructing means completes its operation and before turning off the valid/invalid display bit, or the plurality of pieces of information Each effective/
When a subsequent scalar data load operation command is received from the command means before the invalid indication bit turns off, the vector store address means indicates the scalar data load address received in conjunction with the scalar data load operation command. Also, whether or not the address area is within an address area where the valid bit during vector store operation from another information processing device to the main storage device is set to ON, as indicated by the address area receiving means. an area detecting means for checking if the area is within the area and outputting an in-area detection signal if the area is within the area; Then, in response to the in-area detection signal, all registered contents of the tag storage means are invalidated, a valid/invalid display bit in the address area receiving means is turned off, and the invalidation instruction means An information processing system comprising: invalidation means for canceling the operation of the information processing system. 2. In an information processing system consisting of a main storage device and a plurality of information processing devices that share the main storage device, the information processing system has at least one data transmission/reception path between the main storage device and the data stored in the main storage device. at least one vector arithmetic processing means for accessing vector element data, a scalar arithmetic processing means having a data transmission/reception path with the main storage device, and a scalar arithmetic processing means for accessing the vector arithmetic processing means or the scalar arithmetic processing means according to a program instruction. command means for issuing load/store operation commands for vector data or scalar data; and buffer memory means having a data transmission/reception path with the main memory and storing a copy of a part of the data in the main memory. a tag storage means for registering block address information of the main storage device corresponding to block data stored in the buffer memory means together with a valid bit indicating validity/invalidity of the block address information; a tag control means for controlling new registration of information or invalidation processing of a registered address; and a plurality of vector elements generated in response to a vector data store operation command from the command means and in response to the vector data store operation command. Check whether the store address on the main storage device for each data is registered in the tag storage means, and if it is registered, instruct the tag control means to invalidate the registered address. tag invalidation instructing means; and outputting a store start address and a store end address on the main storage device corresponding to the vector store operation command as an address area, and each time each data is stored for a plurality of vector element data. vector store address means that operates to reduce the width of the address area in response to the above, and an output of the vector store address means and a store processing display bit indicating whether or not vector store processing is in progress, a plurality of address area receiving means that receive the outputs of the address area outputting means respectively sent from the plurality of information processing devices; Before the tag registration invalidation instruction means completes its operation and turns off the store processing display bit, or before all the store processing display bits sent from the plurality of information processing devices are turned off, the command is executed. When a subsequent scalar data load operation command is received from the means, it is determined whether or not the scalar data load address received along with the scalar data load operation command is within the address area indicated by the vector store address means; If the store processing display bit for the main storage device of another information processing device indicated by a plurality of address area receiving means is turned on, the scalar is stored in the address area sent from the corresponding other information processing device. area detection means for checking whether a data load address is included and outputting an in-area detection signal if it is within the area; When receiving the within-area detection signal from the means, in response to the within-area detection signal, all registered contents of the tag storage means are invalidated, and a valid/invalid display bit within the address area receiving means is turned off. and a disabling means for canceling the operation of the disabling instruction means.