JPH0156429B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an information processing system that performs overtaking control of scalar data load processing during vector data store processing.

Prior Art In an information processing system having a scalar arithmetic processing device having a buffer memory circuit and a parallel vector arithmetic processing device having a plurality of interfaces to a main memory and capable of accessing a plurality of vector element data simultaneously, In response to the store operation of vector elements to the main memory performed by the vector arithmetic processing unit, a vector store address is sent to the buffer memory circuit and the tag storage circuit in order to guarantee the contents of the buffer memory circuit possessed by the scalar arithmetic processing unit. A method has been known in the past that includes an invalidation circuit that checks whether data corresponding to a vector store address is registered in the buffer memory and invalidates the corresponding address registered in the tag storage circuit if it is registered. There is. Generally, this invalidation behavior is
A method is also known in which a plurality of invalidation circuits are provided in order to improve the processing efficiency of the invalidation operation, which is performed independently of the actual vector element store operation to the main memory.

However, simply improving the processing efficiency of the invalidation operation in response to the vector store instruction does not make it possible to speed up instructions subsequent to the vector store instruction, especially scalar load instructions. In other words, during vector store processing (vector store operation and invalidation processing operation), subsequent scalar load instructions will not be processed until the data guarantee of the buffer memory circuit ends, even if the requested scalar data exists in the buffer memory circuit. The drawback is that the speed of scalar instructions cannot be increased because execution is interrupted.

Purpose of the Invention The store operations of vector elements in vector operation instructions are generally divided into store operations to consecutive addresses, store operations at fixed distance addresses, and store operations to random addresses. It is. An object of the present invention is to calculate the start address and end address of the store address in advance and store them in a vector store address area register during store operations to consecutive addresses and store operations to addresses of a fixed distance. An object of the present invention is to provide an information processing system that enables overtaking processing of vector store processing if the load address does not fall within the vector store address area.

Structure of the Invention The system of the present invention comprises a main storage device and a buffer memory means that has a data transmission/reception path between the main storage device and stores a copy of a part of the data in the main storage device, and a buffer memory device that stores data stored in the buffer memory device. a tag storage means for registering block address information in the main storage device corresponding to the tag storage means; a tag control means for controlling new registration of block address information in the tag storage means or invalidation of the registered address; A command main stage that issues data or scalar data load and store operation commands, and a vector store operation command from the command means, in which each store address for a plurality of vector element data generated in response to the command is set to the tag. tag registration invalidation command means for checking whether the registered address is registered in the storage means, and instructing the tag control means to invalidate the registered address if it is registered; A vector store area that stores the store start address and store end address on the main memory where the vector store is executed based on the vector store start address, the distance between vector element data, and the number of vector store elements that are generated accordingly. and storage means, and when a subsequent scalar data load command is received from the command means before the operation of the tag registration invalidation instructing means is completed in response to the vector data store command, the scalar data load address received in conjunction with the command is Area detection means for checking whether or not the address area is within the address area indicated by the vector store area storage means and outputting an in-area detection signal if it is within the area, and connected to the command means, buffer memory means, and tag storage means, respectively. and scalar control means for controlling to relay scalar load command processing upon receiving an in-area detection signal from the area detection means.

Embodiments of the Invention Next, the present invention will be described with reference to the drawings.

Referring to FIG. 1, one embodiment of the present invention includes a command circuit 1, a plurality of vector processing units 2, 3, and 4, a main memory 5, a scalar load control circuit 6, a vector store address area register 7, a tag It is composed of a circuit 8, a tag control circuit 9, a buffer memory circuit 10, a tag registration invalidation instruction circuit 11, an area detection circuit 12, and a scalar calculation circuit 13.

Referring to FIG. 2, the tag registration invalidation instruction circuit 11 includes a start address register 201, a vector element distance register 202, an element number register 203, a switching circuit 204, and an adder input register 2.
05, an adder 206, a vector address register 207, a switching circuit 208, a subtracter 209, a subtraction result register 210, a vector store address control circuit 211, a part of the switching circuit 300, and a tag detection address register 301.

The tag storage circuit 8 is a part of the switching circuit 300,
It consists of a part of the tag detection address register 301, a tag memory 302, a "1" level signal 303, a "0" level signal 304, a switching circuit 305, and a tag V bit memory 306.

The tag control circuit 9 is a write address register 4.
06, and AND gates 401 and 402.

The vector store address area register 7
are a start address register 600, a vector element distance register 601, an element number register 602,
It consists of a multiplier 603, an adder 604, a vector end address register 605, and a vector store start address register 606. The area detection circuit 12 is composed of subtracters 700 and 701 and an AND gate 702.

Next, the operation of this embodiment will be explained in detail.

A vector data store command is sent from the command circuit 1 via a path 101 to the vector arithmetic processing units 2, 3,
4, vector store address area register 7, and tag registration invalidation circuit 11, vector arithmetic processing units 2, 3, and 4 transfer vector store data to main memory 5 via paths 102, 103, and 104. perform an action. In vector store address area register 7, path 1
From the information of the vector store start address B, vector element distance D, and vector store element number E sent via 01, vector store start address B and end address = start address B + vector element distance D x vector store Number of elements E
Calculate and store the results. In addition, in the tag registration invalidation circuit 1, vector store addresses B, (B+D), (B+2D), ... (B+E×D) are determined from the vector store information sent via the path 101.
Create the tag address information 1 of the tag storage circuit 8.
Compare with 08. If ratio matching is achieved, it indicates that the vector store address is registered in the tag storage circuit 8, so the vector store operation is not performed on the main memory 5 where the vector store operation is performed.The contents of the buffer memory circuit 10 In order to guarantee this, the tag control circuit 9 is instructed to invalidate the block address of the tag memory circuit 8 which registers the block address on the main memory of the data held in the buffer memory circuit 10. The conversion instruction is transferred via path 109.

When the scalar load control circuit 6 receives a subsequent scalar data load command from the finger circuit 1 via the path 106 while executing the tag registration invalidation process for the vector store command, the scalar load address information is transferred via the path 116. The signal is then transferred to the area detection circuit 12, via the path 115 to the tag storage circuit 8 and the tag registration invalidation instruction circuit 11, and via the path 112 to the buffer memory circuit 10 together with the scalar load command signal.
When receiving a scalar load command, area detection circuit 1
In step 2, the scalar load address sent together is compared with the output 105 of the vector store address area register 7, and it is compared whether the scalar load address is within the vector store address area. The in-area detection signal is sent to the scalar load control circuit 6 via a path 107.
is sent to interrupt the scalar load operation.

If the in-area detection signal is not output, it is first checked whether or not the scalar load address is registered in the tag storage circuit 8. If it is registered, the scalar data read from the buffer memory circuit 10 is transferred to the scalar load address via the path 113. The signal is sent to the arithmetic circuit 13. If the scalar load address is not registered in the tag storage circuit 8, block data including the scalar load address data is registered in the buffer memory circuit 10 from the main memory 5 via the path 11. The block address including the scalar load address in the tag storage circuit 8 is also stored in the tag control circuit 9.
is registered according to the instructions of the buffer memory circuit 10.
The scalar load data is read out again from the scalar calculation circuit 13, and the load data is sent to the scalar calculation circuit 13.

Next, one implementation of the tag storage circuit 8 and the tag registration invalidation instruction circuit 11 will be further explained using FIG.

Vector store command passes from command circuit 1 to pass 10
1 to the tag registration invalidation circuit 11, the start address B of the vector store, the distance D between vector elements, and the number of elements E of the vector store, which are sent together, are respectively sent to the start address register 20.
1, vector element distance register 202, and element number register 203 are set.

The output of the start address register 201 is sent to the adder input register 205 via the switching circuit 204, and the output of the vector element distance register 202 is sent to the adder 206. Adder 206 adds the output of adder input register 205 and the output of vector element distance register 202, and the result is sent to switching circuit 204 and vector store address register 207. Vector address register 2
The output of 07 is set to the tag search address register 301 in the tag storage circuit 8 via the switching circuit 300 every time the result of the adder 206 is set. Further, a vector store address is set in the vector address register 207 E times, the number of elements, and transferred to the tag storage circuit 8 E times as a vector store address. Creation and transfer of vector store addresses are performed using the number of elements register 20.
Each time a vector store address is created and transferred, the subtracter 209 increments the output of 3 by 1, and the output of the subtraction result register 210 continues until the vector store address control circuit 211 detects zero. The switching circuits 204, 208 and 300 are controlled by a vector store address control circuit 211. A detailed explanation of the operation will be omitted since it has little to do with the present invention.

When a vector store address is set in the tag search address register 301, the address in the lower block of the address is sent to the tag memory 302 and the tag V set memory 30 via a path 307.
6, the corresponding block address and V
The bits are read and sent to comparison circuits 212, 213 and AND gates 214, 215. In this embodiment, the buffer memory 2 is considered to be a compartment (level).The comparison circuits 212 and 213 use the output of the tag memory 302 and the tag search address register 3.
01 is compared with the upper block address information, and the comparison result is ANDed with the output of the tag V bit memory 306 for each level by AND gates 214 and 215.
Each condition is taken. A tag V-bit memory 30 that displays a comparison match in the comparison circuit 212 or 213 and the validity of the corresponding block address.
If the output of 6 is "1", the level "0" match flag register 218 or the level 1 match flag register 219 is set, the OR gate 220 takes the logical sum of the match signals of both levels, and the bit signal becomes the bit display flag. It is set in register 217.

When the hit display flag register 217 is set, the address information in the lower block of the tag search address register 301 is set in the invalidation address register 216, and the tag control circuit 9 receives the pass 10.
Transferred via 9. In the tag control circuit 9, the output of the hit display flag register 217 is ANDed with the timing signal by an AND gate 401, and is stored in the tag V bit memory 306 in the tag storage circuit 8.
It is indicated by the output of AND gate 402. An instruction signal is sent along path 114 with the output of invalidate write address register 400 to set the level V bit to "0". Here, the output of the "0" level signal 304 is selected by the switching circuit 305 as the write input for setting the V bit of the tag V bit memory 306 to "0". The above is the explanation of the invalidation processing method for the vector store address of the tag storage circuit 8.

Next, the vector store address area register 7 and area detection circuit 12, which are features of the present invention, will be explained using the embodiment block diagram of FIG.

When a vector data store command is issued from the command circuit 1 to the vector store address area register 7 via the path 101, the start address B of the vector store, the distance D between vector elements, and the number of elements E of the vector store, which are sent together, are respectively started. The address register 600, vector element distance register 601, and number of elements register 602 are set.

The output of the start address register 600 is sent to the adder 6
04 and vector store start address register 60
Sent to 6. The outputs of the inter-element distance register 601 and the number of elements register 602 are input to the multiplier 603, and the output of the vector element distance D x the number of elements of the vector store E is input to the adder 604.
From 04 onwards, the calculation result of start address B+distance between vector elements D×number of vector store elements E is set in vector store end address register 605. These two registers 605 and 60
The contents of 6 are valid until the vector store address control circuit 211 detects that the number of remaining vector elements is zero. In other words, the vector store start address register 6 is used only while tag registration invalidation processing is being executed in response to a vector data store command.
06 and vector store end address register 60
The contents of 5 are valid, and during other periods, for example, they are cleared and all values of "0" are set, and have invalid contents.

When the values in the registers 605 and 606 are set and the subsequent scalar data load command is issued from the command circuit 1 to the scalar load control circuit 6 while tag registration invalidation processing is being executed, the commands are transferred together. Along with scalar data load address information, an access control signal to the area detection circuit 12, tag storage circuit 8, buffer memory circuit 10, etc. is generated. The scalar load control circuit 801 is activated, and the scalar load address information is transmitted to the area detection circuit 12, the tag storage circuit 8, and the buffer memory circuit 1.
Sent to 0.

In the area detection circuit 12, a subtracter 700 subtracts the scalar load address information 116 from the output of the vector store end address 605, and if the result sign is a positive value, a subtraction possible (carry out) signal 703 is generated.
is served. On the other hand, the subtracter 701 conversely subtracts the output of the vector store start address register 606 from the scalar load address information 116, and similarly, if the result is a positive value, a subtraction possible (carry out) signal 704 is output.

That is, if the signal 703 and the signal 704 are ANDed by the AND gate 702, it means that the scalar load address is between the vector store start address and the vector store end address. In this case, there is a possibility that the scalar data load address and the vector data address match, and if the scalar data load is executed before the tag registration invalidation process is completed, the contents of the main memory 5 will be changed in the vector store. Buffer memory circuit 1 before the change
This results in loading the contents of 0. Therefore, if the AND gate 702 meets the AND condition, a scalar load inhibit signal 107 is sent to the scalar load control circuit 6 to interrupt the scalar load process.

Advantages of the Invention The present invention has the advantage that a subsequent scalar load command can be executed during vector store command operation processing.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing a detailed configuration of the tag registration invalidation instruction circuit and tag storage circuit in FIG. 1, and FIG. 3 is a diagram showing the vectors in FIG. 1. FIG. 3 is a diagram showing a detailed configuration of a store address area register and an area detection circuit. In FIGS. 1 to 3, 1...command circuit;
2, 3, 4...vector arithmetic processing unit, 5...main storage device, 6...scalar load control circuit, 7...
...Vector store address area register, 8...
Tag storage circuit, 9... Tag control circuit, 10... Buffer memory circuit, 1... Tag registration invalidation instruction circuit, 12... Area detection circuit, 113... Scalar arithmetic circuit, 14... Scalar arithmetic processing device, 201
...Start address register, 202...Vector element distance register, 203...Element number register, 204...Switching circuit, 205...Adder input register, 206...Adder, 207...Vector store address register, 208...Switching circuit, 209...Subtractor, 210...Subtraction result register, 211...Vector store address control circuit, 212, 213...Comparison circuit, 214, 21
5...AND gate, 216...Invalidation address register, 217...Hit display flag register, 218...Level 0 match flag register, 2
19...Level 1 match flag register, 220...
...OR gate, 300...switching circuit, 301...
Tag search address register, 302...Tag memory, 303..."1" level signal, 304...
"0" level signal, 305...Switching circuit, 306
...tag V bit memory, 400 ... invalidation write address register, 401 ... AND gate, 4
02...AND gate, 600...start address register, 601...vector element distance register, 602...element number register, 603...multiplier, 604...adder, 605...vector store end address register, 606...Vector store start address register, 700...Subtractor,
701...Subtractor, 702...AND gate, 7
03,704...Subtractable signal, 801...Scalar load control circuit, 107...Scalar load inhibition signal.

Claims (1)

[Scope of Claims] 1. A main storage device; and at least one vector operation having at least one data transmission/reception path between the main storage device and capable of simultaneously accessing a plurality of vector element data in the main storage device. a processing unit; a scalar arithmetic processing unit having a data transmission/reception path between the main storage device; and a scalar arithmetic processing unit that transmits vector data or slower data to the vector arithmetic processing unit or the scalar arithmetic processing unit according to program instructions. an information processing system having command means for issuing load and store operation commands, buffer memory means having a data transmission/reception path with the main memory and storing a copy of a part of the data in the main memory; a tag storage means for registering block address information of the main storage device corresponding to data stored in the buffer memory means; a tag control means for controlling new registration of block address information in the tag storage means or invalidation processing of the registered address; In response to a vector data store operation command from the command means, each store address for a plurality of vector element data generated in response to the command is checked to see if it is registered in the tag storage means. tag registration invalidation instructing means for instructing the tag control means to invalidate the registered address if the registered address is invalidated; and the vector store operation command and the vector store start address and vector element data generated in accordance with the command. a vector store area storage means for storing a store start address and a store end address in main memory where the vector store is executed based on the distance between the vector stores and the number of elements of the vector store; When a subsequent scalar data load command is received from the command means before the operation of the tag registration invalidation instruction means is completed, the scalar data load address received in conjunction with the command is indicated in the vector store area storage means. an area detecting means for checking whether or not the address is within an address area and outputting an in-area detection signal if it is within the area; An information processing system comprising: scalar load control means for controlling scalar load command processing to be interrupted when an in-area detection signal is received.