JPH0284765A - Semiconductor memory device and its manufacture - Google Patents

Abstract

PURPOSE:To remove a trouble in the connection between the lower electrode of a capacitor and the diffused layer on one side of a transfer gate transistor by a method wherein the diffused layer, to which the lower electrode of the capacitor is connected, on one side of the transistor is formed of a low- concentration n-type diffused layer only. CONSTITUTION:A MIS transfer gate transistor is formed on a p-type semiconductor substrate 21 and moreover, a capacitor is piled up and formed on the transistor. In such a semiconductor memory device, the transistor consists of a gate insulating film 23, a gate electrode 24, low-concentration n-type diffused layers 25 formed in the substrate 21 on both sides of the electrode 24 and a high- concentration n<+> diffused layer 27 provided in the substrate 21 on one side of the electrode 24 and the capacitor consists of a lower electrode 28 connected to the layer 25 on the side, where said layer 27 is not formed, a dielectric thin film 29 on the electrode 28 and an upper electrode 30 on the film 29.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor memory device and a method of manufacturing the same, and more particularly to a MIS type dynamic random access memory and a method of manufacturing the same.

(Prior Art) The number of integrated bits per chip of MIS-type dynamic random access memory (hereinafter referred to simply as DRAM) has quadrupled in about three years.

High integration of DRAM is a must! The middle point is miniaturization of memory cells, which occupy about 50% of the area.

In a DRAM of 16 kilobits or more, one cell (one bit) consists of one capacitor and one switching transistor, which is the most single ITr/10! Cells have been used for this purpose, and if the cells are simply reduced in size, the capacitance of the capacitor decreases, and the soft error phenomenon in which stored information is reversed due to the incidence of alpha particles becomes noticeable.

Therefore, there is a way to ensure a large capacitance even if the cell size is reduced, for example, by Oki Electric Research & Development 13153 [3]
(1986-7) This was done as shown in PP75 to 82.According to this, the capacitors were formed three-dimensionally by stacking them on the field oxide film and transistors, effectively increasing the size of the capacitors. Obtaining capacitance. Such cells are generally called stacked capacitor cells.

The main structure of this star cell is explained using the sectional view of FIG. 4. A switching transfer gate transistor is formed in an active region surrounded by an isolation field oxide film 2 selectively formed on a Pffi silicon substrate 1. This transfer transistor is composed of a gate oxide film 3, a gate electrode 4, a pair of N- diffusion layers 5, a sidewall 6, and a pair of N+ diffusion layers 7. Here, the pair of N+ diffusion layers 7 are formed of dope with a high concentration of As (arsenic). Then, the N-type diffusion layer 7 and the N- diffusion layer 5 form a source/drain diffusion layer of an LDD structure. In addition, the gate electrode 4 also functions as a word line,
It extends in a direction perpendicular to a bit line, which will be described later. An information storage capacitor is formed by stacking the transfer gate transistor and the field oxide film 2 on top of each other. This capacitor is formed of a lower electrode 8 made of polysilicon containing a high concentration of impurities (phosphorus), a dielectric thin film 9, and an upper electrode 1o.・Connected to one diffusion layer of the drain through the N-type diffusion layer 7. The upper electrode 10 is connected to a fixed potential (1/2 vee ). On the other hand, a bit line 13 is connected through a contact hole 12 to a portion of the N-type diffusion layer 7 of the other source/drain diffusion layer of the transfer transistor.

The bit line 13, the gate electrode 4, and the capacitor/base are insulated from each other by a glabella insulating film 14.15, and the contact hole 11.12 is formed in the interlayer insulating film 14, 15. ing. Further, a pad page carbon film 16 is formed on the entire surface.

(Problems to be Solved by the Invention) However, in the conventional configuration as described above, in the connection between the lower electrode 8 of the canister and the diffusion layer of one of the source and drain of the transfer gate transistor, the following happens. There was a problem.

■ The lower electrode 8 of the capacitor is connected to the N diffusion layer 7, but since accelerated diffusion of PCIJ occurs in the N+ diffusion layer 7 doped with Aa at a high concentration, the lower electrode 8 is connected to the N diffusion layer 7. Phosphorus in the formed polysilicon diffuses into the substrate l, forming a deep junction (portion 170 in FIG. 4).

For this reason, the collection efficiency of carriers generated by alpha particles incident on the substrate 1 is increased, and the occurrence rate of phantom errors that destroy memory information is increased.

(2) The surface of the N-type dispersion layer 7 into which impurities are implanted at a high concentration is easily oxidized even at low temperatures, and good ohmic contact with the lower electrode 8 of the capacitor cannot be obtained.

The object of the present invention is to eliminate the above-mentioned problems in the connection between the lower electrode of the canacitor and the diffusion layer of the transfyl'-'p transistor.

Means for Solving the CS Problem) In the present invention, one diffusion layer of the transfer gate transistor to which the lower electrode of the capacitor is connected is formed only of a lightly doped N-type diffusion layer.

Further, in the third aspect of the present invention, when forming a capacitor,
The lower electrode of the middle layer is formed of a non-doped silicon layer, a dielectric thin film is formed on it, and round arsenic ions are implanted into the lower electrode polysilicon layer through the dielectric thin film to impart conductivity. conduct.

(Function) As described above, if one diffusion layer of the transformer 7 agot2 innostar to which the lower electrode of the capacitor is connected is formed of only a low concentration N type diffusion layer, even if the lower electrode of the capacitor is Even if the impurity contained in the silicon layer is phosphorus, the impurity will not diffuse deeply into the substrate, and no deep junction will be formed. Moreover, if arsenic is used as an impurity as in the third aspect of the present invention, since the diffusion coefficient of arsenic is small, it is further ensured that arsenic will not be diffused deeply into the substrate. Further, according to the low concentration Na diffusion layer, an oxide film is hardly formed on the surface. Furthermore, like this third invention,
If the lower electrode polysilicon layer is doped with impurities after forming the dielectric thin film, the natural oxide film formed on the surface of the polysilicon layer during the formation of the dielectric thin film becomes thinner.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings. FIG. 1 is a sectional view showing an example of a semiconductor mesori device of the present invention. In this figure, reference numeral 21 denotes a P-type silicon substrate, and an MIS is installed in an active area surrounded by a field oxide film 22 for isolation selectively formed on this substrate 21.
A type of transfer gate transistor is formed. This transfer gate transistor consists of a gate oxide film 23 formed on the surface of a substrate 21 and 1. R-meter electrode 24 formed thereon, substrate 21 on both sides of the gate electrode 24
an N- diffusion layer 25 formed within the gate electrode 240;
Sidewalls 26 formed on both sides, N-type dispersion layer 2 formed only in the substrate 21 on one side of the gate electrode 24
It consists of 7. On the side where the N+ diffusion layer 27 is formed, the diffusion layer of the transfer gate transistor is formed in the LDD structure with the N'' diffusion layer 25. On the opposite side, a diffusion layer of the transformer 7 is formed of only the N- diffusion layer 25. Note that the f-meter electrode 24 also functions as a word line and extends in a direction perpendicular to a pit line, which will be described later. A canadacillator for information storage is further formed so as to be stacked on such a transfer gate transistor and field oxide film 22. This canister includes a lower electrode 28 formed of 4-silicon containing impurities, a dielectric thin film 29 formed thereon, and an upper electrode 3 formed thereon.
The lower electrode 28 is connected through the contact hole 31 to the N- diffusion layer 25 of the transistor on the side where the N-type dispersion layer 27 is not formed.

On the other hand, a contact hole 32 is provided in the N2 diffusion layer 27 of the transfer r-transistor located on the opposite side.
A bit line 33 is connected through it. The bit line 33, the gate electrode 24, and the contact hole 3 are insulated from each other by interlayer insulating films 34 and 35.
1 and 32 are formed. Further, the entire surface is covered with a pudge page carbon film 36.

Such a semiconductor memory device is manufactured by the first embodiment of the manufacturing method of the present invention shown in FIG. The manufacturing method will be explained next.

First, a field oxide film 22 is selectively formed on the surface of a P-base silicon substrate 210 by a selective oxidation method or the like. Next, a gate oxide film 23 is formed to a thickness of about 25 nm on the surface of the substrate 21 in the active region surrounded by the field oxide film 22. Then, a gate electrode 24 is formed on the gate oxide film 23 (FIG. 2(4)). This gate electrode 24 is made by depositing polysilicon on the substrate 21 to a thickness of about 300 nm by LPCVD (low-pressure chemical vapor deposition), and then doping it with phosphorus at a high concentration to give conductivity to the polysilicon. and then by turning/turning the phosphorus polysilicon using conventional photolithography and dry etching techniques.

Next, using the gate electrode 24 and the field oxide film 22 as a mask, IX10LS~5X1011013
By ion-implanting phosphorus into the substrate 21 at a dose of ``e'', N is implanted into the substrate 21 on both sides of the gate electrode 24.
- forming a diffusion layer 25; Thereafter, an oxide film (SiO! film) is deposited on the entire surface using the CVD method, and the oxide film is etched on the entire surface using anisotropic RIE (reactive ion etching) to form sidewalls 26 on both sides of the gate electrode 240. Form.

(FIG. 2 (11)) Next, the surface of the substrate 21 on one side of the gate electrode 24 is covered with a resist pattern 41. Then, using the resist pattern 41, the gate electrode 24, and the sidewall 26 as a mask, arsenic is removed from the substrate 21. The ion implantation was carried out at a dose of 5 x 101IIe+-''! Next, the N+ diffusion layer 27 was formed only in the substrate 21 on the opposite side to the side covered with the resist pattern 41 (FIG. 2(c)). Here, CMOS (complementary metal oxide semiconductor) is used in the peripheral circuit.
When using N-channel transistors, SiSist/9 turning is performed to separately form the N+ diffusion layer for the N-channel transistor and the P-type diffusion layer for the P-channel transistor. If the resist patterning for forming the N+ diffusion layer for the channel transistor and the resist/turning for forming the N+ diffusion layer 27 only on one side are performed using the same photomask, the number of steps will not increase.

Next, after removing the resist pattern 41 and further removing unnecessary parts of the f-t oxide film 23, a glabellar insulating film 34 is formed on the entire surface including the tops of the diffusion layers 25 and 27 and the tops of the gate electrodes 24.
An oxide film is deposited by CVD. A contact hole 31 is formed in the glabellar insulation film 34 so as to penetrate through the y diffusion layer 25 on the side where only the N- diffusion layer 25 is formed. [FIG. 2(G)] Thereafter, the lower electrode 28 of the capacitor is formed on the interlayer insulating film 34 so as to be connected to the bottom N- diffusion layer 25 through the contact hole 31 (FIG. 2@). This lower electrode 28fi is made of polysilicon layer with a film thickness of 2 by LPCVD method.
After depositing the polysilicon layer to a thickness of about 0.00 nm over the entire surface, phosphorus is added at 1×1020 to 3×1 to give conductivity to the polysilicon layer.
It is formed by doping at a concentration of 0"3-" and then repeatedly turning the doped polysilicon layer by conventional photolithography and dry etching. At that time, the portion where the polysilicon layer is connected to the substrate 21 is N
- Diffusion layer 25, thus suppressing accelerated diffusion of phosphorus from the polysilicon layer to the substrate 21 and low-temperature oxidation of the surface of the substrate 21.

Thereafter, a silicon nitride film 42, which will become the dielectric thin film of the canister, is coated on the entire surface including the top of the lower electrode 28 using monosilane (Si).
LPCV using H,) and ammonia (N'H4) gas
The film is deposited to a thickness of 10 nm using the D method. Thereafter, in order to reduce the leakage current of the silicon nitride film 42,
Annealing is performed in a wet oxygen atmosphere at ~950° C. to form an oxide film (not shown) with a thickness of about 2 nm on the surface of the silicon nitride film 42. Thereafter, a polysilicon layer 43 for forming an upper electrode of the capacitor is formed on the silicon nitride film 42 having the oxide film on its surface. After doping the polysilicon layer 43 with impurities, the polysilicon layer 43 and the silicon nitride film 42 (having an oxide film on the surface) are repeatedly turned.
The upper electrode 30 of the capacitor and the dielectric thin film 29 are formed so as to extend from above onto the glabellar insulating film 34 . (Figure 2■
) Thereafter, BPSG (
Deposit a poron phosphosilicate glass) film. Then, the second interlayer insulating film 35 and the interlayer insulating film 34
A contact hole 3 is formed so as to penetrate through the N+ diffusion layer 27.
2 is opened, and a bit line 33 is formed of A/-8t alloy so as to be connected to the N+ diffusion layer 27 through the contact hole 32.

(Figure 2 (2)) Finally, a 9% carbon film is formed on the surface.

FIGS. 3(4) to (3) show a second embodiment of the manufacturing method of the present invention, and the semiconductor memory device shown in FIG. 1 can also be manufactured by this manufacturing method.

This second embodiment differs from the first embodiment shown in FIG. 2 in the method of forming the lower electrode 28 of the capacitor. In order to avoid duplication of explanation, only the different parts will be explained. In this second embodiment, as shown in FIG. As shown in FIG. 3, a lower electrode 28 of the capacitor is formed using a non-doped polysilicon layer. Subsequently, as shown in the figure, a silicon nitride film 42 as a dielectric thin film of the capacitor is deposited on the entire surface including the surface of the lower electrode 28 by LPCVD.
Formed to a thickness of nm. After forming this silicon nitride film 42, arsenic ions are implanted into the lower electrode (non-doped polysilicon layer) 28 through this silicon nitride film 42 at a dose of about 1x1016cIR''2 as shown in FIG. to give conductivity.

Thereafter, the steps after the step of forming an oxide film on the surface of the silicon nitride film 42 are performed in the same manner as in the first embodiment shown in FIG.

In the second embodiment shown in FIG. 3, the same parts as those in the first embodiment shown in FIG.

(Effects of the Invention) As explained in detail above, according to the present invention, one diffusion layer of the transfer gate transistor to which the lower electrode of the capacitor is connected is formed only of a low concentration N-type diffusion layer. Form the lower electrode of the armpit/armpit. fl
Even if the impurity contained in the silicone layer is phosphorus, the impurity will not be diffused deeply into the substrate, and deep junctions will not be formed. Therefore, the incidence of soft errors can be dramatically reduced. can. Furthermore, if arsenic is used as an impurity contained in the polysilicon layer, since the diffusion coefficient of arsenic is small, it is further ensured that arsenic will not be diffused deeply into the substrate, and the incidence of soft errors can be further reduced. Further, since an oxide film is hardly formed on one surface of the low concentration N diffusion layer, good contact with the lower electrode of the capacitor can be obtained.

Furthermore, if the polysilicon layer that forms the lower electrodes of the middle layer and armpit is doped with impurities to impart conductivity after forming the dielectric thin film of the capacitor, it is possible to Since the natural oxide film formed on the surface of the polysilicon layer becomes thinner, the increase in capacitance of the capacitor can be suppressed.

[Brief explanation of drawings]

FIG. 1 is a structural cross-sectional view showing one embodiment of the semiconductor memory device of the present invention, FIG. 2 is a process cross-sectional view showing the first embodiment of the method for manufacturing the semiconductor memory device of the present invention, and FIG. Process sectional view showing the second embodiment of the manufacturing method of the invention, No. 4
The figure is a cross-sectional view of the structure of a conventional in-stack yapacita type cell. 21... P-type silicon substrate, 22-- field oxide film, 23... gate oxide film, 24... gate electrode,
25... N-diffusion layer, 26... Side wall, 2
7-.N+ diffusion layer, 28--lower electrode, 29--dielectric thin film, 30--upper electrode, 31--contact hole, 34--interlayer insulating film. 〜〜 Duty G Shizuka Ei Tuna υ 1st II Chiang P Yue's 1st O ■ [J "J Yun's Meji Begging" Cod d My D 2nd Picture Book 6g Moon's O LA Shimi Ai γ Nuta Kaene Epa Dictionary” Part 3
Fig. 1 (σ) λ C i' Shield 7 cross-section 11ff)

Claims (3)

[Claims] (1) In a semiconductor memory device in which an MIS type transfer gate transistor is formed on a P-type semiconductor substrate and a capacitor is formed by stacking the transistor on top of the transistor, the transfer gate transistor has a gate insulating film, a gate electrode, and the gate. The capacitor consists of a low concentration N type diffusion layer formed in the substrate on both sides of the electrode and a high concentration N type diffusion layer provided in the substrate on one side of the gate electrode, and the capacitor is formed by the high concentration N type diffusion layer. 1. A semiconductor memory device comprising: a lower electrode connected to the low concentration N-type diffusion layer on the non-concentrated side; a dielectric thin film above the lower electrode; and an upper electrode above the lower electrode. (2) (a) Forming a gate insulating film on a P-type semiconductor substrate and forming an r gate electrode thereon; (b) Using the gate electrode as a mask, apply low concentration N in the substrate on both sides of the gate electrode. (c) After that, sidewalls are formed on the sides of the gate electrode, and with one surface of the gate electrode covered with a mask, a highly concentrated N-type layer is formed only in the substrate on the opposite side. (d) After that, after removing the mask, an insulating film is formed on the entire surface, and this insulating film has a low concentration N-type layer on the side where the high concentration N-type diffusion layer is not formed. (e) forming a lower electrode of a capacitor on the insulating film so as to be connected to the low concentration N-type diffusion layer at the bottom through the contact hole; f) forming a dielectric thin film on the lower electrode, and further forming an upper electrode of a capacitor thereon. (3) (a) Forming a gate insulating film on a P-type semiconductor substrate and forming a gate electrode thereon; (b) Using the gate electrode as a mask, form a low concentration N-type film in the substrate on both sides of the gate electrode. (c) After that, sidewalls are formed on the sides of the gate electrode, and with one surface of the gate electrode covered with a mask, high-concentration N-type diffusion is performed only in the substrate on the opposite side. (d) After that, after removing the mask, an insulating film is formed on the entire surface, and this insulating film includes a low concentration N-type diffusion layer on the side where the high concentration N-type diffusion layer is not formed. (e) forming a lower electrode of a capacitor with a non-doped polysilicon layer on the insulating film so as to be connected to the low concentration N-type diffusion layer at the bottom through the contact hole; (f) forming a dielectric thin film on the lower electrode non-doped polysilicon layer; (g) arsenic ions to impart conductivity to the lower electrode non-doped polysilicon layer through the dielectric thin film; A method for manufacturing a semiconductor memory device, comprising the steps of: performing implantation; and (h) thereafter forming an upper electrode of a capacitor on a dielectric thin film.