JPH0269943A - Compound semiconductor device and its manufacturing method - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor device and a method for manufacturing the same, and particularly to a compound semiconductor device suitable for integrated circuits.

(Prior technology) Beterojunction bipolar transistors (HBTs) using compound semiconductors have low power consumption due to their high speed and excellent current drive ability.
/f (HBT) is attracting attention as an element for ultra-high frequency and ultra-high speed digital and analog ICs due to its excellent noise characteristics.The only drawback of this HBT is that it consumes a large amount of power.On the other hand, two-dimensional Electron gas field effect transistor (
FET) (2DEGFET, which is a synonym for HEMT and is □) has low power consumption, high speed, and low high-frequency noise characteristics, but has the drawbacks of low current drive ability and large IK noise. For this reason, HBT and 2
Research and development is being carried out to integrate dimensional electron gas FETs on the same semiconductor chip, compensate for each other's weaknesses, and maximize the advantages of both. For example, in a microwave monolithic reception front end, a two-dimensional electron gas FET is used in a low-noise amplification section, and an HBT is used in a local oscillation section and a mixing section.

Figure 4 shows the conventional AlGaAs/GaAs HBT and Al
This is a GaAs/GaAs 2DEGFET hybrid integrated circuit.

In this figure, an n+-GaAs layer 33, an n-GaAs layer 34, a p
”-GaAs layer 35, n-AlGaAs layer 36, n+-
An emitter electrode 38 made of AuGeNi, a base electrode 39 made of AuMnNi, and a collector electrode 4 made of AuGeNi are formed on the crystal structure made of the GaAs layer 37.
0 is formed to constitute an HBT. Furthermore, GaAs
On other parts of the substrate 30, a non-doped GaAs layer 31, n
-A gate electrode 41 made of AI and a source electrode 4 made of AuGeNi on a crystal structure made of an AlGaAs layer 32
2 and a drain electrode 43 are formed. FIG. 5 shows a band diagram when bias is applied along dashed-dotted lines A and B in FIG. 4. The reference numbers in FIG. 5 are the same as in FIG. Figure 5A is a typical HB
T structure, B is a typical 2DEGFET structure.

(Problems to be Solved by the Invention) In the conventional example described above, the active layers of the HBT and 2DEGFET are formed by selective epitaxial growth, but the selective epitaxial growth method does not provide uniformity for fine structures with different shapes. Not enough, especially 2DEGFET
The threshold voltage ■7 and the minimum noise figure vary,
In addition, there were drawbacks such as a longer manufacturing process and higher costs.

The purpose of the present invention is to eliminate the above-mentioned drawbacks, and to produce compound HBT and FE using only the full-surface epitaxial growth technology that has good uniformity and can shorten the process, without relying on selective epitaxial technology.
An object of the present invention is to provide a T-hybrid integrated circuit.

(Means for Solving the Problems) A compound semiconductor device of the present invention for achieving the above object is a semiconductor device in which a heterojunction bipolar transistor and a two-dimensional electron gas FET are configured on the same semiconductor chip. A non-doped first semiconductor layer, a second semiconductor layer of a first conductivity type having a lower electron affinity than the first semiconductor layer, and a highly doped third semiconductor layer of the first conductivity type are formed on a semi-insulating compound semiconductor substrate in this order. A fourth semiconductor layer of the first conductivity type, which becomes a collector layer, is placed at a predetermined position on the semiconductor substrate on which the semiconductor layer is formed.
a highly concentrated fifth semiconductor layer of a second conductivity type that serves as a base layer; and a sixth semiconductor layer of a first conductivity type that has a wider band gap than the fifth semiconductor layer and serves as an emitter layer. and a highly doped seventh semiconductor layer serving as a cap layer.
The third semiconductor layer at another predetermined position on the semiconductor substrate is removed, and a Schottky metal serving as a gate electrode is provided on the exposed second semiconductor layer, sandwiching the gate electrode and parallel to the third semiconductor layer. A plurality of two-dimensional electron gas FETs each having an ohmic metal serving as a drain electrode and a source electrode are disposed on a third semiconductor layer adjacent to the third semiconductor layer, and an inter-element isolation region is provided between these transistors. It is characterized by Furthermore, the manufacturing method for realizing the above structure includes: a non-doped first semiconductor layer on the entire surface of the semi-insulating compound semiconductor substrate; a second semiconductor layer of a first conductivity type having a lower electron affinity than the first semiconductor layer; a highly doped third semiconductor layer of the first conductivity type, a fourth semiconductor layer of the first conductivity type, a highly doped fifth semiconductor layer of the second conductivity type, and a third semiconductor layer having a wider bandgap than the fifth semiconductor layer. a sixth semiconductor layer of one conductivity type;
A step of sequentially forming a highly concentrated seventh semiconductor layer of the first conductivity type, etching the seventh and sixth semiconductor layers except for a predetermined position where an emitter electrode of a heterojunction bipolar transistor is to be provided, and forming a base electrode. exposing the third semiconductor layer by etching the fifth and fourth semiconductor layers except for the positions where the emitter electrode and the base electrode are provided; ,
Said No. 7. An ohmic metal is deposited on the fifth semiconductor layer to serve as an emitter electrode and a base electrode, respectively, and an ohmic metal is deposited on the third semiconductor layer adjacent to the fourth semiconductor layer to serve as a collector electrode. the step of attaching the gate electrode of the two-dimensional electron gas FET;
A step of etching the second semiconductor layer to expose the second semiconductor layer and depositing a Schottky metal at this position, and forming a drain electrode on the third semiconductor layer adjacent in parallel with the Schottky metal sandwiched therebetween. and a step of depositing an ohmic metal that will become a source electrode, and a third step around the heterojunction bipolar transistor and the two-dimensional electron gas FET. isolation ion implantation into the second and first semiconductor layers; The method is characterized in that it includes a step of etching and removing the second and first semiconductor layers.

(Example) FIG. 1 and FIG. 2 show an example of the compound semiconductor device of the present invention, and FIG. 3 shows an example of the present invention regarding its manufacturing method.

In FIG. 1, an emitter electrode 8 made of AuGeNi is provided on an emitter cap layer made of an n+-GaAs layer (concentration 5×101B, thickness 100OA) 7 of the seventh semiconductor layer, and AlGaAs layer (
P+-GaAs of the fifth semiconductor layer forming a heterojunction with a concentration of 3 x 1017 cm-3 and a thickness of 1500 cm
A base electrode 9 made of AuMnNi is provided on the surface of the substrate 5 (concentration 4×10′ cm=, thickness 500).

As the fourth semiconductor layer, an n-GaAs layer (concentration 5×101
The collector layer consists of a third semiconductor layer, an n+-GaAs layer (concentration 5 x 10
18cm-3, thickness 4000A) 3, and the surface of the n+-GaAs layer 3 is made of AuGe.
A collector electrode 10 made of Ni is provided and made of AlGaAs.
/GaAs HBT is constructed. Under the third semiconductor layer n+-GaAs layer 3, an n-A layer is formed as a second semiconductor layer.
Although the undoped GaAs layer 1 is provided as the lGaAs layer 2 and the first semiconductor layer, it does not affect the operation of the HBT. A band diagram along the dashed line A-A in FIG. 1 is shown in FIG. 6. The reference numbers are the same as in FIG. Since current flows in the n''-GaAs layer 3, which is the sub-collector layer, in the direction perpendicular to the plane of the paper, discontinuities in the bottom of the conduction band occur between the n+-GaAs layer 3, the n-AlGaAs layer 2, and the non-doped GaAs layer 1. is not a problem at all, but rather has the effect of improving isolation from the substrate 15.

On the other hand, a part of the n+-GaAs layer 3 is removed and the n-AlG
A gate electrode 11 made of A1 is placed on the surface where the aAs layer 2 is exposed.
is provided, and an n+-GaAs layer 3 near this gate electrode is provided.
A source electrode 12 and a drain electrode 13 made of AuGeNi are provided on top of the 2DE with a recessed gate structure.
A GFET is configured. HBT and 2DEGFE
The area around the T is insulated by boron ion implantation to create an isolation region between the elements. In the embodiment of FIG.
The area around the 2DEGFET is etched to form an isolation region 18 (device isolation) between elements. The reference numbers in FIG. 2 are the same as in FIG.

FIG. 3 shows a manufacturing method according to an embodiment of the present invention.
), non-doped GaAs layers 1, n
-AlGaAs layer 2, n''-GaAs layer 3, n-G
aAs layer 4, p+-GaAs layer 5, n-AlGaAs
Layer 6 and n-AlGaAs layer 7 are grown in sequence. (b)
In this step, an emitter mesa and a base mesa are formed using photoresist or the like as a mask. Next, in (C), Au is deposited on the n-AlGaAs layer 7 which becomes the emitter cap layer
An emitter electrode 8 made of GeNi and a p
A base electrode 9 made of AuMnNi on the "-GaAs layer 5" and a collector electrode 10 made of AuGeNi on the n+-GaAs layer 3 serving as a sub-collector layer are successively formed by a photoresist lift-off method.Furthermore, in (d) n+-GaAs using photoresist 51 as a mask.
Layer 3 is etched and then Schottky metal A111 is vertically evaporated. Thereafter, A1 on the resist is removed by a photoresist lift-off method. next(
In e), AuGe was removed by photoresist lift-off method.
A source electrode 12 made of Ni and a drain electrode 13 made of the same AuGeNi are formed at the same time.

Finally, (0) selectively implant poron ions into the periphery 17 of the device using the photoresist as a mask.
Etch 7.

(Effects of the Invention) In the compound semiconductor device and manufacturing method thereof of the invention, the compound H
A BT and a 2DEGFET can be formed in a mixed manner on the same semiconductor chip. Therefore, not only the device characteristics become uniform, but also the crystal growth process can be shortened, and a high-performance integrated circuit can be provided at low cost.

Although GaAs is used as the compound semiconductor substrate in the embodiment of the present invention, the material is not limited to GaAs, and may be any other material such as InP. Furthermore, it goes without saying that the method can be applied to any number of atoms, not just two.

Although n+-GaAs was used for the cap layer of the HBT, the cap layer may also be a semiconductor such as n+-InGaAs or n''-Ge. A graded structure may also be used.

[Brief explanation of the drawing]

FIGS. 1, 2, and 3 (a) to (O are diagrams for explaining the present invention in detail, and FIG. 6 is a diagram showing the energy band structure of the semiconductor device shown in the embodiment of the present invention. , FIG. 4 is a cross-sectional view of a conventional compound semiconductor device, and FIGS. 5A and 5B are diagrams showing its energy band structure. 1, 31--Non-doped GaAs layer, 2.6.32.
36·-·n-AlGaAs layer, 3.33·n+-Ga
As layer, 4.34·n-GaAs layer, 5,35-p”-
GaAs layer, 7.37-n+-GaAs layer, 8.38-
...Emitter electrode, 9,39...Base electrode, 10.
40...Collector electrode, 11.41...Gate electrode, 12.42...Source electrode, 13.43...Drain electrode, 15.30...Semi-insulating GaAs substrate, 1
4.17.18... Inter-element isolation region, 101...H
BT, 102...2DEGFET.

Claims (2)

[Claims] (1) In a semiconductor device in which a heterojunction bipolar transistor and a two-dimensional electron gas field effect transistor are configured on the same semiconductor chip, the heterojunction bipolar transistor is formed on a semi-insulating compound semiconductor substrate with a non-doped first semiconductor. layer, a second semiconductor layer of the first conductivity type having a lower electron affinity than the first semiconductor layer, and a third semiconductor layer of the first conductivity type with high concentration are formed at a predetermined position on the semiconductor substrate, a fourth semiconductor layer of a first conductivity type that serves as a collector layer; a fifth highly doped semiconductor layer of a second conductivity type that serves as a base layer; and an emitter layer that has a wider band gap than the fifth semiconductor layer. The two-dimensional electron gas field effect transistor includes a sixth semiconductor layer of the first conductivity type, and a seventh semiconductor layer of high concentration, which serves as a cap layer. The third semiconductor layer is removed, a Schottky metal serving as a gate electrode is provided on the exposed second semiconductor layer, and a drain electrode and a source electrode are provided on the third semiconductor layer on both sides of the gate electrode. What is claimed is: 1. A compound semiconductor device comprising an ohmic metal, and an inter-element isolation region is provided between these transistors. (2) A non-doped first semiconductor layer on the entire surface of the semi-insulating compound semiconductor substrate, a second semiconductor layer of a first conductivity type having a lower electron affinity than the first semiconductor layer, and a third semiconductor layer of a highly concentrated first conductivity type. a fourth semiconductor layer of the first conductivity type, a fifth semiconductor layer of the second conductivity type with high concentration, and a sixth semiconductor layer of the first conductivity type having a wider band gap than the fifth semiconductor layer. ,
A step of sequentially forming a highly concentrated seventh semiconductor layer of the first conductivity type, etching the seventh and sixth semiconductor layers except for a predetermined position where an emitter electrode of a heterojunction bipolar transistor is to be provided, and forming a base electrode. exposing the third semiconductor layer by etching the fifth and fourth semiconductor layers except for the positions where the emitter electrode and the base electrode are provided; ,
Ohmic metals are deposited on the seventh and fifth semiconductor layers to serve as an emitter electrode and a base electrode, respectively, and further to serve as a collector electrode at a position adjacent to the fourth semiconductor layer on the third semiconductor layer. a step of depositing an ohmic metal; and a step of depositing an ohmic metal on the third
A step of etching the second semiconductor layer to expose the second semiconductor layer and depositing a Schottky metal at this position, and forming a drain electrode on the third semiconductor layer adjacent in parallel with the Schottky metal sandwiched therebetween. and a step of depositing an ohmic metal that will become a source electrode, and performing isolation ion implantation into the third, second, and first semiconductor layers surrounding the heterojunction bipolar transistor and two-dimensional electron gas FET, or 2. The method of manufacturing a compound semiconductor device according to claim 1, further comprising the step of etching and removing the third, second, and first semiconductor layers.