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JPH0268446U - - Google Patents

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Publication number
JPH0268446U
JPH0268446U JP14864588U JP14864588U JPH0268446U JP H0268446 U JPH0268446 U JP H0268446U JP 14864588 U JP14864588 U JP 14864588U JP 14864588 U JP14864588 U JP 14864588U JP H0268446 U JPH0268446 U JP H0268446U
Authority
JP
Japan
Prior art keywords
package
mounted semiconductor
mount
packaging
making
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14864588U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP14864588U priority Critical patent/JPH0268446U/ja
Publication of JPH0268446U publication Critical patent/JPH0268446U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の一実施例の平面図、第2図は
第1図の側面図、第3図は第1図の背面図、第4
図は本考案の他の実施例の平面図、第5図は第4
図の側面図である。 1……はんだ付け用の電極、2……セラミツク
ケース、3……セラミツクキヤツプ、4……半導
体素子、5……リード。
Figure 1 is a plan view of one embodiment of the present invention, Figure 2 is a side view of Figure 1, Figure 3 is a rear view of Figure 1, and Figure 4 is a rear view of Figure 1.
The figure is a plan view of another embodiment of the present invention, and FIG.
FIG. 1... Electrode for soldering, 2... Ceramic case, 3... Ceramic cap, 4... Semiconductor element, 5... Lead.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 表面実装型半導体装置のパツケージにおいて、
同一外部電極をパツケージの表面および裏面の両
面に配列し、これにより、該パツケージのいずれ
の面に対しても実装可能にしたことを特徴とする
表面実装型半導体装置のパツケージ。
In the packaging of surface-mounted semiconductor devices,
1. A package for a surface-mounted semiconductor device, characterized in that the same external electrodes are arranged on both the front and back surfaces of the package, thereby making it possible to mount the package on either surface.
JP14864588U 1988-11-14 1988-11-14 Pending JPH0268446U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14864588U JPH0268446U (en) 1988-11-14 1988-11-14

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14864588U JPH0268446U (en) 1988-11-14 1988-11-14

Publications (1)

Publication Number Publication Date
JPH0268446U true JPH0268446U (en) 1990-05-24

Family

ID=31420152

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14864588U Pending JPH0268446U (en) 1988-11-14 1988-11-14

Country Status (1)

Country Link
JP (1) JPH0268446U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08213504A (en) * 1995-02-03 1996-08-20 Matsushita Electron Corp Resin-sealed semiconductor device and manufacture thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08213504A (en) * 1995-02-03 1996-08-20 Matsushita Electron Corp Resin-sealed semiconductor device and manufacture thereof

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