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JPH0258793B2 - - Google Patents

Info

Publication number
JPH0258793B2
JPH0258793B2 JP56135172A JP13517281A JPH0258793B2 JP H0258793 B2 JPH0258793 B2 JP H0258793B2 JP 56135172 A JP56135172 A JP 56135172A JP 13517281 A JP13517281 A JP 13517281A JP H0258793 B2 JPH0258793 B2 JP H0258793B2
Authority
JP
Japan
Prior art keywords
solder
container
pads
interconnection
insulating plate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP56135172A
Other languages
Japanese (ja)
Other versions
JPS5835935A (en
Inventor
Nobuhiko Mizuo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP56135172A priority Critical patent/JPS5835935A/en
Publication of JPS5835935A publication Critical patent/JPS5835935A/en
Publication of JPH0258793B2 publication Critical patent/JPH0258793B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49805—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3442—Leadless components having edge contacts, e.g. leadless chip capacitors, chip carriers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3457—Solder materials or compositions; Methods of application thereof
    • H05K3/3478—Applying solder preforms; Transferring prefabricated solder patterns
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/15165—Monolayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10227—Other objects, e.g. metallic pieces
    • H05K2201/10424—Frame holders
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10727—Leadless chip carrier [LCC], e.g. chip-modules for cards
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/04—Soldering or other types of metallurgic bonding
    • H05K2203/041—Solder preforms in the shape of solder balls
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Description

【発明の詳細な説明】 本発明は半導体装置、特に半導体素子収納容器
を配線基体へ相互接続パツドにより接合させた組
立体の接合構成及び方法の改良に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to semiconductor devices, and more particularly to improvements in the structure and method for bonding an assembly in which a semiconductor device storage container is bonded to a wiring substrate by interconnection pads.

高集積度の半導体ICのパツケージ乃至は組立
体の形式としてチツプキヤリアと称されるものが
公知であるが、これはIC素子を封入する通常は
セラミツク製の容器に相互接続用パツドをメタラ
イズパターンによつて設けておき、これをプリン
ト板への実装用接続ピンを有する通常セラミツク
製の配線基体（マザーボード）へ半田によつて接
合する形式のものである。このチツプキヤリアと
配線基体との接合は、夫々に設けた相互接続用パ
ツドの少なくとも一方に半田揚げ又は印刷等の手
法で半田を付着しおき、これにより予め所謂半田
のタマリを形成しておいて、しかる後両者を重ね
合せて熱処理を施すことによつて行なつている。
かかる従来技術においては、パツドへの半田の付
着量が一定せず、半田不足や過剰によつて相互接
続の不完全な箇所や隣接パツド間がシヨートして
しまう箇所しばしば発生するという欠点を生じて
いた。特にチツプキヤリア形式は高集積度ICを
高密度実装する目的で使われることが多いので、
相互接続面には数100μ角の微小なパツドを多数
密集させておくことが要求されるようになつてお
り、上記原因による不良は益々増加する傾向にあ
る。 A well-known type of package or assembly for highly integrated semiconductor ICs is called a chip carrier, which is a container that encloses an IC element, usually made of ceramic, and interconnection pads formed by a metallized pattern. This is of a type that is soldered to a wiring base (motherboard), usually made of ceramic, which has connection pins for mounting on a printed circuit board. The chip carrier and the wiring base are bonded by applying solder to at least one of the interconnection pads provided on each pad by a method such as soldering or printing, thereby forming a so-called solder bulge in advance. This is then done by superimposing the two and subjecting them to heat treatment.
This conventional technique has the disadvantage that the amount of solder attached to the pads is not constant, and insufficient or excessive solder often results in incomplete interconnections or short spots between adjacent pads. Ta. In particular, the chip carrier format is often used for the purpose of high-density mounting of highly integrated ICs.
It has become necessary to have a large number of minute pads of several hundred square micrometers densely packed on the interconnection surface, and the number of defects due to the above-mentioned causes tends to increase more and more.

従つて本発明はかかる半導体収納容器と配線基
板との相互接続パツド半田付けによる接合を行な
うに当り、上記した従来のような接続不完全或い
はシヨートによる不良発生を解消し、また製作工
程もむしろ簡潔化し得る構造及び製法を提供せん
とするものである。 Therefore, the present invention eliminates the above-mentioned problems caused by incomplete connections or shorts when joining the semiconductor storage container and the wiring board by soldering the interconnection pads, and also simplifies the manufacturing process. The aim is to provide a structure and manufacturing method that can be used to

本発明の主たる特徴は、容器と配線基体との間
に絶縁板を介在させ、この絶縁板には各対応パツ
ド間の相互接続部において半田が貫通する孔を設
けた構造にあり、またその製法上の特徴は、各相
互接続部分に対応した位置に貫通孔を有し且つ該
貫通孔に半田が挿入された接続用絶縁板を用意し
て、これを容器と配線基体との間に挾んで重ねた
状態で熱処理し、接合させる工程にある。 The main features of the present invention are that an insulating plate is interposed between the container and the wiring substrate, and this insulating plate is provided with holes through which solder passes through the interconnections between the corresponding pads, and the manufacturing method thereof The above feature is to prepare a connection insulating plate that has through holes at positions corresponding to each interconnection part and insert solder into the through holes, and to sandwich this between the container and the wiring base. The process involves heat-treating the stacked layers and joining them together.

以下本発明を実施例により詳細に説明する。 The present invention will be explained in detail below using examples.

第１図は本発明において使用する接続用絶縁板
の製造方法の１例を示す図である。絶縁板１とし
ては、例えばポリイミドの如き耐熱性のある樹脂
のシート（例えば厚さ100μ）を用い、このシー
ト１に対し、容器と配線基板の相互接続パツドの
パターンに一致した位置に貫通孔２をパンチング
によつて形成しておく。一方、直径500μ程度の
半田ボール３を予め形成しておき、これを第１図
ａの如く貫通孔２上に配置し、上方より平板にて
押圧して各貫通孔２内に半田ボール３を圧入す
る。４は圧入用補助具で、半田ボール３を受ける
凹部５が形成されており、これにより半田ボール
３は圧潰されることなく第１図ｂの如くに貫通孔
へ圧入される。 FIG. 1 is a diagram showing an example of a method for manufacturing a connection insulating plate used in the present invention. As the insulating plate 1, a heat-resistant resin sheet (for example, 100 μm in thickness) such as polyimide is used, and through holes 2 are formed in the sheet 1 at positions corresponding to the pattern of interconnection pads between the container and the wiring board. is formed by punching. On the other hand, solder balls 3 with a diameter of about 500 μm are formed in advance, placed over the through holes 2 as shown in FIG. Press fit. Reference numeral 4 denotes a press-fitting aid, which is formed with a recess 5 for receiving the solder ball 3, so that the solder ball 3 is press-fitted into the through hole as shown in FIG. 1b without being crushed.

半田ボール３は、１箇所の相互接続部分に対し
て適量の半田量分だけのサイズとするものであ
る。 The solder ball 3 is sized to accommodate an appropriate amount of solder for one interconnection portion.

第１図ｂの如き相互接続用の耐熱性シート１を
用意したなら、これを第２図ａの如く、容器１０
と配線基体２０との間に介在させて重ね合わせ
る。第２図において、１１は容器１０側の相互接
続用パツドであり、例えば金のペーストで印刷形
成されたものである。セラミツク製の容器１０
は、本例では典型的なチツプキヤリア形式のもの
であり、１２は封入されたIC素子、１３はリー
ドワイヤ、１４はコバール製の封止用キヤツプ板
である。本発明はこのチツプキヤリアの内部構造
には関係していないので詳細は省略してある。２
１は配線基体（マザーボード）２０側に設けられ
た相互接続用パツドである。配線基体２０も構造
詳細の図示は省略するが、これは例えばセラミツ
ク製の基体であつてスクリーン印刷によるメタラ
イズ配線層が単層又は多層に形成され、必要に応
じて更にプリント板への実装のための接続ピンを
付設したものである。 Once the heat-resistant sheet 1 for interconnection as shown in FIG. 1b is prepared, it is attached to the container 10 as shown in FIG.
and the wiring base 20 and overlap each other. In FIG. 2, reference numeral 11 denotes an interconnection pad on the side of the container 10, which is printed with, for example, gold paste. Ceramic container 10
In this example, is a typical chip carrier type, 12 is an encapsulated IC element, 13 is a lead wire, and 14 is a sealing cap plate made of Kovar. Since the present invention is not concerned with the internal structure of this chip carrier, details are omitted. 2
Reference numeral 1 denotes an interconnection pad provided on the wiring base (motherboard) 20 side. The detailed structure of the wiring base 20 is also omitted, but this is a base made of ceramic, for example, and has a single or multilayer metallized wiring layer formed by screen printing. It is equipped with a connecting pin.

第２図ａの如く絶縁シート１、容器１０、及び
配線基体２０を重ねた状態で熱処理を施すと、半
田ボール３は熔融し、各パツド１１，２１と合金
化して第２図ｂの如く相互接続が行なわれる。こ
こで、各半田ボール３は、従来の如く半田揚や印
刷で半田のタマリを作成する場合と比べると、一
定量とするのが容易であり、各相互接続パツドに
対して常に適量の半田を与えることができるた
め、全てのパツドにおいて再現性良く良好な半田
接続を行なうことができる。しかも絶縁シート１
は半田との濡れが悪いので熔融半田の周囲への拡
がりを抑制すると共に、容器１０と配線基板２０
との間隔を常に一定に保つスペーサとしての効果
も期待でき、それによつて余分な半田の拡がりに
よる隣接パツド間のシヨートも起し難いという効
果も得られる。 When the insulating sheet 1, the container 10, and the wiring base 20 are heat-treated in a stacked state as shown in FIG. 2a, the solder balls 3 are melted and alloyed with the respective pads 11 and 21, so that they mutually interact as shown in FIG. 2b. A connection is made. Here, it is easier to make a fixed amount of each solder ball 3 compared to the conventional method of creating a solder ball by soldering or printing, and an appropriate amount of solder is always applied to each interconnection pad. Therefore, good solder connections can be made with good reproducibility on all pads. Moreover, insulation sheet 1
Because it has poor wettability with solder, it suppresses the spread of molten solder to the surrounding area, and also prevents the container 10 and the wiring board 20 from spreading.
It can also be expected to act as a spacer to keep the distance between pads constant, and thereby prevent shortening between adjacent pads due to the spread of excess solder.

以上のように本発明によれば、各相互接続パツ
ドに対して常に適量の半田を与えることができる
ため、従来経験されたような半田の過不足による
シヨートや接続不良事故を減らすことができ、更
には絶縁板の介在によつて相互接続部の対向パツ
ド間隔が常に一定に保たれて再現性の良い接合を
実現できるものである。そして製造工程において
も、本発明では相互接続用絶縁板を予め別に用意
しておけば、接合工程自体はむしろ従来より短縮
されることになり、組立工程所要時間は短縮され
る効果がある。 As described above, according to the present invention, since the appropriate amount of solder can always be applied to each interconnection pad, it is possible to reduce shorts and poor connection accidents caused by excess or shortage of solder, which have been experienced in the past. Furthermore, by interposing the insulating plate, the distance between the opposing pads of the interconnection portion is always kept constant, making it possible to realize bonding with good reproducibility. In the manufacturing process as well, in the present invention, if the insulating plates for interconnection are prepared separately in advance, the bonding process itself can be shortened compared to the conventional method, and the time required for the assembly process can be shortened.

尚、接続用半田シートとしては上記実施例で説
明した第１図に示すもの以外にも、例えば耐熱性
絶縁シートに設けた貫通孔にリベツト形式の半田
を挿入固定した形態のものや、或いはかがる絶縁
シートの貫通孔に銅のような良導金属のハトメ乃
至リベツトを固定し、その表裏に半田を半球状に
付着させたもの等を用いることができる。 In addition to the solder sheet shown in FIG. 1 explained in the above embodiment, the solder sheet for connection may be one in which rivet-type solder is inserted and fixed into a through hole provided in a heat-resistant insulating sheet, or An eyelet or rivet made of a highly conductive metal such as copper may be fixed in the through hole of an insulating sheet, and solder may be applied in a hemispherical shape to the front and back sides of the eyelet or rivet.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明実施例に使用する相互接続用絶
縁板の製作工程を示す図、第２図は本発明実施例
の半導体装置及びその製造工程を示す図である。 １……絶縁板、３……半田ボール、１０……半
導体素子収納容器、１１，２１……相互接続用パ
ツド、２０……配線基体。 FIG. 1 is a diagram showing a manufacturing process of an interconnection insulating plate used in an embodiment of the present invention, and FIG. 2 is a diagram showing a semiconductor device and its manufacturing process in an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Insulating plate, 3... Solder ball, 10... Semiconductor element storage container, 11, 21... Interconnection pad, 20... Wiring base.

Claims (1)

【特許請求の範囲】 １ 半導体素子を収容する容器と、該容器を搭載
する配線基体とに夫々対応する接続用パツドを設
けておき、各対応するパツドを半田により相互接
続した装置において、前記容器と前記配線基体と
の間に絶縁板が介在し、該絶縁板には前記各対応
するパツドを相互接続する半田が貫通する孔が各
相互接続部分に形成されていることを特徴とする
半導体装置。 ２ 半導体素子を収容する容器と、該容器を搭載
する配線基体とに夫々対応する接続用パツドを設
けておき、各対応するパツドを半田により相互接
続することにより前記容器を前記配線基体へ接合
するに当り、各相互接続部分に対応した位置に貫
通孔を有し且つ該貫通孔に半田が挿入された接続
用絶縁板を、前記容器と前記配線基体との間に介
在させ、熱処理を施すことにより両者を接合させ
ることを特徴とする半導体装置の製造方法。[Scope of Claims] 1. In an apparatus in which connection pads are provided corresponding to a container for housing a semiconductor element and a wiring base on which the container is mounted, and the corresponding pads are interconnected by solder, An insulating plate is interposed between the pad and the wiring substrate, and the insulating plate has holes formed at each interconnection portion through which solder for interconnecting each of the corresponding pads passes. . 2. Connecting pads corresponding to the container housing the semiconductor element and the wiring base on which the container is mounted are provided, respectively, and the corresponding pads are interconnected by solder to join the container to the wiring base. In this case, a connection insulating plate having through holes at positions corresponding to each interconnection part and solder inserted into the through holes is interposed between the container and the wiring base, and heat treatment is performed. 1. A method for manufacturing a semiconductor device, which comprises bonding the two together.
JP56135172A 1981-08-28 1981-08-28 Semiconductor device and its manufacturing method Granted JPS5835935A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56135172A JPS5835935A (en) 1981-08-28 1981-08-28 Semiconductor device and its manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56135172A JPS5835935A (en) 1981-08-28 1981-08-28 Semiconductor device and its manufacturing method

Publications (2)

Publication Number Publication Date
JPS5835935A JPS5835935A (en) 1983-03-02
JPH0258793B2 true JPH0258793B2 (en) 1990-12-10

Family

ID=15145513

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56135172A Granted JPS5835935A (en) 1981-08-28 1981-08-28 Semiconductor device and its manufacturing method

Country Status (1)

Country Link
JP (1) JPS5835935A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03132692A (en) * 1989-10-18 1991-06-06 Matsushita Electric Ind Co Ltd Method for driving liquid crystal display device and its driving circuit
JPH0450998A (en) * 1990-06-15 1992-02-19 Matsushita Electric Ind Co Ltd Liquid crystal display device and driving method and driving device thereof
US6734041B2 (en) 1999-04-16 2004-05-11 Ming-Tung Shen Semiconductor chip module and method for manufacturing the same

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60123093A (en) * 1983-12-07 1985-07-01 富士通株式会社 Method of attaching semiconductor device
JP2548691B2 (en) * 1984-02-29 1996-10-30 キヤノン株式会社 Soldering method and electric circuit device
JPS63304636A (en) * 1987-06-05 1988-12-12 Hitachi Ltd Solder carrier and manufacture thereof, and method of mounting semiconductor device using same
EP0673188B1 (en) * 1994-03-15 1998-07-01 Mayer, Heinrich Belt for providing solder depots for soldering components on a printed circuit board
JP3145331B2 (en) * 1996-04-26 2001-03-12 日本特殊陶業株式会社 Relay board, method of manufacturing the same, structure including substrate, relay board, and mounting board, connection body of substrate and relay board, and method of manufacturing connection body of relay board and mounting board
JP3116273B2 (en) * 1996-04-26 2000-12-11 日本特殊陶業株式会社 Relay board, method of manufacturing the same, structure including board, relay board, and mounting board, connection body between board and relay board
TW432650B (en) 1999-04-16 2001-05-01 Cts Comp Technology System Cor Semiconductor chip device and the manufacturing method thereof

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03132692A (en) * 1989-10-18 1991-06-06 Matsushita Electric Ind Co Ltd Method for driving liquid crystal display device and its driving circuit
JPH0450998A (en) * 1990-06-15 1992-02-19 Matsushita Electric Ind Co Ltd Liquid crystal display device and driving method and driving device thereof
US6734041B2 (en) 1999-04-16 2004-05-11 Ming-Tung Shen Semiconductor chip module and method for manufacturing the same

Also Published As

Publication number Publication date
JPS5835935A (en) 1983-03-02

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