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JPS60123093A - Method of attaching semiconductor device - Google Patents

Method of attaching semiconductor device

Info

Publication number
JPS60123093A
JPS60123093A JP23087483A JP23087483A JPS60123093A JP S60123093 A JPS60123093 A JP S60123093A JP 23087483 A JP23087483 A JP 23087483A JP 23087483 A JP23087483 A JP 23087483A JP S60123093 A JPS60123093 A JP S60123093A
Authority
JP
Japan
Prior art keywords
chip carrier
printed wiring
wiring board
chip
board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP23087483A
Other languages
Japanese (ja)
Inventor
武彦 佐藤
薫 橋本
祐司 松井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP23087483A priority Critical patent/JPS60123093A/en
Publication of JPS60123093A publication Critical patent/JPS60123093A/en
Pending legal-status Critical Current

Links

Landscapes

  • Wire Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 (a) 発明の技術分野 本発明は信頼性を高めたチップキャリアの装着方法に関
する。
DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a method for mounting a chip carrier with increased reliability.

(b) 技術の背景 電算機の高速化および大容量化を実現するためにIC,
LSIなどの半導体素子(以後略称チップ)は大型化さ
れ端子数が200〜300に及ぶものも実用化されつ\
ある。
(b) Technology background In order to realize higher speed and larger capacity computers, IC,
Semiconductor devices (hereinafter referred to as chips) such as LSIs have become larger and devices with 200 to 300 terminals are being put into practical use.
be.

従来チップはチップ装着用凹部を備えたセラミック製の
配線基板にグイボンディング々どの方法で固着された後
チップの配線端子(バッド)と配線基板のチップ装着用
四部の周辺に設けられている配線端子(パッド)とをワ
イヤボンディングなどの方法で接続して回路接続を行い
、これに耐候性と機械的信頼性をもたせるためパッケー
ジ外装を行い半導体装置として出荷されている。
Conventionally, a chip is fixed to a ceramic wiring board with a recess for chip mounting using various bonding methods, and then the wiring terminals (buds) of the chip and the wiring terminals provided around the four chip mounting parts of the wiring board are bonded. (Pads) are connected to each other by a method such as wire bonding to make a circuit connection, and in order to provide weather resistance and mechanical reliability, the semiconductor device is packaged and shipped as a semiconductor device.

本発明は最近実用化されている多端子の半導体装置をプ
リント配線基板に高い信頼度で装着する方法に関するも
のである。
The present invention relates to a method of mounting a multi-terminal semiconductor device on a printed wiring board with high reliability, which has been put into practical use recently.

(c)従来技術と問題点 プリント配線されたセラミックなどの基板にチップを装
着した半導体装置はチップキャリアと云われているが、
このチップキャリアの端子構造としてはビンを用いるも
のとバンプを用いるものとがある。
(c) Conventional technology and problems A semiconductor device in which a chip is mounted on a ceramic substrate with printed wiring is called a chip carrier.
The terminal structure of this chip carrier includes one using a bottle and one using a bump.

すなわちビンを用いるものはチップキャリアの片面から
マ) IJソックス状金属性のビンが突出した構造をと
り、このビンをプリント配線基板のスルーホールに挿入
しフローソルダリングなどの方法でハンダ付けを行うも
ので従来のチップキャリアにはこのタイプのものが多い
。然し200〜300本もの多数の端子を0.6(mw
〕程度の間隔で高密度に形成する目的に対し7てはこの
方法はスペース的に罹めて困難である。
In other words, those that use a bottle have a structure in which an IJ sock-like metal bottle protrudes from one side of the chip carrier, and this bottle is inserted into a through hole in a printed wiring board and soldered using a method such as flow soldering. Many conventional chip carriers are of this type. However, a large number of 200 to 300 terminals are
] This method is difficult due to space constraints for the purpose of forming them at a high density at intervals of about 7.

一方ピンに代ってマトリックス状に接続用ノくンプを形
成し、これを直接にプリント配線基板に接Mf;bフェ
イスダウンポンディング法がある。
On the other hand, there is a face-down bonding method in which connecting bumps are formed in a matrix shape instead of pins and are directly connected to a printed wiring board.

この方法は高密度端子の形成には適しているがチップキ
ャリアとして通常用いられているアルミナ基板の熱膨張
系数とエポキシ、ポリイミドなどの合成樹脂からなるプ
リント配線基板の熱膨張系数とは大幅に異るため接続後
に熱サイクル試験を行うと熱ストレスが発生し接続部分
のノ・ンダが破断すると云う問題点がある。
Although this method is suitable for forming high-density terminals, the thermal expansion coefficient of the alumina substrate normally used as a chip carrier is significantly different from that of a printed wiring board made of synthetic resin such as epoxy or polyimide. Therefore, if a thermal cycle test is performed after connection, there is a problem that thermal stress will occur and the solder at the connection part will break.

(d) 発明の目的 本発明は高密度で多数の接続端子をもつチップキャリア
のプリント配線基板への接続に際して膨張系数の相違に
よ抄生ずるストレスを吸収可能な装着方法を提案するこ
とを目的とする。
(d) Purpose of the Invention The purpose of the present invention is to propose a mounting method capable of absorbing stress caused by differences in expansion coefficients when connecting a chip carrier having a high density and a large number of connection terminals to a printed wiring board. do.

(e) 発明の構成 本発明の目的は基板裏面の中央四部に多数個の端子を備
えた半導体チップを装着すると共に該基板裏面の周辺に
設けた複数個のパンダを通じてプリント配線基板の導体
パターンと接続するチップキャリアと前記プリント配線
基板との間にチップキャリアのバンプ配置位置に合わせ
て金属線を上下面に突出させて埋め込んだ緩衝板を設け
、該緩衝板の突出導線を介在させてチップキャリアとプ
リント配線基板との回路接続を行うことによし達成する
ことができる。
(e) Structure of the Invention The purpose of the present invention is to mount a semiconductor chip with a large number of terminals on the four central parts of the back surface of the board, and connect it to the conductor pattern of the printed wiring board through a plurality of pandas provided around the back surface of the board. A buffer plate is provided between the chip carrier to be connected and the printed wiring board, in which metal wires are embedded and protruded from the upper and lower surfaces in accordance with the bump arrangement positions of the chip carrier, and the protruding conductive wires of the buffer plate are interposed between the chip carrier and the printed wiring board. This can be achieved by making a circuit connection with a printed wiring board.

(f) 発明の実施例 本発明は膨張系数の相違により発生するストレスを細い
リード線の弾性を利用して吸収するものである。
(f) Embodiments of the Invention The present invention utilizes the elasticity of thin lead wires to absorb stress caused by differences in expansion coefficients.

第1図は本発明に係る緩衝板の平面図(5)と側面図の
)を最も簡単な場合について示すものである。
FIG. 1 shows a plan view (5) and a side view of a buffer plate according to the invention in the simplest case.

すなわちチップキャリアと同じ寸法の合成樹脂板1に鋼
(Cu)などのように比較約款い材料で直径が0.1〜
0.2[ii〕のビン2を垂直に埋め込み成型し、その
一部が合成樹脂板1より突出するようにす6・ 逢 次にか\る合成樹脂板1はノ・ンダ溶に浸漬してビ/2
にハンダ被覆を施すことにより本発明に係る緩衝板3が
でき上る。
In other words, a synthetic resin plate 1 with the same dimensions as the chip carrier is made of a comparative material such as steel (Cu) and has a diameter of 0.1~
A bottle 2 of 0.2 [ii] is vertically embedded and molded so that a part of it protrudes from the synthetic resin plate 1. Tebi/2
By applying solder coating to the buffer plate 3 according to the present invention, the buffer plate 3 according to the present invention is completed.

第2図はか\る緩衝板3を用いてチップキャリア4をプ
リント配線基板5に装着する手順を示すものでちる。
FIG. 2 shows the procedure for mounting the chip carrier 4 on the printed wiring board 5 using the buffer plate 3.

この実施例で示すチップキャリア4においてはIC。The chip carrier 4 shown in this embodiment is an IC.

LSIなどのチップ7は基板裏面に設けられている凹部
に接着されており、ワイヤボンディングによりパンプロ
と回路接続されているプリント配線基板のパッド部に結
線されている。
A chip 7 such as an LSI is bonded to a recess provided on the back surface of the board, and connected by wire bonding to a pad part of a printed wiring board that is circuit-connected to the panpro.

さて従来はチップキャリア4のバンプ6とプリント配線
基板5の接続用パッド8とを正しく位置合わせし直接に
ノ・ンダ付けすることにより接合が行われていたが、本
発明に係る処理法においてはプリント配線基板5の上に
緩衝板3をまたこの上には半導体チップ7を装着したチ
ップキャリア4をスルーホール孔とビン2とまた導線2
とバンプ6とが正しく対向するように位置決めを行った
後側面から熱風を加えるなどの方法で加熱して接点部を
相互に融解させて一体化させる。
Conventionally, the bumps 6 of the chip carrier 4 and the connection pads 8 of the printed wiring board 5 were properly aligned and bonded by direct soldering, but in the processing method according to the present invention, A buffer plate 3 is placed on top of the printed wiring board 5, and a chip carrier 4 on which a semiconductor chip 7 is mounted is placed on the printed wiring board 5 through a through hole, a bottle 2, and a conductor 2.
After positioning is performed so that the and bumps 6 are correctly opposed to each other, heating is performed by applying hot air from the side to melt the contact portions and integrate them.

このような装着法をとる場合は緩衝板3がら突出してい
る導線2が歪を吸収するため熱サイクルを繰返しても熱
疲労による破壊は起らず信頼性の高い装着を行うことが
できる。
When such a mounting method is adopted, since the conductive wire 2 protruding from the buffer plate 3 absorbs strain, no damage due to thermal fatigue occurs even after repeated thermal cycles, and highly reliable mounting can be achieved.

実施例 面積が20 (mal角で厚さが1〔朋〕のエポキシ樹
脂板に直径が0.2.hi:lの純銅線からなるビンを
0.5[、π〕ピッチに埋め込むと共に上下に0.2(
gm)づつ突出させて成型し、これをハンダ浴に浸漬し
てビンの突出部をハンダ被覆して緩衝板を作成した0 次にこの緩衝板をチップキャリアとプリント配線基板と
の間に介在させ熱風を用いてハンダ融着したが、このよ
うにして装着したチップキャリアは安定であって熱サイ
クルを施しても断線障害の発生けない。
Example: Bottles made of pure copper wire with a diameter of 0.2.hi:l were embedded in an epoxy resin plate with an area of 20 mm square and a thickness of 1 mm at a pitch of 0.5 mm, and placed vertically. 0.2(
gm) were molded so that they protruded, and this was immersed in a solder bath to cover the protruding parts of the bottle with solder to create a buffer plate.Next, this buffer plate was interposed between the chip carrier and the printed wiring board. Although the solder was fused using hot air, the chip carrier mounted in this way is stable and does not suffer from disconnection even when subjected to thermal cycles.

(め 発明め効果 本発明は半導体装置の高速化と大容量化により実装方法
も改良され多数個のバンプをもつチップキャリアが用い
られるようになったが、この場合熱膨張系数の相違に原
因してプリント配線基板との接続不良が起り易くなった
(Mean Effect of the Invention) The present invention has improved the mounting method due to the increase in speed and capacity of semiconductor devices, and chip carriers with a large number of bumps have come to be used. Therefore, poor connection with the printed wiring board is more likely to occur.

本発明けこの不良発生を無くすることを目的としてなさ
れたもので本発明の実施により不良発生を防ぐことが可
能となる。
The present invention was made with the aim of eliminating the occurrence of defects in the cage, and by implementing the present invention, it becomes possible to prevent the occurrence of defects.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明に係る緩衝板の平面図(A)と側面図(
B)、また第2図は緩衝板の使用法を説明する側面図で
囚はチップキャリア、(B)は緩衝板、(0はプリント
配線基板である。 図において、 1は合成樹脂板、2はピン、3は緩衝板、4はチップキ
ャリア、5はプリント基板、6はバンプ、7はチップ、
8は接続用パッド。
FIG. 1 shows a plan view (A) and a side view (A) of a buffer plate according to the present invention.
B), and Figure 2 is a side view explaining how to use the buffer board, where the figure shows the chip carrier, (B) shows the buffer board, and (0 shows the printed wiring board. In the figure, 1 shows the synthetic resin board, 2 shows the buffer board. is a pin, 3 is a buffer plate, 4 is a chip carrier, 5 is a printed circuit board, 6 is a bump, 7 is a chip,
8 is a connection pad.

Claims (1)

【特許請求の範囲】[Claims] 基板裏面の中央凹部処多数個の端子を備えた半導体チッ
プを装着すると共に該基板裏面の周辺に設けた複数個の
バンプを通じてプリント配線基板の導体パターンと接続
するチップキャリアと前詰−プリント配線基板との間に
チップキャリアのバング配置位置に合わせて金属線を上
下面に突出させて埋め込んだ緩衝板を設け、該緩衝板の
実用導線を介在させてチップキャリアとプリント配線基
板との回路接続を行うことを特徴とする半導体装置の装
着方法。
A chip carrier and a front-packed printed wiring board on which a semiconductor chip with a number of terminals is mounted in a central recess on the back side of the board and connected to a conductive pattern of a printed wiring board through a plurality of bumps provided around the back side of the board. A buffer plate with embedded metal wires protruding from the upper and lower surfaces in accordance with the placement position of the chip carrier's bang is provided between the chip carrier and the circuit connection between the chip carrier and the printed wiring board by interposing the practical conducting wire of the buffer plate. A method for mounting a semiconductor device, characterized in that:
JP23087483A 1983-12-07 1983-12-07 Method of attaching semiconductor device Pending JPS60123093A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23087483A JPS60123093A (en) 1983-12-07 1983-12-07 Method of attaching semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23087483A JPS60123093A (en) 1983-12-07 1983-12-07 Method of attaching semiconductor device

Publications (1)

Publication Number Publication Date
JPS60123093A true JPS60123093A (en) 1985-07-01

Family

ID=16914657

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23087483A Pending JPS60123093A (en) 1983-12-07 1983-12-07 Method of attaching semiconductor device

Country Status (1)

Country Link
JP (1) JPS60123093A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0883818A (en) * 1994-09-12 1996-03-26 Nec Corp Electronic parts assembly body
US6033936A (en) * 1997-10-28 2000-03-07 Nec Corporation Method of mounting an LSI package
US6080936A (en) * 1996-04-26 2000-06-27 Ngk Spark Plug Co., Ltd. Connecting board with oval-shaped protrusions
US6115913A (en) * 1996-04-26 2000-09-12 Ngk Spark Plug Co., Ltd. Connecting board
CN111072450A (en) * 2019-12-27 2020-04-28 江苏广域化学有限公司 Synthesis method of allyl alcohol derivative

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5835935A (en) * 1981-08-28 1983-03-02 Fujitsu Ltd Semiconductor device and its manufacturing method
JPS6233352U (en) * 1985-08-14 1987-02-27

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5835935A (en) * 1981-08-28 1983-03-02 Fujitsu Ltd Semiconductor device and its manufacturing method
JPS6233352U (en) * 1985-08-14 1987-02-27

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0883818A (en) * 1994-09-12 1996-03-26 Nec Corp Electronic parts assembly body
US6080936A (en) * 1996-04-26 2000-06-27 Ngk Spark Plug Co., Ltd. Connecting board with oval-shaped protrusions
US6115913A (en) * 1996-04-26 2000-09-12 Ngk Spark Plug Co., Ltd. Connecting board
US6148900A (en) * 1996-04-26 2000-11-21 Ngk Spark Plug Co., Ltd. Connecting board for connection between base plate and mounting board
US6033936A (en) * 1997-10-28 2000-03-07 Nec Corporation Method of mounting an LSI package
CN111072450A (en) * 2019-12-27 2020-04-28 江苏广域化学有限公司 Synthesis method of allyl alcohol derivative
CN111072450B (en) * 2019-12-27 2022-09-02 江苏广域化学有限公司 Synthesis method of allyl alcohol derivative

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