JPH025546A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH025546A JPH025546A JP15730088A JP15730088A JPH025546A JP H025546 A JPH025546 A JP H025546A JP 15730088 A JP15730088 A JP 15730088A JP 15730088 A JP15730088 A JP 15730088A JP H025546 A JPH025546 A JP H025546A
- Authority
- JP
- Japan
- Prior art keywords
- silicon
- silicon substrate
- groove
- oxide film
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 24
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 61
- 239000010703 silicon Substances 0.000 claims abstract description 61
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 60
- 239000000758 substrate Substances 0.000 claims abstract description 38
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 20
- 238000000034 method Methods 0.000 claims abstract description 18
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 8
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 8
- 238000005498 polishing Methods 0.000 claims description 15
- 238000010438 heat treatment Methods 0.000 claims description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 7
- 229920005591 polysilicon Polymers 0.000 abstract description 7
- 150000001412 amines Chemical class 0.000 abstract description 3
- 238000005299 abrasion Methods 0.000 abstract 2
- 238000002955 isolation Methods 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 239000007788 liquid Substances 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910052594 sapphire Inorganic materials 0.000 description 2
- 239000010980 sapphire Substances 0.000 description 2
- 241001663154 Electron Species 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- -1 oxygen ions Chemical class 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
Landscapes
- Element Separation (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置の製造方法に関し、特に、誘電体分
離構造をもつ半導体装置の製造方法に関する6
〔従来の技術〕
従来、誘電体分離構造をもつ半導体装置の製造方法とし
ては、サファイア基板」二に設けられた島状シリコンを
用いて半導体素子を形成する方法(Sjlicon o
n 5apphire、SO5と略す)、シリコン基板
に酸素をイオン注入した後にシリコン層をエピタキシャ
ル成長し、このシリコン層を島状としてそこに半導体素
子を形成する方法(Ssparation byImp
lanted Oxygen、 SUMOXと略ず)な
どが知らitていたうしかしながら、SO8ではシリコ
ン層の結晶性が通常のパルグ状シリコンに比べて悪く、
rJf−やホールの移動度が低いという欠点があり、
SIMOXでは多量の酸素をイオン注入する必要があり
、基板の形状が困難であるという欠点があった。最近、
二枚のシリコン基板を用い、少なくとも一方の基板の表
面に酸化膜を形成した後、酸化膜を間に介して両板を張
り合わせる。二とにより誘電体分離構造をもつ半導体装
置が形成できることが報告されている。この技術は単結
晶シリコンを半導体素子の形成に用いることができるた
め、SO8における移動度の低下はなく、まゾ迅、張り
合わぜの工程も熱処理や電圧をかけるフ′:、シづでよ
<SIMOXにおける多址のイオン注入も必要としない
という利点をもっている。[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device, and in particular, relates to a method of manufacturing a semiconductor device having a dielectric isolation structure. [Prior Art] Conventionally, a dielectric isolation structure has been used. As a method for manufacturing a semiconductor device having a sapphire substrate, there is a method of forming a semiconductor element using island-like silicon provided on a sapphire substrate.
n 5apphire, abbreviated as SO5), a method in which oxygen ions are implanted into a silicon substrate, a silicon layer is epitaxially grown, and this silicon layer is formed into an island shape to form a semiconductor element there (Ssparation by Imp).
However, in SO8, the crystallinity of the silicon layer is worse than that of normal pulg-like silicon, and
It has the disadvantage of low mobility of rJf- and holes,
SIMOX requires a large amount of oxygen to be ion-implanted, and has the disadvantage that the shape of the substrate is difficult. recently,
Two silicon substrates are used, and after forming an oxide film on the surface of at least one of the substrates, the two boards are bonded together with the oxide film interposed therebetween. It has been reported that a semiconductor device having a dielectric isolation structure can be formed by using the above two methods. Since this technology can use single crystal silicon to form semiconductor elements, there is no decrease in mobility in SO8, and the bonding process does not require heat treatment or voltage application. It has the advantage of not requiring multiple ion implantations in SIMOX.
しかし、この張り合わせ技術におい7)は、半導体素子
を形成するためのシリコン層を薄く形成することが重要
となるが、従来報告された方法ではコン1−ロール良く
容易に薄いシリコン′fJを形成することが困碧であっ
た。例えば、研磨により薄1摸化する方法は、コストは
かからないが精度良く均一なシリコン層を得ることは困
難である。2また、エピタキシャルウェーハを用い、選
択エツチングによりシリコンを薄くして半導体素子形成
層を作成する方法も知られているが、エピタキシャルウ
ェーハのコストが高いという欠点があった。However, in this bonding technology 7), it is important to form a thin silicon layer for forming a semiconductor element, but the previously reported methods do not allow easy formation of thin silicon layers with good control. It was very difficult. For example, the method of reducing the thickness of the silicon layer by polishing is inexpensive, but it is difficult to obtain a uniform silicon layer with high precision. 2. Another known method is to use an epitaxial wafer and thin the silicon by selective etching to form a semiconductor element formation layer, but this method has the disadvantage that the cost of the epitaxial wafer is high.
本発明の目的はこれらの欠点をなくし、大幅な工程の増
加を伴わないで、均一な厚さのシリコン層を精度良く形
成できる半導体装置の製造方法を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to eliminate these drawbacks and provide a method for manufacturing a semiconductor device that can form a silicon layer of uniform thickness with high precision without significantly increasing the number of steps.
前記目的を達成するため1本発明による半導体装置の製
造方法に49いては、第一のシリコン基板の一主面に形
成された溝内を含んで表面に二酸化シリコン膜を形成す
るとともにこのシリコン基板の一主面に平坦な絶縁膜を
形成する工程と、前記第一のシリコン基板の一主面と第
二のシリコン基板とを密着し熱処理を施すことにより両
板を張り合わせる工程と、第一のシリコン基板を他の主
面から選択研磨を施して前記溝底に形成さシ]また二酸
化シリコンが露出するまで研磨する工程と、前記第一の
シリコン基板の研磨面に半導体素子を形成する工程とを
含むものである。In order to achieve the above object, a method for manufacturing a semiconductor device according to the present invention includes forming a silicon dioxide film on the surface including the groove formed on one main surface of a first silicon substrate; a step of forming a flat insulating film on one main surface; a step of bonding the first silicon substrate and the second silicon substrate by closely contacting them and performing heat treatment; selectively polishing the silicon substrate from the other main surface to form the bottom of the groove] and polishing until silicon dioxide is exposed; and forming a semiconductor element on the polished surface of the first silicon substrate. This includes:
本発明の半導体装置の製造方法において、ウェーハの研
磨にアミン系の研磨液を使用すれば、シリコンの研磨速
度に比ベシリコン酸化膜の研磨速度が100分の1.以
下と小さく、酸化膜が露出した点で研磨が停止する。そ
のためシリコン中に酸化シリコンの領域を予め形成しで
おくことによりシリコノに選択研磨した際、この酸化シ
リコンが露出した時点で研磨が停止し、酸化シリコンに
よって囲まれたシリコンは一定の厚さに形成される。In the semiconductor device manufacturing method of the present invention, if an amine-based polishing liquid is used for polishing the wafer, the polishing rate for silicon oxide film is 1/100th that of silicon. Polishing stops at the point where the oxide film is exposed. Therefore, when selectively polishing the silicon by forming a silicon oxide region in advance in the silicon, the polishing stops as soon as this silicon oxide is exposed, and the silicon surrounded by the silicon oxide is formed to a constant thickness. be done.
したがって、研磨だけで精度良くシリコンを一定の厚さ
に研磨できる。Therefore, silicon can be polished to a constant thickness with high precision just by polishing.
以下本発明による半導体装置の製造方法の一実施例を第
1図から第4図を利用して説明する。これらの図は、各
製造工程におl−するウェーハの一部分の断面を示して
いる。An embodiment of the method for manufacturing a semiconductor device according to the present invention will be described below with reference to FIGS. 1 to 4. These figures show a cross-section of a portion of the wafer that undergoes each manufacturing step.
まず、第11図に示すように第1のシリコン基板1の主
面に二酸化シリコンによる酸化膜2で表面が覆われた溝
を形成する。具体的には第1のシリコン基板1の主面に
異方性ドライエツチングにより溝を設けた後、熱酸化に
より溝の内部に酸化膜2を形成するもので、その後ポリ
シリコン3で溝を埋め込み、さらに熱酸化して表面全面
に平坦な酸化膜2を形成させる、次に、第2図に示すよ
うに、第】、のシリコン基板1と第2のシリコン基板4
とを前記表面の酸化膜2を介して化学的に結合さぜ張り
合わせる。この工程は、例えば上記の2枚のシリコン基
板を親水性処理した後、密着させ高い温度(例えば、1
000℃)で熱処理することによって行う。この方法は
シラノール接合と呼ばれ、例えば、応用物理、第56巻
第3号、373−376頁(1987)に報告されてい
る。また1間に酸化膜を介して接合することも可能であ
り、この方法は例えばアイイーイーイー、インク・・−
ナショナル エレクトロン デバイス ミーティング(
IEEE、 ■nternational Elect
ron DevieeMeetinH)のテクニカル
ダイジエスl” (Technical Diqest
)684−687頁(1985年)に報告されている。First, as shown in FIG. 11, a groove whose surface is covered with an oxide film 2 made of silicon dioxide is formed on the main surface of a first silicon substrate 1. Specifically, after a groove is formed on the main surface of a first silicon substrate 1 by anisotropic dry etching, an oxide film 2 is formed inside the groove by thermal oxidation, and then the groove is filled with polysilicon 3. The silicon substrate 1 and the second silicon substrate 4 are further thermally oxidized to form a flat oxide film 2 on the entire surface, as shown in FIG.
and are chemically bonded together via the oxide film 2 on the surface. In this step, for example, the two silicon substrates described above are subjected to hydrophilic treatment, and then brought into close contact with each other at a high temperature (for example,
This is done by heat treatment at 000°C). This method is called silanol bonding, and is reported, for example, in Oyoi Jitsu, Vol. 56, No. 3, pp. 373-376 (1987). It is also possible to bond between 1 and 1 through an oxide film, and this method can be used, for example, with ink...
National Electron Device Meeting (
IEEE, International Elect
ron DevieMeetinH) Technical
Technical Diquest
), pp. 684-687 (1985).
また、同様の技術は特公昭39−17869号公報にも
報告されている8次に、第1のシリコン基板1を裏面か
ら選択研磨により、前記溝の底に設けられた酸化膜2が
露出するまで研磨する。研磨液としてアミンを用いるこ
とにより。A similar technique is also reported in Japanese Patent Publication No. 39-17869.8 Next, the first silicon substrate 1 is selectively polished from the back surface to expose the oxide film 2 provided at the bottom of the groove. Polish until By using amine as polishing liquid.
酸化膜2が露出した時点で研磨が自動的に停止するため
、第1のシリコン基@1の研磨後の厚さは上記の溝の深
さとほぼ等しくなり、均一な厚さのシリコン層を精度良
く形成することができる。その後、第3図のように誘電
体分離されたシリコン基板1の一部であるシリコン層1
1に通常の集積回路プロセスにより第4図のようにP′
″シリコン7、n″シリコン8 nシリコン9、pシリ
コン10を形成し、グー1−酸化膜5.ゲー+=電極6
を付して半導体素子を構成することにより、誘電体分離
さ九た半導体装置が得られる。第4図はコンプリメンタ
リ−IGFET(Ins ulated Gate F
ield Effcct Tr−ansistor)が
形成された半導体装置を示し、ポリシリコンからなるグ
ー1へ電極6をちつnチャネルIGFETとpチャネル
IGFETが互いに誘電体分離されて形成されている。Since the polishing is automatically stopped when the oxide film 2 is exposed, the thickness of the first silicon base @1 after polishing is approximately equal to the depth of the groove described above, and a silicon layer with a uniform thickness can be formed with precision. Can be formed well. Thereafter, as shown in FIG.
1, as shown in FIG.
"Silicon 7, n" silicon 8, n silicon 9, p silicon 10 are formed, and a goo 1-oxide film 5. Ge+=electrode 6
By configuring a semiconductor element by attaching the following, a dielectrically isolated semiconductor device can be obtained. Figure 4 shows a complementary IGFET (Insulated Gate FET).
A semiconductor device is shown in which an n-channel IGFET and a p-channel IGFET are dielectrically separated from each other by connecting an electrode 6 to a goo 1 made of polysilicon.
以上実施例では溝内にポリシリコン3を埋め込んだ例を
示しているが、ポリシリコン3は単に充填材として使用
したのみであるため必ずしもポリシリコンの埋込みは必
要ではない。溝内全体に酸化膜を形成し、さらに第1の
シリコン基板】−の主面に酸化膜による平坦な絶縁膜を
形成しても良い。In the above embodiment, an example is shown in which polysilicon 3 is buried in the groove, but since polysilicon 3 is merely used as a filling material, burying of polysilicon is not necessarily necessary. An oxide film may be formed entirely within the trench, and a flat insulating film made of an oxide film may be further formed on the main surface of the first silicon substrate.
さらに絶縁膜の表面は平坦化処理によらず1例えば液状
のS iO,の添加によって表面平坦な絶縁膜を形成で
きる。Furthermore, the surface of the insulating film can be formed with a flat surface by adding 1, for example, liquid SiO, without using a planarization process.
以上説明したように本発明によれば誘電体で分離された
半導体基板をシリコンウェーハの張り合わせ技術を使用
し、酸化膜形成面で張り合わせて容易に製造でき6厚さ
が均一で精度良くコントロールされた誘電体分離シリコ
ン層を形成できるという効果がある。As explained above, according to the present invention, semiconductor substrates separated by a dielectric material can be easily manufactured by bonding them together on the oxide film forming surface using silicon wafer bonding technology.6 The thickness can be uniform and accurately controlled. This has the effect of forming a dielectric isolation silicon layer.
第1−図から第4図は本発明の一実施例を工程順に示し
た半導体ウニ〜ハの一部分の断面図である。
1・・・第1のシリコン基板 2・・・酸化膜3・・・
ポリシリコン 4・・・第2のシリコン基板5・・
・ゲート酸化膜 6・・・グーl−電極7・・・
P4′シリコン 8・・・n+シリコン9・・
・nシリコン 10・・・Pシリコン11・・
・シリコン層1 to 4 are cross-sectional views of a portion of a semiconductor wafer illustrating an embodiment of the present invention in the order of steps. 1... First silicon substrate 2... Oxide film 3...
Polysilicon 4... Second silicon substrate 5...
・Gate oxide film 6...Glue electrode 7...
P4' silicon 8...n+silicon 9...
・N silicon 10...P silicon 11...
・Silicon layer
Claims (1)
含んで表面に二酸化シリコン膜を形成するとともにこの
シリコン基板の一主面に平坦な絶縁膜を形成する工程と
、前記第一のシリコン基板の一主面と第二のシリコン基
板とを密着し熱処理を施すことにより両板を張り合わせ
る工程と、第一のシリコン基板を他の主面から選択研磨
を施して前記溝底に形成された二酸化シリコンが露出す
るまで研磨する工程と、前記第一のシリコン基板の研磨
面に半導体素子を形成する工程とを含むことを特徴とす
る半導体装置の製造方法。(1) A step of forming a silicon dioxide film on the surface of the first silicon substrate including the inside of the groove formed on the first silicon substrate, and forming a flat insulating film on the first main surface of the silicon substrate; A step of bonding one principal surface of the first silicon substrate and a second silicon substrate by applying heat treatment to the two substrates, and selectively polishing the first silicon substrate from the other principal surface to form the groove bottom. A method for manufacturing a semiconductor device, comprising: polishing the first silicon substrate until silicon dioxide formed on the substrate is exposed; and forming a semiconductor element on the polished surface of the first silicon substrate.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15730088A JPH025546A (en) | 1988-06-24 | 1988-06-24 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15730088A JPH025546A (en) | 1988-06-24 | 1988-06-24 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH025546A true JPH025546A (en) | 1990-01-10 |
Family
ID=15646649
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP15730088A Pending JPH025546A (en) | 1988-06-24 | 1988-06-24 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH025546A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5204282A (en) * | 1988-09-30 | 1993-04-20 | Nippon Soken, Inc. | Semiconductor circuit structure and method for making the same |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61133641A (en) * | 1984-12-03 | 1986-06-20 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
-
1988
- 1988-06-24 JP JP15730088A patent/JPH025546A/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61133641A (en) * | 1984-12-03 | 1986-06-20 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5204282A (en) * | 1988-09-30 | 1993-04-20 | Nippon Soken, Inc. | Semiconductor circuit structure and method for making the same |
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