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JPH025511A - Semiconductor device - Google Patents

Semiconductor device

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Publication number
JPH025511A
JPH025511A JP15483088A JP15483088A JPH025511A JP H025511 A JPH025511 A JP H025511A JP 15483088 A JP15483088 A JP 15483088A JP 15483088 A JP15483088 A JP 15483088A JP H025511 A JPH025511 A JP H025511A
Authority
JP
Japan
Prior art keywords
layer
group
compound semiconductor
iii
zn5e
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15483088A
Other languages
Japanese (ja)
Inventor
Naoki Kobayashi
直樹 小林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP15483088A priority Critical patent/JPH025511A/en
Publication of JPH025511A publication Critical patent/JPH025511A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To form a II-IV group/III-V group super lattice quantum well structure with especially steep interface by a method wherein a III-V compound semiconductor layer containing group III atom of Al is inserted between a III-V compound semiconductor substrate and P- or N-type II-VI compound semiconductor layers. CONSTITUTION:A P-AlAs layer 2 is formed on a P-GaAs substrate 1 and then PN junction of ZnSe is formed on the P-AlAs layer 2. In other words, e.g., the P-AlAs layer 2 (Zn doped amount, 1X10<18>cm<-3>) 1000Angstrom thick, P-ZnSe layer 3 (Li or N doped amount, 1X10<15>cm<-3>) 5000Angstrom thick and N-ZnSe layer 4 (Cl or Al doped amount, 1X10<17>cm<-3>) 5000Angstrom thick are successively formed on the P-GaAs substrate 1 (Zn doped amount, 1X10<18>cm<-3>) to form the PN junction of ZnSe.

Description

【発明の詳細な説明】 [産業上の利用分野] 本発明は半導体装置に関し、特jシニ高純度で高品質の
半導体層からなるIII −V族/II−VIl族環導
体装置関するものである。
[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor device, and particularly to a III-V group/II-VII group ring conductor device comprising a semiconductor layer of high purity and high quality. .

[従来の技術] 従来より、II −VI族化合物半導体は、III −
V族化合物半導体基板上に結晶成長し、・ていた。例え
ば、Zn5eはGaAs基板上に成長し、7nSはGa
P基板上に成長していた。この理由は1nseとGaA
sとの格子不整が小さい、ZnSとGaPとのJ’ll
子不整が小さいこと、III −V族化合物基板が転位
が小さいこと、高品質であること、Si、GeなとのI
V族基板を用いた際に発生するアンチフJ−,イズドメ
インの生成の問題がないことなどによる。
[Prior Art] Conventionally, II-VI group compound semiconductors are III-VI group compound semiconductors.
Crystals were grown on a Group V compound semiconductor substrate. For example, Zn5e is grown on a GaAs substrate, and 7nS is grown on a GaAs substrate.
It was grown on a P substrate. The reason for this is 1nse and GaA
J'll of ZnS and GaP with small lattice mismatch with s
small misalignment, small dislocations in the III-V group compound substrate, high quality, and I
This is due to the fact that there is no problem of generation of anti-J-, is-domains that occur when a group V substrate is used.

[発明が解決しようどする課題] しかしながら、GaAs基板−トのZn5e成長を例に
取って説明すると、GaAs/Zn5eヘテロ界面での
相互拡散が著しく、ZnおよびSeは400℃の成長温
度において、1時間のうちに約500人もGaAs中に
拡散する。また、GaおよびAsは400℃の成長温度
で1時間のうちに、約70人もZn5e中に拡散する(
N。
[Problems to be Solved by the Invention] However, taking Zn5e growth on a GaAs substrate as an example, interdiffusion at the GaAs/Zn5e hetero interface is significant, and Zn and Se are Approximately 500 particles diffuse into the GaAs over time. In addition, Ga and As diffuse into Zn5e by about 70% in 1 hour at a growth temperature of 400°C (
N.

にobayashi、 Jpnj、^pp1.Phys
、 、に投稿中)。このペテロ界面における相互拡散に
よフて、GaAs基板上に形成した2nSe層はアンド
ープであってもGaとAsにより自動的にドープされて
しまう。
ni obayashi, Jpnj, ^pp1. Phys.
, currently posted). Due to this mutual diffusion at the Peter interface, the 2nSe layer formed on the GaAs substrate is automatically doped with Ga and As even if it is undoped.

さらにまた、GaAs基板に拡散したInとSeにより
GaAs基板のZn5e近傍のGaAsの導電形および
抵抗率が変化する。従って、GaAsが基板上にZn5
eのPN接合を形成した場合、GaAs基板とZn5e
ヘテロ界面との相互拡散による制御不可能な変成層が形
成サレ、2nSeのPNダイオードの特性を劣化させて
いた。また7、nSe/GaAs超格子、量子井戸構造
の作製はへテロ界面の相互拡散により不可能であった。
Furthermore, the conductivity type and resistivity of GaAs near Zn5e of the GaAs substrate change due to In and Se diffused into the GaAs substrate. Therefore, GaAs has Zn5 on the substrate.
When forming a PN junction of e, GaAs substrate and Zn5e
An uncontrollable metamorphic layer formed due to interdiffusion with the hetero interface deteriorated the characteristics of the 2nSe PN diode. Furthermore, it has been impossible to fabricate an nSe/GaAs superlattice or quantum well structure due to interdiffusion at the hetero interface.

従って、本発明の目的はII−VI族/ III −V
族のへテロ構造において、原子の相互拡散を抑制し、特
性の優れたPN接合II −VIl族環導体装置特に急
峻な界面を持つII −VI族/ III −V族超格
子、量子井戸構造を提供することにある。
Therefore, the object of the present invention is to group II-VI/III-V
In group heterostructures, PN junction II-VIl group ring conductor devices with excellent characteristics suppress interdiffusion of atoms. Especially, group II-VI/group III-V superlattices and quantum well structures with steep interfaces are developed. It is about providing.

[課題を解決するための手段J かかる目的を達成するために、本発明の第1の形態は、
III −V族化合物半導体基板に、II −IV族化
合物半導体層のPN接合を形成した構造において、II
I −V族化合物半導体基板とP形またはN形II −
VL族化合物半導体層との間に、III族原子がA1で
あるIII −V族化合物半導体層が挿入されているこ
とを特徴とする。
[Means for Solving the Problems J In order to achieve such an object, the first form of the present invention is as follows:
In a structure in which a PN junction of a II-IV group compound semiconductor layer is formed on a III-V group compound semiconductor substrate,
I - V group compound semiconductor substrate and P type or N type II -
A III-V group compound semiconductor layer in which the group III atom is A1 is inserted between the VL group compound semiconductor layer and the VL group compound semiconductor layer.

本発明の第2の形態は、III −V族化合物半導体層
とTI −VI族化合物半導体層とを交互に繰り返した
構造において、III −V族化合物半導体層とII 
−VI属化合物半導体層との間に、Tlll原子が+l
であるIII −V族化合物半導体層が挿入されている
ことを特徴とする。
A second embodiment of the present invention provides a structure in which III-V group compound semiconductor layers and TI-VI group compound semiconductor layers are alternately repeated.
-Tllll atoms +l between the group VI compound semiconductor layer
A III-V compound semiconductor layer is inserted therein.

[作 用] 本発明によれば、例えばZn5e/AflAsへテロ接
合で代表されるII −VI族/A11−V族ヘテロ接
合による相互拡散は著しく少ない。この結果、Zn5e
/GaAsヘテロ界面において物性の制御不可能な変成
層は形成されず、Zn5e層へのGaおよびAsのオー
トドーピングは著しく抑制される。
[Function] According to the present invention, interdiffusion due to the II-VI group/A11-V group heterojunction represented by, for example, the Zn5e/AflAs heterojunction is significantly reduced. As a result, Zn5e
A metamorphic layer with uncontrollable physical properties is not formed at the /GaAs heterointerface, and autodoping of Ga and As into the Zn5e layer is significantly suppressed.

[実施例] 以下、図面を参照して本発明の実施例を詳細に説明する
[Example] Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

実施例1 第1図は本発明の半導体装置の一実施例を示す断面図で
ある。第1図はp−GaAs基板上にp−へ1^S層を
形成し、その上にZn5eのPN接合を形成した例を示
したものである。
Embodiment 1 FIG. 1 is a sectional view showing an embodiment of the semiconductor device of the present invention. FIG. 1 shows an example in which a p-1^S layer is formed on a p-GaAs substrate, and a Zn5e PN junction is formed thereon.

p−GaAS基板1(Znドープ量、1 x 10”c
m−’)上に厚ざ1000人のp−AfiAs層2(Z
nドープ量、1x10”cm−3)順次厚さ5000人
のp−Zn5e層3(LiあるいはNドープ量、1 x
 10”cm−3) 、および厚さ5000人のN−Z
n5e層4(ciあるいはAJZドープ量、1 x 1
0”cm−3)を形成して、Zn5eのPN接合を形成
した。
p-GaAS substrate 1 (Zn doping amount, 1 x 10”c
p-AfiAs layer 2 (Z
P-Zn5e layer 3 (Li or N doping amount, 1 x
10”cm-3), and 5000mm thick N-Z
n5e layer 4 (ci or AJZ doping amount, 1 x 1
0''cm-3) to form a Zn5e PN junction.

実施例2 第2図は本発明の半導体装置の他の実施例を示す断面図
である。
Embodiment 2 FIG. 2 is a sectional view showing another embodiment of the semiconductor device of the present invention.

第2図はN−GaAs基板上にN−AJ:tAs層を形
成し、その上にZn5eのPN接合を形成した例を示し
たものである。
FIG. 2 shows an example in which an N-AJ:tAs layer is formed on an N-GaAs substrate, and a Zn5e PN junction is formed thereon.

N−GaAs基板5(Siのドープ量、1 x 1o”
cm−3)上に厚さ1000人のN−1As層6(Se
のドープ量、1 x 10′8c「3) 、順次厚さ5
000人のN−Zn5e層7(ciあるいはA1ドープ
量、I X 10”cm−ジ、および厚さ5000人の
p−Zn5e層8(LiあるいはNドープ量、1 x 
10”cm−’)を形成して、Zn5eのPN接合を形
成した。
N-GaAs substrate 5 (Si doping amount, 1 x 1o"
cm-3) with a thickness of 1000 N-1As layer 6 (Se
doping amount, 1 x 10'8c "3), successive thickness 5
000 thick N-Zn5e layer 7 (ci or A1 doping, I
10"cm-') to form a Zn5e PN junction.

上記の各実施例において、AuAsはGaAsよりも結
合エネルギーが約1eV程度強いために、+l原子ある
いはAs原子は容易にZn5e層に拡散しないことが予
想される。実際、A11As/GaAsヘテロ界面のS
IMS分析、 AES分析により界面急峻性は分解能以
下であり、GaAs/Zn5eど比Q1ノ下へテロ界面
における構成原子の相互拡散性は著しく抑制さ1+丁い
ることがわかった。
In each of the above embodiments, since AuAs has a stronger binding energy than GaAs by about 1 eV, it is expected that +l atoms or As atoms will not easily diffuse into the Zn5e layer. In fact, the S of the A11As/GaAs hetero interface
IMS analysis and AES analysis revealed that the interface steepness was below the resolution, and that the interdiffusivity of the constituent atoms at the heterointerface was significantly suppressed by 1+ mm under the GaAs/Zn5e ratio Q1.

このことにより従来問題となっていたZn5e/GaA
sヘテロ界面の変成層は形成されず、Zn5e層へのG
aとAsのオートドーピングの問題が解決ざね、良好な
PN接合特性を示した。
This caused Zn5e/GaA, which had been a problem in the past.
A metamorphic layer at the s-hetero interface is not formed, and G to the Zn5e layer
The problem of autodoping of a and As was resolved, and good PN junction characteristics were exhibited.

実施例ユ 第3図は本発明の半導体装置のさらに別の実施例を示す
断面図である。III −V族化合物半導体GaAs層
とII−VI族化合物半導体層7nSe層との間IcA
n As層を挟んだ例を示ず。GaAs基板9上に厚さ
10人のAQAs層10層厚0100 人のGaAs層
11、厚さ10人のAf2As層12、層上2厚810
0 人のZn5e層1′3を形成したt)のである。以
下は同様の構造を繰り返lノで積層する。
Embodiment FIG. 3 is a sectional view showing still another embodiment of the semiconductor device of the present invention. IcA between the III-V group compound semiconductor GaAs layer and the II-VI group compound semiconductor layer 7nSe layer
n An example of sandwiching an As layer is not shown. A GaAs layer 11 with a thickness of 10 people, an Af2As layer 12 with a thickness of 10 people, an AQAs layer with a thickness of 10 people on the GaAs substrate 9, and a thickness of 810 nm on the top layer.
t) in which the Zn5e layer 1'3 was formed. Below, similar structures are repeatedly laminated one after another.

このような積層構造においては、従来問題となっている
Zn5e/GaAsへ″j′−ロ界面における構成原子
の相互拡散による超格子構造の破壊は観測されず、良好
な折子井戸発光が観察さシまた。
In such a laminated structure, destruction of the superlattice structure due to interdiffusion of constituent atoms at the "j'-lo interface in Zn5e/GaAs, which has been a problem in the past, was not observed, and good folding well luminescence was observed. Also.

[発明の効果] 以上説明1ノたよう6″、、本発明によれば、例えば7
、nSe/AJ2 Asヘテロ接合で代表さ才′pる+
i −vi族/Aj2−V族ヘテロ接合による相互拡散
は著しく少ない、この結果、Zn5e/GaAsヘテロ
界面において物性の制御不可能な変成層は形成されず、
Zn5e層へのGaおよびAsのオートドーピングは著
しく抑ル1さ、lする。
[Effect of the invention] According to the present invention, for example 7
, represented by the nSe/AJ2As heterojunction
Interdiffusion due to the i-vi group/Aj2-V group heterojunction is extremely small, and as a result, no metamorphic layer with uncontrollable physical properties is formed at the Zn5e/GaAs heterointerface.
Autodoping of Ga and As into the Zn5e layer is significantly suppressed.

従って、PN接合を用いた可視光発光ダイオードの特性
は向上l・、急峻な界面性を要求するZn5e/ A 
ft As層 GaAs超格子、量子井戸構造の実現が
可能どなる。
Therefore, the characteristics of visible light emitting diodes using PN junctions are improved.
ft As layer GaAs superlattice makes it possible to realize a quantum well structure.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例を示す断面図、第2図は本発
明の他の実施例を示す断面図、第3図は本発明のさらに
他の実施例を示す断面図である。 1・・・p−GaAS基板、 2・・・p−AJ2As層、 3 =jp−4nSe層、 4−−−N−ZnSe層、 5− N−GaAs基板、 6・・・N−AρAs層、 7 ・−N−1nse層。 8・・・p−1nSe層。 り  =−G aA s j、% @i 、10−−−
  AfIAs層、 11=Ga八sl’5. 12・・・ AQAs層、 13−−−ZnSe層。
FIG. 1 is a sectional view showing one embodiment of the invention, FIG. 2 is a sectional view showing another embodiment of the invention, and FIG. 3 is a sectional view showing still another embodiment of the invention. 1... p-GaAS substrate, 2... p-AJ2As layer, 3 = jp-4nSe layer, 4---N-ZnSe layer, 5- N-GaAs substrate, 6... N-AρAs layer, 7.-N-1nse layer. 8...p-1nSe layer. ri = -G aA s j, % @i, 10---
AfIAs layer, 11=Ga8sl'5. 12... AQAs layer, 13---ZnSe layer.

Claims (1)

【特許請求の範囲】 1)III−V族化合物半導体基板に、II−IV族化合物半
導体層のPN接合を形成した構造において、III−V族
化合物半導体基板とP形またはN形II−VI族化合物半導
体層との間に、III族原子がAlであるIII−V族化合物
半導体層が挿入されていることを特徴とする半導体装置
。 2)III−V族化合物半導体層とII−VI族化合物半導体
層とを交互に繰り返した構造において、III−V族化合
物半導体層とII−VI属化合物半導体層との間に、III族
原子がAlであるIII−V族化合物半導体層が挿入され
ていることを特徴とする半導体装置。
[Claims] 1) In a structure in which a PN junction of a II-IV group compound semiconductor layer is formed on a III-V group compound semiconductor substrate, a p-n junction of a III-V group compound semiconductor substrate and a P-type or N-type II-VI group 1. A semiconductor device characterized in that a III-V compound semiconductor layer whose group III atoms are Al is inserted between the compound semiconductor layer and the compound semiconductor layer. 2) In a structure in which group III-V compound semiconductor layers and group II-VI compound semiconductor layers are alternately repeated, group III atoms are present between the group III-V compound semiconductor layer and the group II-VI compound semiconductor layer. A semiconductor device characterized in that a III-V group compound semiconductor layer made of Al is inserted.
JP15483088A 1988-06-24 1988-06-24 Semiconductor device Pending JPH025511A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15483088A JPH025511A (en) 1988-06-24 1988-06-24 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15483088A JPH025511A (en) 1988-06-24 1988-06-24 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH025511A true JPH025511A (en) 1990-01-10

Family

ID=15592811

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15483088A Pending JPH025511A (en) 1988-06-24 1988-06-24 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH025511A (en)

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