JPH0254582B2 - - Google Patents

Description

[Detailed Description of the Invention] [1] Technical Field of the Invention The present invention relates to a central processing unit, a storage device, and a memory.
This paper relates to a scan data protection method in a system consisting of a control unit.

[2] Background of the technology In recent years, memory technology has been developed to determine the startup signal and timing of the activation signal from the central processing unit to the storage device, and to select processing such as system down, retry, or recovery depending on the content of the error. It is necessary to provide a check circuit in the control section to determine the activation signal and its timing, and to store the results in the scan flip-flop and hold them as scan data.

[3] Prior Art and Problems FIG. 1 is a diagram for explaining a conventional scan data protection system. In the figure, 1 is the central processing unit, 2 is the memory control unit, and 3 is the timing signal CET0~ from the activation signal *~G0 from the central processing unit and the basic timing signal MCLK.
4 is a timing generation circuit for creating CET2; 4 is a check circuit for determining the activation signals * to G0 and their timings and generating various error signals; and 5 is a scan flip-flop for holding error signals. FIG. 2 is a time chart for explaining the operation of the scan data protection method shown in FIG. This will be explained below with reference to FIGS. 1 and 2.

When the activation signal *~G0 is sent from the central processing unit 1, the check circuit 4 of the control unit 2 checks the operating state and outputs the check output (DME,
Set TME0, TME1) to the scan flip-flop. When the check output is an error leading to system down (signal DME), it is set to flip-flop FF1, and its output is sent to central processing unit 1 as signal *DMG,
It also becomes a control signal for each gate that creates clocks *SC0 to *SC2 that set data in the scan flip-flop. Therefore, when an error is detected, the signal *DMG becomes "L", the generation of the clocks *SC0 to *SC2 is stopped, and each piece of information regarding the error is held in the scan flip-flop 5.

However, in this type of system, the scan clock is controlled only by the signal *DMG, so
Since the scan clock is stopped when the first error occurs, there is a drawback that it is impossible to tell whether the error is an intermittent failure or a fixed failure.

[4] Purpose of the Invention In view of the above-mentioned drawbacks of the conventional art, it is an object of the present invention to provide a scan data protection system that can determine whether an error is an intermittent failure or a fixed failure.

[5] Structure of the Invention According to the present invention, in a system comprising a central processing unit, a storage device, and a memory control unit, the memory control unit is provided with information on the operating state of each circuit of the system in response to a start signal. A two-stage continuously connected scan flip-flop is provided, and when an abnormality occurs, the third and subsequent activation signals are stopped except for the memory refresh activation signal, and the operating state is stored in the scan flip-flop during the refresh cycle. This is achieved by providing a scan data protection method characterized by stopping the generation of a clock signal for causing a scan flip-flop to protect the data of the scan flip-flop.

[6] Embodiments of the invention Hereinafter, embodiments of the invention will be described with reference to the drawings.

FIG. 3 is a diagram for explaining the scan data protection method of the present invention, FIGS. 4 and 5 are time charts for explaining its operation, and FIG. 6 is a diagram for explaining the scan data protection method of the present invention. FIG. 3 is a diagram for explaining control of the activation signal in the FIG.

In Figure 3, the scan clock is generated by the inverted signal DMG of the signal *DMG and the refresh signal DMG.
It is stopped on a NAND condition with the signal RFCY indicating the cycle. Further, the scan flip-flop circuit 5 has two stages of flip-flops connected in succession and can store errors caused by two activation signals.

When an error occurs, the signal DMG becomes “H” and the operating status of the cycle in which the error occurred (DME, TME
0, TME1) scan clock *SC0~
Flip-flops A, C, and E are set by SC2, and the operating state of the next activation signal is checked. If the activation signal is other than the refresh cycle, flip-flops A, C, and E are set. At this time, the operating state of the cycle in which the previous error occurred has been shifted to flip-flops B, D, and F.

For example, referring to the time chart in Fig. 4, the check circuit 4 detects an error at the first start signal *WTG0, and the signal DME becomes "H".
Set flip-flop A and its output signal
SCOUTOA becomes “H”. Next activation signal *
If there is no error in RDG0, the signal DME is “L”
(dotted line in Figure 4) is set in flip-flop A, and its output signal SCOUTOA is "L".
become. The operating state of the previous cycle is then shifted to flip-flop B, and the operating state of flip-flop B
The output signal SCOUTOB becomes "H", indicating that the error is an intermittent failure. Signal in reverse
If DMF becomes “H” and is left alone, the signal
Both SCOUTOA and SCOUTOB become "H", indicating that there is a fixed failure.

Furthermore, as shown in FIG. 5, if the activation signal *RFG0 next to the cycle in which the error occurred is a refresh cycle, RFCY becomes "H" and the scan flip-flop circuit 5 clocks *SC0 to *SC2 By stopping the cycle, the operating state of the previously erroneous cycle can be protected.

A signal from the memory control unit 2 that notifies the central processing unit 1 of an error that could lead to a system down *DMG controls the activation signal in the central processing unit, but as shown in FIG. When signal *DMG is received, the second activation signal is sent, but subsequent activation signals are not sent. However, since the refresh cycle is not controlled by the signal *DMG, the scan clock in the memory control section is stopped during the refresh cycle.

[7] Effects of the invention As explained above in detail, according to the scan data protection method of the present invention, it is possible to determine whether an error is an intermittent failure or a fixed failure.
Furthermore, error information is not erased by refreshing the memory.

[Brief explanation of the drawing]

FIG. 1 is a diagram for explaining the conventional scan data protection method, FIG. 2 is a time chart thereof, FIG. 3 is a diagram for explaining the scan data protection method according to the present invention, and FIGS. FIG. 5 is a time chart thereof, and FIG. 6 is a diagram for explaining control of the activation signal by the central processing unit. DESCRIPTION OF SYMBOLS 1...Central processing unit, 2...Memory control section, 3...Timing generation circuit, 4...Check circuit, 5...Scan flip-flop circuit.

Claims (1)

[Claims] 1. In a system consisting of a central processing unit, a storage device, and a memory control section, the memory control section is provided with a two-stage continuous scan flip-flop that stores the operating status of each circuit in the system in response to a start signal, and is configured to detect abnormalities. If this occurs, the third and subsequent activation signals other than the memory refresh activation signal are stopped, and during the refresh cycle, the generation of the clock signal for storing the operating state in the scan flip-flop is stopped, thereby protecting the data of the scan flip-flop. A scanning data protection method characterized by performing the following.