JPH0253139A - Register file controller - Google Patents

Abstract

PURPOSE:To reduce the microprogram quantity by realizing a virtual 3-port register file and designating three types of registers stored in a register file with a single microinstruction. CONSTITUTION:The designated register numbers stored in the register files 2 and 3 are set in a C-E field of a microinstruction code 9. When an address '011' of a microinstruction shown in a diagram is carried out, the contents of the fields C, D and E show 0, 1 and 2 respectively. The data on a field C of the code 9 are led to the A ports of both files 2 and 3. Then the data DA1 and a DA2 on a register #0 designated by the field C are read out of the files 2 and 3. The data DA1 and the data DA2 read out of the register #0 are inputted to a data selector 7. Then either one of both data DA1 and DA2 is selected according to a level signal CLVL (0 or 1).

Description

[Detailed Description of the Invention] [Objective of the Invention] (Industrial Field of Application) The present invention realizes a virtual 3-port register file in a computer using a microprogram control method, and writes data in the register file with one microinstruction. The present invention relates to a register file control device that can specify three types of registers.

(Prior Art) Conventionally, in a microprogram-controlled arithmetic logic circuit (hereinafter referred to as ALU), data in corresponding registers is calculated from a register file using two register numbers set in a microinstruction code. Control is performed such that each data is read out as a target, each data is operated on by the ALU, and the resulting data is stored in the register file again.

Figure 4 shows the register file and ALU in the conventional configuration.
FIG. 2 is a block diagram showing the circuit configuration of the main unit and its peripheral circuitry.

Here, among the register numbers set in the C field and D field of the microinstruction code 43, the register number of the C field is input to the A port of the register file 42, and the register number of the D field is also input to the register file 42. is input to the B port of The register file 42 reads data DA of the register indicated by the A port and data DB of the register indicated by the B port, and outputs them to the ALU 41. The ALU 41 performs arithmetic processing on each of the above data (D^, DB) and outputs the resulting data to the register file 42. The register file 42 stores this data in the register indicated by the B port.

Therefore, when storing the operation results of two types of registers in other registers, this can be achieved by temporarily storing the operation results in the register indicated by the B port, and then transferring them to the target register.

(Problem to be Solved by the Invention) In this way, in a two-port register file, one port (Port B in the example in Figure 4) has both read and write functions, so one The contents of the register will always be rewritten with the data of the operation result. Therefore, conventionally, when storing the operation result of a 2F class register to another register, the source data was saved to another register and then the operation was executed in order to avoid the problems caused by data rewriting described above. . For this reason, conventionally, when storing the operation results of two types of registers to other registers, separate microinstruction processing was required to save the source data to the other registers, which caused problems in terms of microprogram size, processing speed, etc. Ta.

The present invention was made in view of the above-mentioned circumstances, and it realizes a virtual 3-port register file in a computer using a microprogram control system, and allows specifying three types of registers in the register file with one microinstruction. The present invention provides a register file control device that can perform operations on similar registers and store the operation results in other registers in one step of microprogram processing, thereby reducing the amount of microprograms and improving processing speed. I can figure it out.

[Structure of the Invention] (Means and Effects for Solving the Problems) The present invention provides two sets of register files with two ports, and specifies the storage destination register number of the operation result set in the register field of the microinstruction code. An address selector that selects two types of register numbers depending on the level, including a specific field to be stored, and an address selector that selects the register number of the register field selected by this address selector and the register number set in the other register field of the microinstruction code to the above register file. level control means for selectively supplying data to each port of the above; a data selector that selects data read from the register file for each port and supplies the data to the ALU as calculation data; It has a means for writing to the register specified by the above-mentioned specific field of the register file, and it is regarded as one register file with three ports on the microprogram, and three ports in the register file can be written with one microinstruction.
It is possible to specify the seed register, which allows 2
Operations on different types of registers and operations for storing the operation results in other registers can be executed in one step of microprogram processing, thereby simplifying the microprogram and speeding up the processing.

(Example) An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a register file control device according to an embodiment of the present invention.

In FIG. 1, reference numeral 1 denotes an ALU (arithmetic logic circuit) which receives data to be operated on outputted from the data selector 7.8 and executes arithmetic and logic operations on the same data.

2 and 3 are two-port register files, respectively. Of these, the register file 2 sends the contents of the register indicated by the A1 port to the selector 7 as data DAI.
The contents of the register indicated by the port are output to the selector 8 as data DBI. Further, the level signal DLVI from the level control unit 6 enables write, and the output data of ALUI (data of the calculation result) is written. Here, the level of this register file 2 is set to “0” (
LVLO). In addition, the register file 3 sends the contents of the register indicated by the A2 port as data DA2 to the selector 7, and sends the contents of the register indicated by the B2 port to the data DB.
2 and output to the selector 8, respectively. Furthermore, the level signal ELVL from the level control unit 6 enables write, and the output data of ALUI is written. Here, the level of this register file 3 is '1' (LVLI
).

4 and 5 are address selectors for selecting register designation addresses of the register files 2 and 3. Among these, the address selector 4 selects the D field or the E field of the microinstruction code 9 according to the level signal DLVL from the level control section 6 and sends it to the 81 port of the register file 2. Further, the address selector 5 selects the D field or the E field of the microinstruction code 9 according to the level signal ELVL from the level control section B, and sends it to the 82 port of the register file 3.

6 is the level of each register in register file 2.3 (
It is a level control unit 6 that maintains a value of “0”/“1°), and the level of the register indicated by the C field of the microinstruction code 9 is set as DLVL, and the level of the register indicated by the D field is set as DLVL, and is sent to each functional unit, respectively. In addition, when a register is rewritten, the level of that register (E) (the register indicated by the - field) is set to ELV.
Rewrite to L (logical negation of DI and VL). That is, the level control section 6 has a 1-bit level holding section corresponding to each register of the register files 2 and 3, and the level of the level holding section corresponding to the register indicated by the E field of the level holding section ('O@/“1”) to ELVL (
Rewrite it to (logical negation of DLVL).

7 is a level signal CLVL (“0”) from the level control unit 6.
/“1#), output data DA1 specified by port A1 of register file 2, or register file 3
Select the output data DA2 specified by the A2 port of
This is a data selector that is sent to ALUI as data to be calculated, and selects data DAI when CLVL-“0#” and selects data DA2 when CLVL-“1”.

8 is a level signal DLVL (“0”) from the level control unit 6.
/ According to “11), output data DBI specified by port 81 of register file 2 or register file 3
Select output data DB2 by specifying 82 ports of
This is a data selector that is sent to ALUI as data to be calculated, and selects data DBI when DLVL-“0”, and selects data D day 2 when DLVL-“1#”.

9 is a microinstruction code, and in this embodiment, the C field is the source register designated for A port, the D field is the source register designated for B port, and the E field is designated as B port.
Define this area as an area for port-specified write registers.

FIG. 2 is a flowchart showing the processing steps of a microprogram for explaining the operation of the above embodiment.

In the figure, Sl is the processing step of the microprogram at address ro11J. Here, the contents of register #O (RO) and register #1 (R1) are added and the result is stored in register #2 (R2). (RO+R1→R2)
.

Figure 3 shows each register (ROlRl,
The level of R2) is shown using addresses r011J and ro12J of the microprogram as an example, and the "011" column shows the level of each register (RO, R1°R2,...) at the time of execution of address r011J in the above flowchart. "012"
The columns indicate the levels of each of the above registers at the time of execution at address ro 12J in the above flowchart.

Here, the operation of one embodiment will be explained with reference to the above-mentioned FIGS. 1 to 3.

The designated register number in the register file 2.3 is set in the C-C field of the microinstruction code 9. Address ro11J of the microprogram shown in FIG. Data rOJ for specifying register #0 (RO),
The D field contains data “1” to specify register #1 (R1), and the C field contains data “1” to specify register #2 (R
Data "2" for specifying 2) is set respectively.

The C field data of the above microinstruction code 9 is:
Register file 2.3 A port (AI port, A2
The data of register #0 specified by the C field is transferred from each register file 2 and 3 to
I, DA2) is read out. This register file 2
The data (DAI) read from register #0 of register file 3 and the data (DA2) read from register #0 of register file 3 are both input to data selector 7,
One of the data (DAI/DA2) is selected according to the level signal CLVL (“0”/“1”).

Further, the data in the D field and the data in the C field of the microinstruction code 9 are respectively sent to the address selector 4.
．． 5 and is supplied to the level control section 6.

The level control unit 6 sends the level signal DLVL of the register #i (R1) according to the data of the D field to the address selector 4, and outputs the level signal DLVL of the logical negation of the register #i (R1).
is sent to the address selector 5.

Here, address "011" (step SL) shown in FIG.
), the level signal DLVL is "1" because the level of register #1 (R1) is "1".
, the level signal ELVL is "0#", so that the address selector 4 selects the C field and the address selector 5 selects the D field.

The data of the C field selected by the address selector 4 is supplied to the 81 port of the register file 2, and the data of the D field selected by the address selector 5 is supplied to the B2 port of the register file 3.

Register file 2 outputs the contents of register #2 (R2) as data DBI from the C field data supplied to the B1 port, and register file 3 outputs the contents of register #2 (R2) as data DBI.
The contents of register #1 (R1) are output as data DB2 from the D field data supplied to port 2.

Each of the data (DBI, DB2) is supplied to the data selector 8.

Further, the level control unit 6 sends the level signal CLVL of register #0 (RO) according to the data of the C field to the data selector 7, and sends the level signal DLVL of the register #1 (R1) according to the data of the D field to the data selector 8. Send to.

Here, when executing the process at address ro 11J (step SL) shown in FIG. 2, the level of register #0 (RO) is "0" and the level of register #1 (R1) is "1" as described above. Therefore, the data selector 7 selects the data DAI output from the register file 2, and the data selector 8 selects the data DB2 output from the register file 3, and sends them to the ALUI.

That is, here, the data of register #0 (RO) specified by the C field of microinstruction code 9 and the data of register #1 (R1) specified by the D field are each supplied to ALUI as operation target data. .

ALUI is data DAI output from register file 2 and data D output from register file 3.
B2 is loaded, the data is subjected to arithmetic processing, and the data resulting from the arithmetic operation is sent to each data input terminal of register file 2 and register file 3.

At this time, the write enable of the register file 2 is controlled by the level signal DLVL, and the write enable of the register file 3 is controlled by the level signal ELVL. Here, as mentioned above, the level signal ELVI is "0"
Since the level signal DLVL is "11", writing to register file 3 is prohibited, and register file 2
The data of the operation result output from the ALUI is written to the register #2 (R2) specified by the E field in the register file 2.

On the other hand, the level control unit 6 writes the level signal ELVL ('o' in this case) as the level value of the register #2 indicated by the E field.

That is, if the register in which the output data of ALUI is written is on the register file 2 side, '0' is held as the level of that register in the 1-bit level storage area corresponding to the above register of the level control unit 6, and the register is File 3
If it is on the side, "1" is held as the level of that register in the same way as above.

In this embodiment, r01 in the flowchart shown in FIG.
At the start of processing at address 1J, the level of register #2 (R2) was “1” as shown in Figure 3, but it became “01”.
After execution of the process at address 1, register #2 on the register file 2 side has been rewritten, so the level of register #2 (R2) becomes "0" at address ro12J.

In this way, two sets of two-port register files are provided, registers are selected and controlled by level control, and in the microprogram, it is regarded as one register file with three ports, and one microinstruction can be used to control the register file contents. 3
By adopting a configuration in which the type of register can be specified, operations on two types of registers and storing the operation results in other registers can be performed in one step of microprogram processing, simplifying the microprogram and processing. It can be made faster.

[Effects of the Invention] As detailed above, according to the register file control device of the present invention, a pair of register files each having a two-port configuration for storing source data to be calculated and data of a calculation result, and A circuit that supplies the register number specified by the specific field of the microinstruction code to each port of the register file, and two fields other than the specific field of the microinstruction code to the other port of the pair of register files. a selector that supplies a register number specified in a field selected for each register file as a selection target; a data selector that selects read data corresponding to one port of each of the pair of register files; A data selector that selects the read data corresponding to each other port of the register file, and the data selected by each data selector is given as an operation target, and the data of the operation result is sent to the above pair of register files. It is equipped with an arithmetic logic operation circuit and a control circuit that selects and controls each of the selectors mentioned above and controls writing to the register file, and on a microprogram, it is regarded as one register file with three ports, and one microinstruction can write the register file. By having a configuration in which three types of registers can be specified, operations on two types of registers and storing the operation results in other registers can be performed in one step of microprogram processing, simplifying microprograms. can speed up processing.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a register file control device according to an embodiment of the present invention, FIG. 2 is a flowchart showing the processing steps of a microprogram to explain the operation of the above embodiment, and FIG. A diagram showing the levels of each register (ROlRl, R2) in FIG. 2 using addresses r011J and ro12J of a microprogram as an example, and FIG. 4 is a block diagram showing the configuration of a conventional register file control device. ■...ALU (arithmetic logic circuit), 2.3...
・Register file (2 port configuration), 4.5...
Address selector, B...level control section, 7.8...
・Data selector, 9...Micro instruction code. Applicant's Representative Patent Attorney Takehiko Suzue

Claims (1)

[Claims] A pair of register files, each of which has a two-port configuration, stores the source data to be operated on and the data of the operation result, and a register number specified in a specific field of the microinstruction code is assigned to each port of this pair of register files. a circuit for supplying the register, and a selector for supplying, to the other port of the pair of register files, the register number specified in the field selected for each of the register files, with two fields other than the specific field of the microinstruction code as selection targets; , a data selector that selects read data corresponding to one port of the pair of register files, and a data selector that selects read data corresponding to the other port of the pair of register files; an arithmetic and logic operation circuit that receives data selected by each data selector as an operation target and sends the resultant data to the pair of register files; and a control circuit that selects and controls each of the selectors and controls writing to the register file. A register file control device comprising: