JPH0250624B2 - - Google Patents
Info
- Publication number
- JPH0250624B2 JPH0250624B2 JP14371582A JP14371582A JPH0250624B2 JP H0250624 B2 JPH0250624 B2 JP H0250624B2 JP 14371582 A JP14371582 A JP 14371582A JP 14371582 A JP14371582 A JP 14371582A JP H0250624 B2 JPH0250624 B2 JP H0250624B2
- Authority
- JP
- Japan
- Prior art keywords
- bed
- resin
- plate
- inner leads
- hole
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3135—Double encapsulation or coating and encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49558—Insulating layers on lead frames, e.g. bridging members
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
この発明は組立工程の短縮化を計ることができ
る半導体装置の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method of manufacturing a semiconductor device that can shorten the assembly process.
一般に半導体装置の組立て方法には大別して次
の２種類の方法がある。まず、第１の方法として
はセラミツクパツケージを使用する方法があげら
れる。この方法においては、半導体ペレツトをセ
ラミツクパツケージのベツド部に固定してから
AuまたはAl線によりボンデイングを行なつた後
金属キヤツプをウエルドリングに溶接あるいはろ
う接等により取り付けて半導体ペレツトを封入し
ている。次に、第２の方法としてはプラスチツク
パツケージを使用する方法があげられる。この方
法においては半導体ペレツトをベツドに固定して
からAuまたはAl線等でボンデイングを行なう。
次にモールド樹脂封止をした後外部リードに外装
メツキをほどこしている。
In general, there are two types of methods for assembling semiconductor devices: The first method is to use a ceramic package. In this method, the semiconductor pellet is fixed to the bed of the ceramic package and then
After bonding with Au or Al wire, a metal cap is attached to the weld ring by welding or brazing, and the semiconductor pellet is encapsulated. The second method is to use a plastic package. In this method, a semiconductor pellet is fixed on a bed and then bonded with Au or Al wire.
Next, after sealing with mold resin, exterior plating is applied to the external leads.
〔背景技術の問題点〕
上記した第１の方法においては、製造工程が容
易であり工程期間が短縮されるがセラミツクパツ
ケージの単価が半導体素子に比べて高いという欠
点があつた。さらに、セラミツクパツケージが単
体として扱われる為、半導体装置の組立の自動化
が困難であるという欠点があつた。また上記した
第２の方法によると半導体装置の組立工程の自動
化が容易で、プラスチツクパツケージの単価は安
価であるが、製造工程が長く、短期間での製品納
入が困難であるという欠点があつた。[Problems with the Background Art] The first method described above has the disadvantage that the manufacturing process is easy and the process period is shortened, but the unit cost of the ceramic package is higher than that of the semiconductor element. Furthermore, since the ceramic package is treated as a single unit, it is difficult to automate the assembly of semiconductor devices. In addition, according to the second method described above, it is easy to automate the assembly process of semiconductor devices and the unit price of the plastic package is low, but it has the disadvantage that the manufacturing process is long and it is difficult to deliver the product in a short period of time. .
この発明は上記の点に鑑みてなされたもので、
その目的は半導体装置の組立て能率の向上及び価
格低減を計りうる半導体装置の製造方法を提供す
ることにある。
This invention was made in view of the above points,
The purpose is to provide a method of manufacturing a semiconductor device that can improve the efficiency of assembling the semiconductor device and reduce the cost.
リードフレームのベツド部及びインナーリード
を耐熱性ゴム平板で覆つた後、上記耐熱性部材の
周囲を樹脂封止し、上記耐熱性ゴム平板を除去し
て上記ベツド部及びインナーリードを露出させる
開口部を設けるようにしている。
After the bed portion and inner leads of the lead frame are covered with a heat-resistant rubber flat plate, the periphery of the heat-resistant member is sealed with resin, and the heat-resistant rubber flat plate is removed to expose the bed portion and inner leads. I am trying to set it up.
以下、図面を参照してこの発明の一実施例を説
明する。第１図は同実施例を示す半導体装置の製
造方法を示す図である。まず、同図Ａに示すよう
にリードフレーム１１のベツド部（図示せず）及
びインナーリード（図示せず）を耐熱性ゴム平板
１２（例えばSi系ゴム平板）で覆う。次に、上記
耐熱性ゴム平板１２の周囲を樹脂１４でモールド
し、上記耐熱性ゴム平板１２を加熱又は機械的手
段により除去して第１図Ｂに示すような形状とす
る。つまり、同図Ｂにおいて、１５は上記耐熱性
ゴム平板１２の除去によつて得られた開口部であ
り、この開口部１５内にはベツド部１６及びイン
ナーリード１７が露出されている。次に、同図Ｃ
に示すように、上記ベツド部１６にペレツトを１
８をマウントしてワイヤボンデイングを行なう。
さらに、上記開口部１５に溶液状、固形又は粉末
状のモールド樹脂１９に入れて加熱して重合し同
図Ｄに示すように樹脂封止している。その後、単
体に切り離して製品としている。
Hereinafter, one embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a diagram showing a method of manufacturing a semiconductor device according to the same embodiment. First, as shown in FIG. 1A, the bed portion (not shown) and inner leads (not shown) of the lead frame 11 are covered with a heat-resistant rubber flat plate 12 (for example, a Si-based rubber flat plate). Next, the periphery of the heat-resistant rubber flat plate 12 is molded with resin 14, and the heat-resistant rubber flat plate 12 is removed by heating or mechanical means to form the shape shown in FIG. 1B. That is, in FIG. B, reference numeral 15 is an opening obtained by removing the heat-resistant rubber flat plate 12, and inside this opening 15, a bed portion 16 and an inner lead 17 are exposed. Next, C
As shown in the figure, one pellet is placed in the bed portion 16.
8 and perform wire bonding.
Furthermore, a molding resin 19 in the form of a solution, solid, or powder is placed in the opening 15 and heated to polymerize, thereby sealing with the resin as shown in FIG. After that, it is separated into individual products.
なお、上記実施例においてはリードフレーム１
１上に第１図Ｂに示すような半導体装置を複数個
作成しているが、第２図に示すように単体に切り
離して以下のペレツトマウント工程を行なうよう
にしても良いことは勿論である。 In addition, in the above embodiment, the lead frame 1
Although a plurality of semiconductor devices as shown in FIG. 1B are fabricated on 1, it is of course possible to separate them into individual devices and perform the following pellet mounting process as shown in FIG. be.
以上詳述したようにこの発明によれば、セラミ
ツクパツケージより低価格で半導体装置の組立て
能率を向上させることができる。さらに、リード
フレームのままでアセンブリ工程を行なうことが
できるので量産にも有利である。
As described in detail above, according to the present invention, it is possible to improve the assembly efficiency of semiconductor devices at a lower cost than that of ceramic packages. Furthermore, since the assembly process can be performed with the lead frame intact, it is advantageous for mass production.
第１図Ａ〜Ｄはこの発明の一実施例における半
導体装置の製造方法を示す図、第２図は応用例を
示す図である。
１１……リードフレーム、１２……耐熱性ゴム
平板、１５……開口部、１６……ベツド部。
FIGS. 1A to 1D are diagrams showing a method for manufacturing a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a diagram showing an application example. DESCRIPTION OF SYMBOLS 11...Lead frame, 12...Heat-resistant rubber flat plate, 15...Opening part, 16...Bed part.
Claims (1)
ドを耐熱性部材で覆う工程と、上記耐熱性部材の
周囲を樹脂封止する工程と、上記耐熱性部材を除
去し上記ベツド部及びインナーリードを露出させ
る開口部を設ける工程とを具備したことを特徴と
する半導体装置の製造方法。1. A step of covering the bed portion and inner leads of the lead frame with a heat-resistant member, a step of sealing the periphery of the heat-resistant member with resin, and an opening for removing the heat-resistant member and exposing the bed portion and inner leads. 1. A method of manufacturing a semiconductor device, comprising the step of providing.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14371582A JPS5933852A (en) | 1982-08-19 | 1982-08-19 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14371582A JPS5933852A (en) | 1982-08-19 | 1982-08-19 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5933852A JPS5933852A (en) | 1984-02-23 |
| JPH0250624B2 true JPH0250624B2 (en) | 1990-11-02 |
Family
ID=15345295
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14371582A Granted JPS5933852A (en) | 1982-08-19 | 1982-08-19 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5933852A (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2503029B2 (en) * | 1987-10-06 | 1996-06-05 | 沖電気工業株式会社 | Method for manufacturing thin semiconductor device |
| JP3631770B2 (en) * | 1993-01-22 | 2005-03-23 | 本田技研工業株式会社 | Intake device for internal combustion engine |
| JPH08506454A (en) * | 1993-11-29 | 1996-07-09 | ロジヤーズ・コーポレイシヨン | Electronic chip carrier package and manufacturing method thereof |
| JP3494284B2 (en) | 1999-09-03 | 2004-02-09 | 本田技研工業株式会社 | Intake port structure of 4-stroke cycle internal combustion engine |
-
1982
- 1982-08-19 JP JP14371582A patent/JPS5933852A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5933852A (en) | 1984-02-23 |
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