JPH0240746A - Memory error processing system - Google Patents

Abstract

PURPOSE:To decide a software or hardware error by driving a shaft register by using a write and a read mode signal as shift-in data and then knowing the generation state of a 1-bit error from the contents of a shift register as information. CONSTITUTION:An error address register 8 holds the address of the 1-bit error when the error occurs. Then a comparing circuit 9 compares an access address with the held contents of an error address register 8 every time a memory is accessed. In this case, if the comparison value of the circuit 9 is coincident and the 1-bit error occurs or if the comparison value of the circuit 9 is coincident and write access is attained, a read mode signal for writing is used as the shift-in data to drive the shift register 13 and the contents of the register 13 are used as information to know the generation state of the 1-bit error. Consequently, it is decided whether the 1-bit error is a software error or hardware error.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory error handling method, and particularly to a memory error handling method for one-bit errors in a storage device.

[Conventional technology-]

Semiconductor memories have rapidly progressed since the introduction of IK (kilo) dynamic memory in 1971 until today, and devices with a memory capacity of LM (mega) bits per chip are now being mass-produced. However, around 1978, it was discovered that in highly integrated dynamic memories, ionizing radiation could reverse the stored data in the memory, causing soft errors.

Soft errors occur randomly in memory elements.
Since this is a one-bit error that does not repeat and is caused by a mechanism different from a failure, it can be completely recovered by rewriting in the next cycle. It is known that this occurs because the charge of the cells and bit lines of the memory element changes due to the charge of alpha particles emitted from the radiation sources uranium and thorium contained in the memory element itself and its case. .

In a dynamic RAM with 16 bits or 64 bits, the amount of charge held by the cells and bit lines of the memory element is sufficiently large, so soft errors are rarely a problem in practice, but with 256 bits or even As the device structure becomes smaller and becomes 1M bit, soft errors caused by alpha elements become a problem.

Soft errors do not surface in storage devices with error correction circuits when only soft errors are considered, but when the soft error failure rate increases to a certain extent, they overlap with hard errors in the memory element and become uncorrectable errors, which can become a problem. Become.

In the above-mentioned technical environment, conventional memory error handling methods register the fact that a 1-bit error has occurred, the error address, etc. in a diagnostic processor, and check if a 1-bit error has occurred multiple times at the same address. If so, the relevant package will be replaced during maintenance.

[Problems to be Solved by the Invention] In the conventional memory error handling method described above, the package is replaced based solely on the fact that a 1-bit error occurs multiple times at the same address, but if only reading continues. Since soft errors appear to be fixed failures, it may be unnecessary to replace the package based on the above facts alone.Furthermore, if the replaced package is one that has caused a soft error, it may be necessary to replace the package. There is a problem that repair work is wasted.

The purpose of the present invention is to solve the problem that the address where a 1-bit error has occurred is caused by a read access occurring in succession.
A flag is set up to determine whether bit errors occur frequently, and the contents of this flag and time-series information on the occurrence of single-bit errors are used as auxiliary information for distinguishing between soft errors and hard errors, facilitating maintenance and operation. The purpose of this invention is to provide a memory processing method with improved performance.

[Means to solve the problem]

The present invention includes an error address register that holds an address when a 1-bit error occurs, a comparison circuit that compares the access address with the contents held in the error address register each time a memory is accessed, and a shift-in of write and read mode signals. As data, it has a shift register that shifts with the shift-in data when the comparison circuit matches and there is a write access.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. In FIG. 1, address register 1 of this embodiment is CPU
The memory 2 is a register that holds address information sent from the memory 2, and the memory 2 is a memory in which RAM elements are arranged. The memory read data register 3 is a register that holds data read from the memory array, and the ECC circuit 4 is a circuit for error checking the read data.

The correction circuit 5 is a circuit that corrects read data,
The read data register 6 holds the corrected data and C
This is a register for sending data to the PU.

The WR control circuit 7 reads (writes) the storage device in response to a WR control signal from the CPU.

This is a circuit that controls write (Reaφ), and the error address register 8 is a register that holds an error address when a 1-bit error occurs. Comparison circuit 9 is a comparison circuit that compares the error address when a 1-bit error occurs and the address in subsequent access. In addition, 10.12
is an AND gate, and 11 is an OR gate. The shift register 13 is a register that shifts data when a 1-bit error occurs or when the 1-bit error address matches the address at the current access. For data, write and read control signals are input.

First, address information transferred from the CPU is held in the address register 1 and sent to the memory array 2.

The memory array 2 is given not only this address information but also timing for operating the memory elements, but a detailed explanation thereof will be omitted.

Data read from the memory array 2 is held in a memory read data register 3 and checked for errors in an ECC circuit 4. If the result of the error check is that there is a 1-bit error, the data is corrected by the correction circuit 5 and held in the read data register 6, and the output of the read data register 6 is sent to the CPU.

ECC circuit 4 simultaneously generates a syndrome and a 1-bit error signal and sends them via path 102 to the diagnostic processor. On the other hand, address information when a 1-bit error occurs is sent from address register 1 to error address register 8 via bus 101, and from ECC circuit 4 to path 10.
3 is set in the error address register 8 by a 1-bit error occurrence signal sent through the address register 8. The contents of the register are held by path 104. In this embodiment, the first error is held. The contents of error address register 8 are sent via path 105 to the diagnostic processor. When considering a subsequent access in a state where a 1-bit error address is held in the error address register 8, if the accessed address is the same as the 1-bit error occurrence address that occurred earlier, the result of the comparator circuit 9 indicates a matching state, which means that the same address where a 1-bit error occurred was accessed in the bargain sale that was in a matching state. In that case, the output of the comparison circuit 9 is the output from the ECC circuit 4, and if there is a 1-bit error, the AND gate 10. The signal is input to the shift register 13 via the OR gate 11 as a shift-up signal for the shift register 13. On the other hand, in the case where a 1-bit error does not occur even if the addresses match, that is, in the write mode, the WR control circuit 7 provides the write signal to the gate circuit 12 via the path 107 together with the request signal (REQUEST). In this case as well, the signal is inputted as a shift up signal to the shift register 13 via the OR gate 11. As described above, the shift register 13 is shifted up when an address matches and there is a 1-bit error or write access. On the other hand, for shift data, a write signal from the WR control circuit 7 is input to the input of the shift register. Therefore, when writing, data 0 is input, and when reading, data 0 is input. By setting all initial values to '1', if the first 1-bit error occurs during reading, '0' will be input, and as the access progresses, '0' will be input. or'
1' is shifted in. The output of the shift register 13 is sent to the diagnostic processor and saved as error information.

The diagnostic processor registers syndromes, error addresses, and the contents of the shift register, and in particular, the contents of the shift register provide time-series data of writes and reads to the address where a 1-bit error has occurred.

In this embodiment, if 'O' is shifted in, it indicates that reading has been performed for that number of times and an error has occurred, and if '1' is shifted in, it indicates that writing was performed in the middle. Recognize. From this information, it can be determined whether the 1-bit error is caused by a hardware error or by continuous reading of a soft error.

〔Effect of the invention〕

As explained above, by providing simple registers, comparison circuits, shift registers, and gate circuits, the present invention makes it possible to obtain time-series information on 1-bit errors that occur, and to prevent soft errors and hard errors. This serves as a basis for determining the distinction. This has the effect of making it easier to determine which cards are to be replaced during subsequent maintenance operations.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention. 1...Address register, 2...Memory array, 3
...Memory read data register, 4...FCC
Circuit, 5... Correction circuit, 6... Read data register, 7... WR control circuit, 8... Error address register, 9... Comparison circuit, 10... AN
D gate, 11...OR gate, 12...AND gate, 3...shift register.

Claims (1)

[Claims] When a 1-bit error occurs, there is an error address register that holds the address at that time, a comparison circuit that compares the access address with the contents held in the error address register each time a memory is accessed, and a comparison circuit that compares the access address and the contents held in the error address register when a 1-bit error occurs. occurs, or when the comparison circuit matches and there is a write access, the read mode signal of the write is used as shift-in data to drive the shift register, and the contents of the shift register are used as information,
A memory error processing method characterized by determining whether a 1-bit error is a soft error or a hard error by knowing the occurrence status of the 1-bit error from its contents.