[go: up one dir, main page]

JPH02306776A - Commercial power supply frequency flicker elimination circuit in image pickup device - Google Patents

Commercial power supply frequency flicker elimination circuit in image pickup device

Info

Publication number
JPH02306776A
JPH02306776A JP1127279A JP12727989A JPH02306776A JP H02306776 A JPH02306776 A JP H02306776A JP 1127279 A JP1127279 A JP 1127279A JP 12727989 A JP12727989 A JP 12727989A JP H02306776 A JPH02306776 A JP H02306776A
Authority
JP
Japan
Prior art keywords
flicker
gain
field
control signal
agc
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1127279A
Other languages
Japanese (ja)
Other versions
JP2762560B2 (en
Inventor
Noriaki Kondou
近藤 紀陽
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP1127279A priority Critical patent/JP2762560B2/en
Publication of JPH02306776A publication Critical patent/JPH02306776A/en
Application granted granted Critical
Publication of JP2762560B2 publication Critical patent/JP2762560B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Landscapes

  • Picture Signal Circuits (AREA)

Abstract

PURPOSE:To attain the gain control for each field for flicker elimination correction without hindrance by applying amplitude limit to a signal of a main line system applying AGC to an image pickup output and a correction system for flicker component whose level is fluctuated at each field by means of a limiter respectively and adding the signals. CONSTITUTION:A main line system 20 detecting an average level of an image pickup output to form an AGC control signal and a flicker correction system 30 detecting a flicker component whose level is fluctuated for each field of the image pickup output based on an AGC control signal as a reference and two limiters 12, 13 limiting the level of each output of the main line system 20 and the flicker correction system 30 are provided. Then the gain of the image pickup output is controlled with a control signal being the sum of the outputs of the limiters 12, 13. When a dark image light is picked up and the gain given to a gain control amplifier is maximized, the gain correction for each field for eliminating the flicker component is attained. Thus, the forming of a gain control signal at the outside of the control range of the gain control amplifier is avoided even under the worst condition of the dark image light.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はビデオカメラ等の撮像装置における商用電源周
波数フリッカを除去する回路に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a circuit for eliminating commercial power frequency flicker in an imaging device such as a video camera.

〔発明の概要〕[Summary of the invention]

撮像出力に対してAGCをかける本線系と、フィールド
ごとにレベル変動するフリッカ成分の補正系とを加算し
てAGCのゲイン制御信号を形成する際に、夫々リミッ
タで振幅制限してから加算するようにし、AGCループ
のゲイン可変アンプの飽和を無くしたフリッカ除去回路
である。
When forming the AGC gain control signal by adding the main line system that applies AGC to the image pickup output and the flicker component correction system whose level fluctuates from field to field, the amplitude of each is limited by a limiter before addition. This is a flicker removal circuit that eliminates saturation of the variable gain amplifier in the AGC loop.

〔従来の技術〕[Conventional technology]

NTSC信号用ビデオカメラでは、垂直走査周波数が6
0Hzであるため、商用電源周波数が50Hzの地域で
は螢光灯の点滅に妨害されたフリッカが1720秒の周
期で画面に現れることがある。つまり螢光灯は交流の半
周期ごとに点滅するので60Hzと100Hzとの最大
公約数20Hzでフリッカが生じる。
For NTSC signal video cameras, the vertical scanning frequency is 6.
Since the frequency is 0 Hz, in areas where the commercial power frequency is 50 Hz, flicker caused by flickering of fluorescent lights may appear on the screen with a cycle of 1720 seconds. In other words, since the fluorescent lamp blinks every half cycle of alternating current, flicker occurs at 20 Hz, which is the greatest common divisor of 60 Hz and 100 Hz.

従来では、フリッカが3フイールド(1/20秒)の周
期で変化しているので、各フィールドに対応した3つの
AGC検波回路を並列に設け、個々の検波回路で保持さ
れている検波出力の平均と各検波出力との差分を本線の
AGC回路(3フイールドより長い時定数を持つ)のA
GC制御電圧に加算する方法が用いられている。この方
法では、3フイールドの各区間で独立のAGC制御電圧
でAGCがかかるようなゲイン制御が行われる。
Conventionally, since flicker changes at a period of 3 fields (1/20 seconds), three AGC detection circuits corresponding to each field are installed in parallel, and the average detection output held by each detection circuit is calculated. The difference between the detection output and each detection output is calculated as A of the main AGC circuit (which has a time constant longer than 3 fields).
A method of adding it to the GC control voltage is used. In this method, gain control is performed such that AGC is applied using independent AGC control voltages in each section of three fields.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

従来の構成では、本線信号のAGC回路が低入射光量時
に大ゲインで作動しているときに、フリッカ変動分に対
応する各フィールドごとのAGC補正電圧の加算が行わ
れると、AGCの制御範囲を越えてしまい、フリッカが
画面に現れる欠点があった。
In the conventional configuration, when the AGC circuit for the main signal is operating at a large gain when the amount of incident light is low, when the AGC correction voltage is added for each field corresponding to the flicker fluctuation, the AGC control range is There was a drawback that flicker appeared on the screen.

本発明はこの問題にかんがみ、螢光灯照明による比較的
暗い室内で撮像するときに、AGCが飽和することなく
、フリッカ除去補正のためのフィールドごとのゲイン制
御が支障なく行われるようにすることを目的とする。
In view of this problem, the present invention has been made to enable field-by-field gain control for flicker removal correction to be performed without any problem without AGC becoming saturated when imaging in a relatively dark room using fluorescent lighting. With the goal.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の商用電源周波数フリッカの除去回路は、撮像出
力の平均レベルを検出してAGC制御信号を形成する本
線系20と、上記AGC制御信号を基準にして撮像出力
のフィールドごとにレベル変動するフリッカ成分を検出
するフリッカ補正系30と、上記本線系20及びフリッ
カ補正系30の各出力のレベルを制限する2つのりミッ
タ12.13とを備え、各リミッタ12.13の出力を
加算した制御信号で撮像出力のゲインを制御することを
特徴とする。
The commercial power frequency flicker removal circuit of the present invention includes a main line system 20 that detects the average level of the imaging output and forms an AGC control signal, and a flicker whose level fluctuates for each field of the imaging output based on the AGC control signal. It is equipped with a flicker correction system 30 that detects the component, and two limiters 12.13 that limit the level of each output of the main line system 20 and flicker correction system 30, and a control signal that is the sum of the outputs of each limiter 12.13. It is characterized by controlling the gain of the imaging output.

〔作用〕[Effect]

NTSCビデオカメラの場合、50Hz電源の螢光灯下
で撮像すると、3フイールド(1/20秒)の周期で画
面にフリッカが生じる。このフリッカは、本線AGC系
のゲイン制御信号をフィールドごとのフリッカ成分で補
正することにより除去することができる。本線AGC系
のゲイン制御信号とフリッカ補正分とを夫々リミッタを
かけて加算することにより、暗像光の最悪条件下でもゲ
イン制御アンプの制御レンジを外れたゲイン制御信号が
形成されることがない。
In the case of an NTSC video camera, when an image is taken under a fluorescent light with a 50 Hz power supply, flickering occurs on the screen at a cycle of 3 fields (1/20 second). This flicker can be removed by correcting the gain control signal of the main AGC system with flicker components for each field. By applying a limiter to the gain control signal of the main AGC system and the flicker correction amount and adding them together, a gain control signal that is outside the control range of the gain control amplifier will not be formed even under the worst dark image light conditions. .

〔実施例〕〔Example〕

第1図は本発明によるフリッカ除去回路の要部ブロック
図を示す。入力の撮像素子出力はゲインコントロール用
の電圧制御アンプ(VCA)1を介し、A/D変換器2
でディジタル信号に変換されてから図外の処理回路へ導
出される。A/D変換器2の出力は例えば1フイ一ルド
分の画素データを加算してフィールド画面の平均レベル
を求める検波回路3に供給される。検波出力はフィール
ドごとに3フイールドのサイクルで順次切換えられるス
イッチ4で振り分けられて各フィールドに対応したメモ
リ (M1〜3)5−1.5−2.5−3に記憶される
FIG. 1 shows a block diagram of essential parts of a flicker removal circuit according to the present invention. The input image sensor output is passed through a voltage control amplifier (VCA) 1 for gain control and then to an A/D converter 2.
The signal is converted into a digital signal and then sent to a processing circuit (not shown). The output of the A/D converter 2 is supplied to a detection circuit 3 that adds pixel data for one field, for example, to obtain the average level of the field screen. The detected output is distributed by a switch 4 which is switched sequentially in a cycle of three fields for each field, and stored in memories (M1-3) 5-1.5-2.5-3 corresponding to each field.

各メモリ5−1〜5−3の内容は成るタイミングで一時
に読み出されて加算器7に供給され、また別のタイミン
グで1つずつ順次に読出され、1〜3フイ一ルド順次で
切換えられるスイッチ6に供給される。
The contents of each memory 5-1 to 5-3 are read out at the same timing and supplied to the adder 7, and are read out one by one at another timing, and are switched in the 1st to 3rd fields sequentially. The signal is supplied to the switch 6 which is connected.

加算器7の出力は3フイ一ルド分の検波レベルの平均と
考えることができる。加算出力はコンパレータ9で基準
レベルrefと比較され、比較結果の誤差出力が時定数
回路10bで十数フィールド期間にわたって平滑されて
、AGC制御信号としてリミッタ13に供給される。リ
ミッタ13は第2図に示すようにその入力レベルをMI
N−MAXの間に制限して出力する。この範囲はVCA
Iのゲインでは+6〜+24dBに相当する。
The output of the adder 7 can be considered to be the average of the detection levels of three fields. The addition output is compared with the reference level ref by the comparator 9, and the error output as a result of the comparison is smoothed over a dozen field periods by the time constant circuit 10b and supplied to the limiter 13 as an AGC control signal. The limiter 13 changes its input level to MI as shown in FIG.
Output is limited between N-MAX. This range is VCA
The gain of I corresponds to +6 to +24 dB.

リミッタ13の出力は加算器14を介してD/A変換器
15に供給され、変換アナログ電圧がAGC制御電圧と
してVCAlに供給される。以上によりAGCループが
構成される。加算器7、コンパレータ9、時定数回路1
0bが本線系20を構成する。
The output of the limiter 13 is supplied to the D/A converter 15 via the adder 14, and the converted analog voltage is supplied to VCAl as an AGC control voltage. The AGC loop is configured as described above. Adder 7, comparator 9, time constant circuit 1
0b constitutes the main line system 20.

一方、メモリ5−1〜5−3からフィールド順次に読出
された検波出力は、スイッチ6でフィールドごとに選択
され、コンパレータ8で基準refと比較される。比較
出力は時定数回路10aで例えば数フイールド区間の時
定数で平滑され、次に減算器11で、本線系20のAG
C制御信号である時定数回路10bの出力が差引かれる
。従って減算器11からはフィールド順次で3フイール
ドサイクルのフリッカ成分が抽出される。なお時定数回
路10aは実際には3フイ一ルド分に対応して3系統あ
り、各々が前回の積分値を保持し、更新値と合わせて新
たな積分を実行する。コンパレータ8、時定数回路10
a及び減算器11がフリッカ補正系30を構成する。
On the other hand, the detection outputs read out in field order from the memories 5-1 to 5-3 are selected field by field by the switch 6, and compared with the reference ref by the comparator 8. The comparison output is smoothed in a time constant circuit 10a with a time constant of several field intervals, for example, and then in a subtracter 11,
The output of the time constant circuit 10b, which is the C control signal, is subtracted. Therefore, the subtracter 11 extracts flicker components of three field cycles in field sequence. Note that there are actually three systems of time constant circuits 10a corresponding to three fields, each of which holds the previous integral value and executes a new integral together with the updated value. Comparator 8, time constant circuit 10
a and the subtracter 11 constitute a flicker correction system 30.

減算器11の出力はリミッタ12に供給される。The output of subtracter 11 is supplied to limiter 12 .

このリミッタ12は入力をVCAlのゲイン換算で±6
dBの範囲に制限する。リミッタ12の出力は加算器1
4で本線のAGC制御信号と加算され、フリフカ補正が
加味されたAGC制御信号としてD/A変換器15から
VCAIに供給される。
This limiter 12 converts the input into VCAl gain by ±6
limited to dB range. The output of limiter 12 is output from adder 1
In step 4, the signal is added to the main AGC control signal and is supplied from the D/A converter 15 to the VCAI as an AGC control signal that has been subjected to flicker correction.

第2図に示すように、VCAIのゲイン可変範囲が0〜
30dBである場合、本線系20のAGC制御信号はリ
ミッタ13で+6〜+24dB相当に制限されている。
As shown in Figure 2, the VCAI gain variable range is from 0 to
In the case of 30 dB, the AGC control signal of the main line system 20 is limited by the limiter 13 to +6 to +24 dB.

一方、フリフカ補正系30のリミッタ12の出力は±6
dBに制限されている。従って加算器14でこれらが加
え合わさったとき、最悪でも0dB(6−6)〜30d
B(24+6)の範囲内でゲイン制御が行われる。従っ
て従来のようにVCAIの制御可能な範囲を外れてゲイ
ン制御電圧が与えられることがなく、どのような状態で
も商用電源フリッカを除去するAGC動作が行われる。
On the other hand, the output of the limiter 12 of the fluffy correction system 30 is ±6
dB. Therefore, when these are added together in the adder 14, the worst case is 0 dB (6-6) to 30 dB.
Gain control is performed within the range of B(24+6). Therefore, the gain control voltage is not applied outside the controllable range of VCAI as in the prior art, and the AGC operation for removing commercial power supply flicker is performed under any conditions.

なお第1図の構成ではリミッタ13の制限範囲は固定(
±6 dB)であるが、本線系20のAGC制御電圧が
大きいときには制限範囲を更に狭め、AccI]i電圧
が小さいときには範囲を広くしてもよい。
In the configuration shown in Figure 1, the limit range of the limiter 13 is fixed (
±6 dB), but when the AGC control voltage of the main line system 20 is large, the limiting range may be further narrowed, and when the AccI]i voltage is small, the limiting range may be widened.

〔発明の効果〕〔Effect of the invention〕

本発明は上述のようにリミッタを介してAGC系のゲイ
ン制御信号及びフィールドごとのフリッカ補正信号とを
加算する構成であるから、暗像光を撮像するときにゲイ
ン制御アンプに与えるゲインが最大になっても、フリッ
カ成分除去のフィールドごとのゲイン補正を支障なく行
う余裕を持たせであるので、最悪条件下でもフリフカ除
去が可能となる。特に、比較的暗い室内で螢光灯下で撮
像してもフリッカが生じない。
As described above, the present invention is configured to add the gain control signal of the AGC system and the flicker correction signal for each field via the limiter, so that the gain given to the gain control amplifier when imaging dark image light is maximized. Even if this happens, there is enough margin to perform gain correction for each field for flicker component removal without any problem, so flicker can be removed even under the worst conditions. In particular, flicker does not occur even when an image is taken under a fluorescent light in a relatively dark room.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明を適用した撮像装置のフリッカ除去回路
のブロック図、第2図は第1図の回路におけるAGC制
御アンプの入出力特性図である。 なお図面に用いた符号において、 1・・・・−−−一−−−−−−−−−−・VCA3・
・−−一−−・・−一−−−−−−・−検波回路8.9
−一−−−・−−−−一−−−−コンパレータ12、1
3・−・・・・・・・リミッタ14・−・−・−・・−
・・・・−加算器20−−−−−−−−−−・−・一本
線系30−−−−−・・−・−一−−−−−−−フリフ
カ補正系である。
FIG. 1 is a block diagram of a flicker removal circuit of an imaging apparatus to which the present invention is applied, and FIG. 2 is an input/output characteristic diagram of an AGC control amplifier in the circuit of FIG. In addition, in the symbols used in the drawings, 1...----1------VCA3.
・−−1−−・−1−−−−−−・−Detection circuit 8.9
−1−−−・−−−−1−−−Comparator 12, 1
3・−・・・・Limiter 14・−・−・−・・−
. . . Adder 20 --- Single line system 30 --- 1 --- This is a frikk correction system.

Claims (1)

【特許請求の範囲】 撮像出力の平均レベルを検出してAGC制御信号を形成
する本線系と、 上記AGC制御信号を基準にして撮像出力のフィールド
ごとにレベル変動するフリッカ成分を検出するフリッカ
補正系と、 上記本線系及びフリッカ補正系の各出力のレベルを制限
する2つのリミッタとを備え、 各リミッタの出力を加算した制御信号で撮像出力のゲイ
ンを制御することを特徴とする撮像装置における商用電
源周波数フリッカ除去回路。
[Claims] A main line system that detects the average level of the imaging output to form an AGC control signal, and a flicker correction system that detects a flicker component whose level fluctuates for each field of the imaging output based on the AGC control signal. and two limiters that limit the level of each output of the main line system and flicker correction system, and the gain of the imaging output is controlled by a control signal obtained by adding the outputs of each limiter. Power frequency flicker removal circuit.
JP1127279A 1989-05-20 1989-05-20 Commercial power frequency flicker elimination circuit in imaging device Expired - Fee Related JP2762560B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1127279A JP2762560B2 (en) 1989-05-20 1989-05-20 Commercial power frequency flicker elimination circuit in imaging device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1127279A JP2762560B2 (en) 1989-05-20 1989-05-20 Commercial power frequency flicker elimination circuit in imaging device

Publications (2)

Publication Number Publication Date
JPH02306776A true JPH02306776A (en) 1990-12-20
JP2762560B2 JP2762560B2 (en) 1998-06-04

Family

ID=14956047

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1127279A Expired - Fee Related JP2762560B2 (en) 1989-05-20 1989-05-20 Commercial power frequency flicker elimination circuit in imaging device

Country Status (1)

Country Link
JP (1) JP2762560B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0548932A (en) * 1991-08-09 1993-02-26 Fujitsu General Ltd Flickerless electronic shutter controller
US6882363B1 (en) * 1999-01-29 2005-04-19 Matsushita Electric Industrial Co., Ltd. Video signal processing apparatus
JP2018078451A (en) * 2016-11-09 2018-05-17 キヤノン株式会社 Imaging apparatus, control method thereof, and control program

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0548932A (en) * 1991-08-09 1993-02-26 Fujitsu General Ltd Flickerless electronic shutter controller
US6882363B1 (en) * 1999-01-29 2005-04-19 Matsushita Electric Industrial Co., Ltd. Video signal processing apparatus
JP2018078451A (en) * 2016-11-09 2018-05-17 キヤノン株式会社 Imaging apparatus, control method thereof, and control program

Also Published As

Publication number Publication date
JP2762560B2 (en) 1998-06-04

Similar Documents

Publication Publication Date Title
JP2687670B2 (en) Motion detection circuit and image stabilization device
JP3375557B2 (en) Video signal processing device
JPH04271669A (en) Gradation corrector
US6657659B1 (en) Flicker compensation for cameras
JPH11220739A (en) Video camera device
JPH02306776A (en) Commercial power supply frequency flicker elimination circuit in image pickup device
JP2995887B2 (en) Flicker correction circuit
JPH02306777A (en) Commercial power supply frequency flicker elimination circuit in image pickup device
KR0134487B1 (en) Peripheral contrast correction circuitry on the camcorder screen
JP4026890B2 (en) Electronic camera and electronic shutter control method thereof
JP3413850B2 (en) Video camera
JP2798562B2 (en) Signal correction circuit
JP2998152B2 (en) Image signal processing circuit
JP3607356B2 (en) Imaging device
US4975774A (en) Art processor in a picture-in-picture system
JP3574668B2 (en) Imaging device
JPH0522653A (en) Exposure control method for imaging device
KR200150134Y1 (en) Automatic gain control system for a digital camcorder
JP3318948B2 (en) Video camera
JPH0730803A (en) Method and device for controlling exposure
JPH10257381A (en) Flicker correction device
JP3417576B2 (en) Imaging device
JPH08181886A (en) Camera system
JPH118780A (en) Image pickup device
JPH05292532A (en) Image pickup device

Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees