JPH02306777A - Commercial power supply frequency flicker elimination circuit in image pickup device - Google Patents
Commercial power supply frequency flicker elimination circuit in image pickup deviceInfo
- Publication number
- JPH02306777A JPH02306777A JP1127280A JP12728089A JPH02306777A JP H02306777 A JPH02306777 A JP H02306777A JP 1127280 A JP1127280 A JP 1127280A JP 12728089 A JP12728089 A JP 12728089A JP H02306777 A JPH02306777 A JP H02306777A
- Authority
- JP
- Japan
- Prior art keywords
- gain
- flicker
- field
- control signal
- agc
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000008030 elimination Effects 0.000 title abstract 2
- 238000003379 elimination reaction Methods 0.000 title abstract 2
- 238000003384 imaging method Methods 0.000 claims description 11
- 238000001514 detection method Methods 0.000 description 10
- 238000010586 diagram Methods 0.000 description 4
- 230000015654 memory Effects 0.000 description 3
- 238000000034 method Methods 0.000 description 2
- 239000000284 extract Substances 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
- 238000009738 saturating Methods 0.000 description 1
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- Picture Signal Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はビデオカメラ等の撮像装置における商用電源周
波数フリッカを除去する回路に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a circuit for eliminating commercial power frequency flicker in an imaging device such as a video camera.
撮像出力に対してAGCをかける本線系と、フィールド
ごとにレベル変動するフリッカ成分の補正系との夫々に
対応させて、直列の2つのゲイン可変器を制御すること
により、暗像光時にAGCループのゲイン可変器の飽和
によるフリッカを生じ無くしたフリッカ除去回路である
。By controlling two series gain variable devices corresponding to the main line system that applies AGC to the image pickup output and the correction system for flicker components whose level fluctuates from field to field, the AGC loop can be adjusted during dark image light. This is a flicker removal circuit that eliminates flicker caused by the saturation of the gain variable device.
NTSC信号用ビデオカメラでは、垂直走査周波数が6
0Hzであるため、商用電源周波数が50Hzの地域で
は螢光灯の点滅に妨害されたフリ7カが1720秒の周
期で画面に現れることがある。つまり螢光灯は交流の半
周期ごとに点滅するので60Hzと100Hzとの最大
公約数2011zでフリッカが生じる。For NTSC signal video cameras, the vertical scanning frequency is 6.
Since the frequency is 0Hz, in areas where the commercial power frequency is 50Hz, flickers interrupted by flashing fluorescent lights may appear on the screen every 1720 seconds. In other words, since the fluorescent lamp blinks every half cycle of alternating current, flicker occurs at the greatest common divisor of 60Hz and 100Hz, 2011z.
従来では、フリッカが3フイールド(1/20秒)の周
期で変化しているので、各フィールドに対応した3つの
AGC検波回路を並列に設け、個々の検波回路で保持さ
れている検波出力の平均と各検波出力との差分を本線の
AGC回路(3フイールドより長い時定数を持つ)のA
GC制御電圧に加算する方法が用いられている。この方
法では、3フイールドの各区間で独立のAGC制御電圧
でAGCがかかるようなゲイン制御が行われる。Conventionally, since flicker changes at a period of 3 fields (1/20 seconds), three AGC detection circuits corresponding to each field are installed in parallel, and the average detection output held by each detection circuit is calculated. The difference between the detection output and each detection output is calculated as A of the main AGC circuit (which has a time constant longer than 3 fields).
A method of adding it to the GC control voltage is used. In this method, gain control is performed such that AGC is applied using independent AGC control voltages in each section of three fields.
従来の構成では、本線信号のAGC回路が低入射光量時
に大ゲインで作動しているときに、フリッカ変動分に対
応する各フィールドごとのAGC補正電圧の加算が行わ
れると、AGCの制御範囲を越えてしまい、フリッカが
画面に現れる欠点があった。In the conventional configuration, when the AGC circuit for the main signal is operating at a large gain when the amount of incident light is low, when the AGC correction voltage is added for each field corresponding to the flicker fluctuation, the AGC control range is There was a drawback that flicker appeared on the screen.
本発明はこの問題にかんがみ、螢光灯照明による比較的
暗い室内で撮像するときに、AGCが飽和することなく
、フリッカ除去補正のためのフィールドごとのゲイン制
御Jが支障なく行われるようにすることを目的とする。In view of this problem, the present invention is designed to prevent AGC from saturating and to perform field-by-field gain control J for flicker removal correction without any trouble when imaging in a relatively dark room using fluorescent lighting. The purpose is to
本発明の商用電源周波数フリッカの除去回路は、撮像出
力の平均レベルを検出してAGC制御信号を形成する本
線系20と、上記A G Cill I[I信号を基準
にして撮像出力のフィールドごとにレベル変動するフリ
、力成分を検出するフリッカ補正系30と、上記本線系
の制御信号で撮像出力のゲインを制御する第1ゲイン可
変器1aと、上記第1ゲイン可変器と直列に接続されて
、上記フリッカ補正系の出力によりゲイン制御される第
2ゲイン可変器1bとを備えることを特徴とする。The commercial power frequency flicker removal circuit of the present invention includes a main line system 20 that detects the average level of the imaging output and forms an AGC control signal, and a main line system 20 that detects the average level of the imaging output and forms an AGC control signal, and A flicker correction system 30 that detects force components due to level fluctuations, a first variable gain device 1a that controls the gain of the imaging output using the control signal of the main line system, and a first variable gain device 1a that is connected in series with the first variable variable device. , and a second gain variable device 1b whose gain is controlled by the output of the flicker correction system.
NTSCビデオカメラの場合、50Hz電源の螢光灯下
で撮像すると、3フイールド(1/20秒)の周期で画
面にフリッカが生じる。このフリッカは、本線AGC系
のゲイン制御信号をフィールドごとのフリッカ成分で補
正することにより除去することができる。本線AGC系
のゲイン制御信号とフリッカ補正分とを夫々別々の直列
ゲイン可変器に与えることにより、暗像光の最悪条件下
でもゲイン制御アンプの制御レンジを外れたゲイン制御
信号が形成されることがない。In the case of an NTSC video camera, when an image is taken under a fluorescent light with a 50 Hz power supply, flickering occurs on the screen at a cycle of 3 fields (1/20 second). This flicker can be removed by correcting the gain control signal of the main AGC system with flicker components for each field. By applying the gain control signal of the main AGC system and the flicker correction component to separate series gain variable devices, a gain control signal that is outside the control range of the gain control amplifier can be formed even under the worst dark image light condition. There is no.
第1図は本発明によるフリ・7力除去回路の第1実施例
の要部ブロック図を示す。入力の描像素子出力はゲイン
可変器である電圧制御アンプ(VCA)la、1bを介
し、A/D変換器2でディジタル信号に変換されてから
図外の処理回路へ導出される。A/D変換器2の出力は
例えば1フイ一ルド分の画素データを加算してフィール
ド画面の平均レベルを求める検波回路3に供給される。FIG. 1 shows a block diagram of a main part of a first embodiment of a free/seven force removal circuit according to the present invention. The input imaging element output is converted into a digital signal by an A/D converter 2 via voltage control amplifiers (VCAs) la and 1b, which are variable gain devices, and then output to a processing circuit (not shown). The output of the A/D converter 2 is supplied to a detection circuit 3 that adds pixel data for one field, for example, to obtain the average level of the field screen.
検波出力はフィールドごとに3フイールドのサイクルで
順次切換えられるスイッチ4で振り分けられて各フィー
ルドに対応したメモリ CM1〜3)5−1.5−2.
5−3に記憶される。The detection output is distributed by a switch 4 which is sequentially switched in a cycle of 3 fields for each field, and the memory CM1 to CM3) 5-1.5-2.corresponds to each field.
5-3.
各メモリ5−1〜5−3の内容は成るタイミングで一時
に読み出されて加算器7に供給され、また別のタイミン
グで1つずつ順次に読出され、1〜3フイ一ルド順次で
切換えられるスイッチ6に供給される。The contents of each memory 5-1 to 5-3 are read out at the same timing and supplied to the adder 7, and are read out one by one at another timing, and are switched in the 1st to 3rd fields sequentially. The signal is supplied to the switch 6 that is connected.
加算器7の出力は3フイ一ルド°分の検波レベルの平均
と考えることができる。加算出力はコンパレータ9で基
準レベルrefと比較され、比較結果の誤差出力が時定
数回路tabで十数フィールド期間にわたって平滑され
て、AGC制御信号としてD/A変換器15に供給され
、変換アナログ電圧がAGC制御電圧として第1ゲイン
可変器であるVCAlaに供給される。以上によりAG
Cループが構成される。加算器7、コンパレータ9、時
定数回路10bが本線系20を構成する。The output of the adder 7 can be considered to be the average of the detection levels for three fields. The addition output is compared with the reference level ref by the comparator 9, and the error output as a result of the comparison is smoothed over a dozen field periods by the time constant circuit tab, and is supplied to the D/A converter 15 as an AGC control signal to convert the converted analog voltage. is supplied as the AGC control voltage to the first variable gain variable circuit VCAla. Due to the above, AG
A C loop is constructed. The adder 7, the comparator 9, and the time constant circuit 10b constitute a main line system 20.
一方、メモリ5−1〜5−3からフィールド順次に読出
された検波出力は、スイッチ6でフィールドごとに選択
され、コンパレータ8で基準refと比較される。比較
出力は時定数回路10aで例えば数フイールド区間の時
定数で平滑され、次に減算器11で、本線系20のAG
C制御信号である時定数回路10bの出力が差引かれる
。従って減算器11からはフィールド順次で3フイール
ドサイクルのフリ・ツカ成分が抽出される。なお時定数
回路10aは実際には3フイ一ルド分に対応して3系統
あり、各々が前回の積分値を保持し、更新値と合わせて
新たな積分を実行する。コンパレータ8、時定数回路1
0a及び減算器11がフリッカ補正系30を構成する。On the other hand, the detection outputs read out in field order from the memories 5-1 to 5-3 are selected field by field by the switch 6, and compared with the reference ref by the comparator 8. The comparison output is smoothed in a time constant circuit 10a with a time constant of several field intervals, for example, and then in a subtracter 11,
The output of the time constant circuit 10b, which is the C control signal, is subtracted. Therefore, the subtracter 11 extracts the free/twist component of three field cycles in field sequence. Note that there are actually three systems of time constant circuits 10a corresponding to three fields, each of which holds the previous integral value and executes a new integral together with the updated value. Comparator 8, time constant circuit 1
0a and the subtracter 11 constitute a flicker correction system 30.
減算器11の出力はフリッカ補正のゲイン制御信号とし
て ”第2ゲイン可変器であるVCAlbに供
給される。The output of the subtracter 11 is supplied as a gain control signal for flicker correction to VCAlb, which is a second gain variable device.
第2図に示すように、VCAlaのゲイン可変範囲は例
えば0〜30dBである。一方、フリ7カ補正系30の
制御電圧によってゲイン制御されるVCAlbは、第3
図のように±6dB以上のゲインが生じないように制限
された入力電圧−ゲイン特性を有する。従って従来のよ
うにVCAlaの制御可能な範囲を外れてゲイン制御電
圧が与えられることがなく、どのような状態でも商用電
源フリッカを除去するAGC動作が行われる。As shown in FIG. 2, the gain variable range of VCAla is, for example, 0 to 30 dB. On the other hand, VCAlb whose gain is controlled by the control voltage of the flicker correction system 30 is
As shown in the figure, the input voltage-gain characteristic is limited so that a gain of ±6 dB or more does not occur. Therefore, the gain control voltage is not applied outside the controllable range of VCAla as in the conventional case, and the AGC operation for removing commercial power supply flicker is performed under any conditions.
第4図は第2実施例を示し、第1図との相違点はフリッ
カ補正系30のVCA 1 bがA/D変換器2の後に
挿入されていることである。VCAIbはディジタル式
ゲイン可変器であり、フリッカ補正系30のゲイン制御
信号でもってフィードフォワード制御が行われ、フリッ
カが除去される。FIG. 4 shows a second embodiment, and the difference from FIG. 1 is that the VCA 1 b of the flicker correction system 30 is inserted after the A/D converter 2. VCAIb is a digital gain variable device, and feedforward control is performed using the gain control signal of the flicker correction system 30 to remove flicker.
第4図の動作は第1図と同じであり、暗像売時にVCA
laが飽和してフリッカが現れるような従来の不都合は
生じない。The operation in Figure 4 is the same as Figure 1, and when selling a dark image, VCA
The conventional problem that la is saturated and flicker appears does not occur.
本発明は上述のようにAGC系のゲイン制御信号及びフ
ィールドごとのフリッカ補正信号とにより直列のゲイン
可変器1a、1bを制御する構成であるから、暗像光を
撮像するときにゲイン可変器に与えるゲインが最大にな
っても、フリッカ成分除去のフィールドごとのゲイン補
正を支障な(行うことができ、最悪条件下でもフリッカ
除去が可能となる。特に、比較的暗い室内で螢光灯下で
撮像してもフリ・7カが生じない。As described above, the present invention is configured to control the gain variable devices 1a and 1b in series using the gain control signal of the AGC system and the flicker correction signal for each field. Even if the applied gain is maximized, it is possible to perform gain correction for each field to remove flicker components, making it possible to remove flicker even under the worst conditions.Especially in a relatively dark room under fluorescent light. Even when taking an image, there is no frizz.
第1図は本発明を適用した描像装置のフリッカ除去回路
の第1実施例のブロック図、第2図及び第3図は第1図
の回路における2つのゲイン可変器用アンプの入出力特
性図、第4図は第2実施例を示す第1図と同様なブロッ
ク図である。
なお図面に用いた符号において、
la、 lb −−−−−・−・V CA3−−−−−
−−−−−−−・−・−・−検波回路8 、9−−−−
−−−−−−・−コンパレータ12.13−−−−−−
−−−−−リミッタ14−−−−−−−−−・−一−−
−−−−加算器20・−・−・・−・・・・−・−・一
本線系30−−−−−−−−−−−−−−−−−−フリ
ッカ補正系である。FIG. 1 is a block diagram of a first embodiment of a flicker removal circuit for an imaging device to which the present invention is applied; FIGS. 2 and 3 are input/output characteristic diagrams of two gain variable amplifier amplifiers in the circuit of FIG. 1; FIG. 4 is a block diagram similar to FIG. 1 showing a second embodiment. In addition, in the codes used in the drawings, la, lb -------・--V CA3-----
−−−−−−−・−・−・−Detection circuit 8, 9−−−−
---------・-Comparator 12.13----
------Limiter 14-------------1--
-----Adder 20---------Single line system 30---------Flicker correction system.
Claims (1)
する本線系と、 上記AGC制御信号を基準にして撮像出力のフィールド
ごとにレベル変動するフリッカ成分を検出するフリッカ
補正系と、 上記本線系の制御信号で撮像出力のゲインを制御する第
1ゲイン可変器と、 上記第1ゲイン可変器と直列に接続されて、上記フリッ
カ補正系の出力によりゲイン制御される第2ゲイン可変
器とを備える撮像装置における商用電源周波数フリッカ
除去回路。[Claims] A main line system that detects the average level of the imaging output to form an AGC control signal, and a flicker correction system that detects a flicker component whose level fluctuates for each field of the imaging output based on the AGC control signal. a first gain variable device that controls the gain of the imaging output using the control signal of the main line system; and a second gain that is connected in series with the first gain variable device and whose gain is controlled by the output of the flicker correction system. A commercial power frequency flicker removal circuit in an imaging device including a variable device.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1127280A JPH02306777A (en) | 1989-05-20 | 1989-05-20 | Commercial power supply frequency flicker elimination circuit in image pickup device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1127280A JPH02306777A (en) | 1989-05-20 | 1989-05-20 | Commercial power supply frequency flicker elimination circuit in image pickup device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH02306777A true JPH02306777A (en) | 1990-12-20 |
Family
ID=14956071
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1127280A Pending JPH02306777A (en) | 1989-05-20 | 1989-05-20 | Commercial power supply frequency flicker elimination circuit in image pickup device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH02306777A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04373365A (en) * | 1991-06-24 | 1992-12-25 | Hitachi Ltd | Television camera |
WO2001076234A1 (en) * | 2000-03-30 | 2001-10-11 | Koninklijke Philips Electronics N.V. | Camera with light modulation removing means |
US6657659B1 (en) * | 1998-04-27 | 2003-12-02 | Koninklijke Philips Electronics N.V. | Flicker compensation for cameras |
US6882363B1 (en) * | 1999-01-29 | 2005-04-19 | Matsushita Electric Industrial Co., Ltd. | Video signal processing apparatus |
-
1989
- 1989-05-20 JP JP1127280A patent/JPH02306777A/en active Pending
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04373365A (en) * | 1991-06-24 | 1992-12-25 | Hitachi Ltd | Television camera |
US6657659B1 (en) * | 1998-04-27 | 2003-12-02 | Koninklijke Philips Electronics N.V. | Flicker compensation for cameras |
US6882363B1 (en) * | 1999-01-29 | 2005-04-19 | Matsushita Electric Industrial Co., Ltd. | Video signal processing apparatus |
WO2001076234A1 (en) * | 2000-03-30 | 2001-10-11 | Koninklijke Philips Electronics N.V. | Camera with light modulation removing means |
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