JPH0230524B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a key input circuit in an integrated circuit equipped with a control circuit.

Conventionally, when detecting key inputs, changes in key inputs have been detected constantly or by predetermined sampling. However, in the method of detecting key input changes constantly or by predetermined sampling, the key input circuit spends a large percentage of the time in operation, which increases power consumption. , had become an obstacle. In addition, key input requires a control circuit to provide a chatter prevention mechanism and invalidate unstable key input, but this chatter prevention control circuit requires a relatively large configuration and increases the chip area. This has been a stumbling block in integrated circuits, leading to increased costs.

In order to eliminate such drawbacks, the present invention shortens the circuit operation time related to key input, and also makes it possible to perform chatter prevention control using a general-purpose register, etc. only immediately after a change in key input, without using a dedicated input circuit. The purpose is to reduce power consumption and chip area in integrated circuits.

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the constituent elements of the present invention. The signals from the key input group such as SW1 to SW3 are detected by the selective differentiation circuit 10, and the flip-flop 20 is set with the output signal of 10.
output signal a, sampling clock generation circuit 3
0 is allowed, the key input determination circuit 40 is operated with the output signal bv of 30, and after a predetermined determination operation, 20
It outputs a signal c to reset the key input, and detects key input only during a predetermined period after the input change signified by 10. 11 out of 10 blocks are keys
SW1 positive going edge and negative going
Detect both edges, 12 is key SW2
positive going ede only, 13 is key SW3
Only negative going edges are detected, 14 is 1
The logical sum of the output signals 1, 12, and 13 is calculated. 41 of the 40 blocks is a counter circuit that generates a carry signal c after counting a predetermined sampling clock; 42 is a counter circuit that generates a carry signal c after counting a predetermined sampling clock; and 42, SW1, SW2,
43 is a D flip-flop circuit that receives the output of 42 as an input; 44 compares the outputs of 42 and 43 to find a match. The circuit to judge, the signal d, is a signal that becomes a predetermined level when they match, and e
is an AND signal of c and d.

FIG. 2 is a diagram showing an example of the timing of each part signal in the configuration of FIG. 1. When SW2 is given, the time sequence shown in Figure 2 occurs,
A coincidence signal is obtained at d, and a signal excluding the determination period is obtained at l. Here, by setting the period of sampling clock b to an appropriate value that corresponds to chattering in the key input system, key input detection with a chattering prevention function is performed, and 42 or 43 parallel signals at detection time _t1 are detected. The output can be passed to the next stage of key input identification processing as input data for the key input group.

The key input group identification process can be realized by any method such as software processing using a microcomputer.

The function of block 40 in Fig. 1 is achieved by applying the b signal to the interrupt input terminal of the microcomputer, and detecting the key inputs of SW1, SW2, and SW3 by software processing of the microcomputer. It is also possible to detect them as a group and implement them as pre-processing for the function identification process.

In addition, the 10-block differentiator circuit in Fig. 1 is used to sample the SW1, SW2, and SW3 signals at a predetermined period shorter than the sampling period of signal b shown in Fig. 2. It can also be realized with a circuit that takes differentiation. As described above, according to the present invention, key identification processing can be performed only for a predetermined period after a meaningful input change, and in order to collectively process inputs of input groups of keys, individual Since there is no need for processing such as a chattering prevention circuit for each key input, power consumption is reduced by reducing operation processing time in an integrated circuit equipped with a key detection function, and there is no individual chattering prevention circuit. It has the advantage of being able to be realized with less hardware. This effect is particularly remarkable in integrated circuits equipped with microcomputer control circuits.

[Brief explanation of drawings]

FIG. 1 shows one embodiment of the invention, in which blocks 10,
20, 30, and 40 indicate constituent elements of the present invention. 10... Selection differentiation circuit, 20... Flip-flop circuit, 30... Sampling clock generation circuit, 40... Key input determination circuit FIG. 2 is a timing chart showing the time sequence of each part signal in FIG. It is.

Claims (1)

[Claims] 1. A selection differentiator circuit that selects a predetermined input level change among changes in the input level of a key input group, a flip-flop circuit that is set by the output signal of the selection differentiator circuit, and when the flip-flop circuit is set. a sampling clock generation circuit that generates a predetermined number of sampling clocks, and a key input determination circuit that determines whether values of input signals of the key input group sampled by the predetermined number of sampling clocks match. A key input detection circuit comprising: an input signal of the key input group sampled when a match is determined by the key input determination circuit as input data.