JPH02304963A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To eliminate the need for a large area when constituting a level conversion circuit by forming a wiring layer at the lower side of an input pad where high voltage is input and by constituting a level conversion circuit with this capacity. CONSTITUTION:One or more wiring layers 3 and 5 are formed between an input pad where high voltage is input and a substrate 1 through an insulating film 2 and capacitor is formed between the input pad and the wiring layer, between the wiring layer and the substrate 1, and between each wiring layer. Thus, a capacity C1 can be formed at the first wiring layer 3, an interlayer insulating film 4, and the second wiring layer 5 and a capacity C2 is formed at the first wiring layer 3, the insulating film 2, and the semiconductor substrate 1. These capacities C1 and C2 can be connected between a bonding pad and an internal element, thus eliminating the need for a large area when constituting a level conversion circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device having a structure in which a high voltage input is converted to a low voltage and introduced into an internal circuit.

[Conventional technology]

Conventionally, this type of semiconductor integrated circuit device has, for example, as shown in FIG.
2 and a protection diode D are connected, and the high voltage input from the pad BP is divided by the resistors R1 and R2, converted to a low voltage, and input to the internal elements. Note that the protection diode D is for protecting the internal elements from high voltage.

Further, as another example, as shown in FIG. 6, a circuit is used in which a high voltage input is converted to a low voltage by a circuit having a flip-flop configuration. This is a low voltage type P-channel transistor PMO3.

The circuit is composed of PMO32, high voltage inverter INV, and high voltage N-channel transistors NMO3, NMOS2, and these transistors handle high voltage input,
It consists of a flip-flop with low voltage output and performs level conversion from high voltage to low voltage.

[Problems to be Solved by the Invention] In the conventional level conversion circuit described above, in the example shown in FIG. 5, a constant current flows through the resistors R3 and R2, so the resistance value must be set to a considerably large value.

However, creating a resistor with a large resistance value on a semiconductor integrated circuit device requires a large area, resulting in poor layout efficiency and a problem of increased power consumption due to constant current.

In addition, in the example shown in Figure 6, although no steady current flows, it is necessary to form a high-voltage transistor, which requires a large amount of area in the level conversion section, making the process complicated and increasing costs. There's a problem.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit device that can reduce circuit formation area, reduce power consumption, and be constructed at low cost.

[Means for Solving the Problems] The semiconductor integrated circuit device of the present invention forms one or more wiring layers with an insulating film interposed between the input pad to which a high voltage is input and the substrate. Capacitances are formed between the wiring layers, between the wiring layer and the substrate, and between the wiring layers.

Further, these capacitors are connected in series to form a voltage dividing circuit for inputting a high voltage.

[Effect]

With this configuration, a large area is not required when configuring a plurality of capacitors below the input pad and configuring a level conversion circuit.

Furthermore, since high voltage is divided by capacitance, constant current is suppressed to reduce power consumption, and high voltage transistors are not required, making it possible to reduce costs.

〔Example] Next, the present invention will be explained with reference to the drawings.

FIGS. 1(a) and 1(b) are a plan view of a first embodiment of the present invention and a cross-sectional view thereof taken along the line A--A, and FIG. 2 shows a circuit diagram of an example of its application.

As shown in FIG. 1, a plurality of strip-shaped first wiring layers 3 are arranged in parallel on an insulating film 2 of a semiconductor substrate 1.

An interlayer insulating film 4 is formed on this first wiring layer 3, and a second wiring layer 5 is further formed thereon to constitute a bonding pad BP. This bonding pad BP has a protective film 6
exposed within an opening provided in the

Here, by opening a contact 7 in a part of the interlayer insulating film 4 at one end of the first wiring layer 3, a part 8 of the second wiring layer 1 that is independent of the bonding pad 8 can be formed.
The wiring 8 is configured as a wiring for connecting to an internal element, and this wiring 8 is electrically connected to a part of the first wiring layer 3. Further, on the other end side of the first wiring layer 3, an arbitrary number of first wiring layers 3 are electrically connected to each other through a contact 10 by a wiring 9 formed from another part of the second wiring layer 5.

According to this configuration, the capacitor C1 can be configured by the first wiring layer 31, the interlayer insulating film 4, and the second wiring layer 5, and the first wiring layer 3.
Insulating film 2. The semiconductor substrate 1 can constitute the capacitor C2. These capacitors C+, Cz can be connected between the bonding pad and the internal elements. For example, if the area of the bonding pad is 100 μm square, a capacitance of about 1.0 to 1.3 pF can be formed. In addition, this capacitance reduces the electrode area of the first wiring layer 3 to the contact 1
Since it can be varied by changing the connection structure of 0 and the wiring 9, it can be changed to any value.

Therefore, when the capacitor configured in this way is connected between the bonding pad BP and the internal elements together with the protection diodes 11 and 12 as shown in the circuit diagram of FIG. 2, level conversion is performed as follows. Ru.

That is, when a high voltage E is input to the bonding pad BP, it is divided by the capacitors Ct and Cz, and the input voltage E to the internal elements theoretically becomes E+ = CIEH/ (CI + C2). however,
Since the high voltage is a pulsed signal voltage, it may deviate from between the low voltage vL and the reference potential (GND), and this is limited by the protection diodes 11 and 12.

Further, the insulating layer used as a dielectric of the capacitor is separated for each capacitor forming portion.

FIG. 3 is a plan view of a second embodiment of the present invention, and FIG. 4 is an applied circuit diagram thereof.

In this embodiment, as shown in FIG. 3, a polycrystalline silicon wiring layer 13 is formed under the first wiring layer 3, and the second wiring layer 5 as a bonding pad and the first wiring layer 3 are connected to each other. A capacitor 1c1 is formed between the first wiring layer 3 and the polycrystalline silicon wiring layer 13, and a capacitor C3 is formed between the polycrystalline silicon wiring layer 13 and the semiconductor substrate 1. are doing.

As shown in FIG. 4, capacitors C, , C, , C3 are connected in series to the bonding pad BP.

Further, an inverter is configured by the P-channel transistor 14 and the N-channel transistor 15, and the open terminal between C1 and C2, which is connected via the contact 7A and the wiring 8A, is connected to the gate of the P-channel transistor 14, and the contact 1 is connected to the gate of the P-channel transistor 14.
Ci, C<open terminal B, which is connected via -7B and wiring 8B, is connected to the gate of N-channel transistor 15.

Note that 16 to 19 are protection diodes.

With this circuit configuration, the high voltage input to the bonding pad BP can be divided by the capacitance, and this can be input to the internal elements at the reference voltage level as the input of the inverter.
Level conversion can be performed.

At this time, since the terminal A is always at a slightly higher potential than the terminal B, each transistor 14, 15 takes a shorter time to turn off and takes a longer time to turn on. Therefore, the circuit configuration has low power consumption.

Conversely, if the terminal A is connected to the gate of the N-channel transistor 15 and the terminal B is connected to the gate of the P-channel transistor 14, a speed-up circuit configuration with a short turn-on time can be obtained.

〔Effect of the invention〕

As explained above, in the present invention, a wiring layer is formed under the input pad to which a high voltage is input to form a capacitor, and this capacitance forms a level conversion circuit. A large area is not required to do so. This increases the layout efficiency on the semiconductor integrated device and lowers the chip unit price.

Furthermore, since a high voltage voltage dividing circuit is constructed by connecting a plurality of capacitors in series, constant current can be suppressed and power consumption can be kept low.

Furthermore, since high voltage transistors are not required, the process can be simplified, and the area and cost can be reduced.

[Brief explanation of drawings]

FIG. 1(a) is a plan view of the main parts of one embodiment of the present invention.
Figure (b) is a sectional view taken along line A-A in Figure 1 (a),
The figure is a circuit diagram of a level conversion circuit that applies the structure shown in Figure 1.
FIG. 3 is a plan view of the main part of another embodiment of the present invention, FIG. 4 is a circuit diagram of a level conversion circuit to which the structure of FIG. 3 is applied, and FIG.
The figure is a circuit diagram of an example of a conventional level conversion circuit, and FIG. 6 is a circuit diagram of another example of a conventional level conversion circuit. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... Insulating film, 3... First wiring layer, 4... Interlayer insulating film, 2... Second wiring layer, 6...
・Protective film, 7.7A, 7B...Contact, 8.8A
, 8B... Wiring, 9... Wiring, 10... Contact, 11.12... Protection diode, 13... Polycrystalline silicon wiring layer, 14... P channel transistor, 15... N-channel transistor, 16-19...
・Protection diode. Figure 1 Figure 2. Figure 3 Figure 4 Figure 5 VL Figure 6 VL VL

Claims (1)

[Claims] 1. In a semiconductor integrated circuit device to which a high voltage is input,
One or more wiring layers are formed between the input pad and the substrate via an insulating film, and capacitances are formed between the input pad and the wiring layer, between the wiring layer and the substrate, and between the wiring layers. A semiconductor integrated circuit device characterized by: 2. The semiconductor integrated circuit device according to claim 1, wherein a plurality of capacitors are connected in series to the input pad, and these capacitors constitute a voltage dividing circuit for inputting a high voltage.