JP2001177056A - Semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a capacitive element having a high capacitance with a small area. SOLUTION: The semiconductor integrated circuit device has capacitive elements having a dielectric film sandwiched with first and second electrodes. The capacitive elements have such a structure that a plurality of first and second electrodes are disposed so that the first and second electrodes mutually face in the plane direction and the thickness direction.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor integrated circuit device, and more particularly to a technique effective when applied to a semiconductor integrated circuit device having a capacitance element.

[0002]

As a semiconductor integrated circuit device, a semiconductor integrated circuit device is known for example, referred to as the analog IC (I ntegrated C ircuit). In this analog IC, a plurality of capacitive elements having a laminated structure in which a first electrode, a dielectric film, and a second electrode are sequentially laminated are used. An analog IC having a laminated structure of a capacitance element is described in, for example, Japanese Patent Application Laid-Open No. 4-127120.

[0003]

By the way, as the integration density of the semiconductor integrated circuit device is increased, a small-area and large-capacity capacitive element is desired. The capacitance of the capacitive element is proportional to the effective area of the dielectric film between the first electrode and the second electrode (the effective area between the electrodes) and inversely proportional to the thickness of the dielectric film. In the case where is constant, it is necessary to increase the effective area of the dielectric film to increase the capacity.

However, since the conventional capacitive element has a structure in which one dielectric film is sandwiched between one first electrode and one second electrode, the effective area of the dielectric film is increased. As a result, the area occupied by the capacitance element increases. That is, it is difficult to increase the capacitance in a small area in the conventional capacitance element.

An object of the present invention is to provide a technique capable of obtaining a large-capacity element with a small area.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0007]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

In a semiconductor integrated circuit device having a capacitor in which a dielectric film is sandwiched between a first electrode and a second electrode, the capacitor is formed in the first direction in a plane direction and a thickness direction.
It has a structure in which a plurality of the first electrodes and the second electrodes are arranged so that the electrodes and the second electrodes face each other.

According to the above-described means, the dielectric film sandwiched between the first electrode and the second electrode can be provided in the plane direction (horizontal direction) and the thickness direction (vertical direction). The effective area of the dielectric film between the first electrode and the second electrode (the effective area between the electrodes) can be increased without increasing the occupied area. As a result, a large-capacitance element with a small area can be obtained.

[0010]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments of the present invention, components having the same functions are denoted by the same reference numerals, and their repeated description will be omitted.

FIG. 1 is a plan layout view of a semiconductor integrated circuit device according to an embodiment of the present invention, FIG. 2 is an equivalent circuit diagram of a filter circuit mounted on the filter circuit portion of FIG. 1, and FIG. FIG. 4 is a schematic cross-sectional view showing a schematic configuration of the element, and FIG. 4 is a schematic plan view showing an electrode pattern of the capacitive element shown in FIG.

As shown in FIG. 1, the semiconductor device according to this embodiment is
The integrated circuit device has a plurality of external terminals (bonding pads)
In the area surrounded by 7, add analog circuits.
Width circuit section 1, filter circuit section 2, A / D (Analog /Di
gital) conversion circuit 3, PLL (PhaseLockedLoo
p) It has a circuit section 4 and a power supply circuit section 5, etc.
It has a configuration having a logic circuit section 6 composed of a circuit.
Each of these circuit units is mainly composed of an n-channel conductive type MOSF.
ET (MetalOxideSemiconductorFieldEffect
Transistor) and p-channel MOSFET
Combined CMOS (ComplementaryMOS) Circuit structure
It has become.

The filter circuit section 2 is provided with a plurality of high-pass filter circuits HPF shown in FIG. The high-pass filter circuit HPF has a configuration mainly including the amplifier 8, the capacitor C, and the resistor R.

The capacitive element C has a structure in which the first electrode and the second electrode sandwiching the dielectric film face each other in a plane direction (horizontal direction) and a thickness direction (vertical direction). It has a structure of multiple arrangements. Hereinafter, a specific configuration of the capacitor C will be described with reference to FIGS. In the present embodiment, the two electrodes (13, 17) are used as the first electrodes, and the two electrodes (14, 18) are used as the second electrodes.
It is used as an electrode, and the interlayer insulating films 11 and 15 are used as a dielectric film.

Each of the electrode 13 as the first electrode and the electrode 14 as the second electrode is formed on the interlayer insulating film 11 on the semiconductor substrate 10.
Is formed inside the groove provided in the groove. The electrode 13 is
As shown in FIG. 4B, the structure has one sub-electrode portion 13A extending in the X direction and two main electrode portions (13B, 13C) extending in the Y direction. One end of the main electrode portion 13B is connected to one end of the sub-electrode portion 13A, and one end of the main electrode portion 13C is connected to the other end of the sub-electrode portion 13A. That is, the electrode 13 has a flat U-shaped electrode pattern. The electrode 14 is shown in FIG.
As shown in (b), one sub-electrode portion 14A extending in the X direction and two main electrode portions (14
B, 14C). One end of the main electrode portion 14B continues to one end of the sub-electrode portion 14A,
One end of the main electrode portion 14C is connected to the other end of the sub-electrode portion 14A. That is, the electrode 14 has a flat U-shaped electrode pattern.

Each of the first electrode 17 and the second electrode 18 is formed on the interlayer insulating film 15 on the interlayer insulating film 11.
Is formed inside the groove provided in the groove. The electrode 17
As shown in FIG. 4A, the structure has one sub-electrode portion 17A extending in the X direction and two main electrode portions (17B, 17C) extending in the Y direction. One end of the main electrode portion 17B is connected to one end of the sub-electrode portion 17A, and one end of the main electrode portion 17C is connected to the other end of the sub-electrode portion 17A. That is, the electrode 17 has a U-shaped electrode pattern on its plane. The electrode 18 is shown in FIG.
As shown in (a), one sub-electrode portion 18A extending in the X direction and two main electrode portions (18
B, 18C). One end of the main electrode portion 18B is connected to one end of the sub-electrode portion 18A,
One end of the main electrode portion 18C is connected to the other end of the sub electrode portion 18A. That is, the electrode 18 has a flat U-shaped electrode pattern.

The interlayer insulating films 11 and 15 are formed of, for example, a silicon oxide film. Electrodes (13, 14, 17, 1)
8) is formed of, for example, a copper (Cu) film.

In the plane direction (horizontal direction) of the capacitive element C, each of the electrodes 13 and 14 is such that the main electrode portion 13C of the electrode 13 corresponds to each electrode portion (14A, 14B, 1) of the electrode 14.
4C) and the main electrode portion 14C of the electrode 14
Are arranged via the interlayer insulating film 11 so as to face the respective electrode portions (13A, 13B, 13C) of the electrode 13. Further, in each of the electrode 17 and the electrode 14, the main electrode portion 17C of the electrode 17 corresponds to each electrode portion (18A, 1A) of the electrode 18.
8B, 18C), and the main electrode portion 18C of the electrode 18 is connected to each electrode portion (17A, 17B, 1) of the electrode 17.
7C), and is arranged with an interlayer insulating film 15 interposed therebetween.

In the thickness direction (longitudinal direction) of the capacitive element C, the electrodes 13 and 18 are respectively composed of a main electrode portion (13B, 13C) of the electrode 13 and a main electrode portion (18) of the electrode 18.
B, 18C) so as to face each other.
5 are interposed. In addition, electrode 14, electrode 1
7 are the main electrode portions of the electrode 14 (14B, 14C)
And main electrode portions (17B, 17C) of electrode 17 are arranged with interlayer insulating film 15 interposed therebetween so as to face each other. Each of the electrode 13 and the electrode 17 is disposed with the interlayer insulating film 15 interposed therebetween such that the sub-electrode portion 13A of the electrode 13 and the sub-electrode portion 17A of the electrode 17 face each other. Further, each of the electrode 14 and the electrode 18 is the electrode 1
The fourth sub-electrode portion 14A and the sub-electrode portion 18A of the electrode 18 are arranged with the interlayer insulating film 15 interposed therebetween so as to face each other.

Each of the electrodes 13 and 17 is an interlayer insulating film 1
The electrode 14 and the electrode 18 are electrically connected to each other through a connection hole provided in the interlayer insulating film 15.
Electrical connection between these electrodes is made at respective sub-electrode portions (13A and 17A, 14A and 18A). Each of the electrodes 13 and 17 is electrically connected to the amplifier 8 of the high-pass filter circuit HPF via a wiring, and each of the electrodes 14 and 18 is electrically connected to the next-stage circuit via the wiring. I have.

The interlayer insulating film 11 interposed between the electrodes 13 and 14 functions as a dielectric film, and a capacitance is formed at this portion. The interlayer insulating film 15 interposed between the electrodes 17 and 18 functions as a dielectric film, and a capacitance is formed in this portion. The main electrode portions (13B, 13C) of the electrode 13 and the main electrode portions (18B,
18C) acts as a dielectric film, and a capacitance is formed in this portion. The interlayer insulating film 15 interposed between the main electrode portions (14B, 14C) of the electrode 14 and the main electrode portions (17B, 17C) of the electrode 17 functions as a dielectric film, and a capacitance is formed in this portion. That is, the first electrode and the second electrode are sandwiched between the first electrode and the second electrode by arranging a plurality of the first electrode and the second electrode such that the first electrode and the second electrode face each other in the plane direction and the thickness direction. Since the dielectric film can be provided in the plane direction and the thickness direction, the effective area of the dielectric film between the first electrode and the second electrode (the effective area between the electrodes) can be increased without increasing the area occupied by the capacitor C. Area) can be increased.

The effective area of the dielectric film sandwiched between the electrode 13 as the first electrode and the electrode 14 as the second electrode is proportional to the thickness of the electrode 13 and the electrode 14 facing each other.
The effective area of the dielectric film sandwiched between the electrode 17 as the first electrode and the electrode 18 as the second electrode is proportional to the film thickness of the electrode 17 and the electrode 18 facing each other. It is desirable to make the film thickness larger than that. In this embodiment, each electrode has a width of, for example, 0.25 [μ
m] and a thickness of 0.4 [μm].

The capacitance between the electrode 13 as the first electrode and the electrode 14 as the second electrode is inversely proportional to the thickness of the dielectric film sandwiched between the electrodes 13 and 14, and the first electrode Since the capacitance between the electrode 17 and the second electrode 18 is inversely proportional to the thickness of the dielectric film sandwiched between the electrode 17 and the electrode 18, the thickness of these dielectric films is small. It is desirable to set the dimension between the electrodes so as to be as follows.
In the present embodiment, the dimension between the electrodes in the plane direction is set to, for example, 0.25 [μm].

The capacitance between the main electrode portion (13B, 13C) of the electrode 13 as the first electrode and the main electrode portion (18B, 18C) of the electrode 18 as the second electrode is the same as that of the main electrode of the electrode 13. It is inversely proportional to the thickness of the dielectric film sandwiched between the main electrode portion of the electrode 18 and the main electrode portion (14B, 14C) of the electrode 14 as the second electrode and the electrode 1 as the first electrode.
Since the thickness is inversely proportional to the thickness of the dielectric film sandwiched between the main electrode portions (17B, 17C) of 7, the dimensions between the electrodes are desirably set so that the thickness of these dielectric films is reduced. . However, since each electrode of the present embodiment is formed together with the wiring in the wiring forming step, in such a case, the parasitic capacitance formed by the lower wiring and the upper wiring and the insulation resistance between the upper and lower wirings are taken into consideration. There is a need to. In the present embodiment, the dimension between the electrodes in the thickness direction is set to, for example, 0.5 [μm].

Next, the production of the capacitive element C will be described with reference to FIGS. 5 and 6 (schematic sectional views). Capacitive element C
Are formed together with the wiring in the wiring forming step.

First, after a transistor element or the like is formed on the main surface of the semiconductor substrate 10, an interlayer insulating film 11 made of, for example, a silicon oxide film is formed on the main surface of the semiconductor substrate 10, and then the surface of the interlayer insulating film 11 is formed. the CMP (C hemical M ec
flattened by hanical P olishing) method, then, 5
As shown in FIG. 3A, a groove 11A and a groove 11B having a U-shaped pattern are formed in the interlayer insulating film 11.
In this step, a groove for forming a wiring is also formed.

Next, and FIG. 5 (b) as shown in, CVD conductive film 12 made of the entire surface, for example, a Cu film on the interlayer insulating film 11 including the inside of the groove (C hemical V apor D eposition)
After that, an excess conductive film 12 on the surface of the interlayer insulating film 11 is removed by a CMP method so that the conductive film 12 remains inside the groove. Thus, as shown in FIG. 5C, the electrodes 13 and 14 are formed inside the groove.
Although not shown, a wiring is formed inside the groove.

Next, an interlayer insulating film 15 made of, for example, a silicon oxide film is formed on the entire surface of the interlayer insulating film 11 including on each electrode and on the wiring, and thereafter, as shown in FIG.
A groove 15A and a groove 15B having a U-shaped pattern are formed in the interlayer insulating film 15. In this step, a groove for forming a wiring is also formed.

Next, a connection hole reaching the sub-electrode portion 14A of the electrode 14 from the bottom surface of the groove 15A, a connection hole reaching the main electrode portion 13A of the electrode 13 from the bottom surface of the groove 15B, and the like are formed. As shown in (e), a conductive film 16 made of, for example, a Cu film is formed on the entire surface of the interlayer insulating film 15 including the inside of the connection hole and the groove by the CVD method, and thereafter, the conductive film 16 remains inside the groove. As described above, the excess conductive film 16 on the surface of the interlayer insulating film 15 is removed by the CMP method. As a result, as shown in FIG.
8 are formed. Further, by this step, the capacitive element C having a structure in which a plurality of first electrodes and second electrodes are arranged so as to face each other in the plane direction and the thickness direction is formed.

As described above, according to the present embodiment, the following effects can be obtained. The capacitive element C has a structure in which a plurality of first electrodes and second electrodes are arranged such that the first electrode and the second electrode face each other in the plane direction and the thickness direction. With such a configuration, the first electrode and the second
Since the dielectric film sandwiched between the electrodes can be provided in the plane direction (horizontal direction) and the thickness direction (vertical direction), the first electrode and the second electrode can be provided without increasing the area occupied by the capacitor C. Effective area of the dielectric film between the electrodes (effective area between electrodes)
Can be increased. As a result, a large-capacity capacitive element C with a small area can be obtained.

Further, since the capacitance element C having a small area and a large capacity can be obtained, high integration of the semiconductor integrated circuit device can be achieved.

In this embodiment, the first electrode and the second electrode
Although the example in which the electrodes are stacked in two stages has been described, the first electrode and the second electrode may be stacked in three or more stages. In this case, the effective area of the dielectric film between the first electrode and the second electrode can be further increased without increasing the area occupied by the capacitor.

In the present embodiment, each electrode (13, 14, 1) is formed in a planar pattern shape having two main electrode portions.
7, 18) has been described, but each electrode may be formed in a planar pattern shape having three or more main electrode portions. Also in this case, the effective area of the dielectric film between the first electrode and the second electrode can be further increased without increasing the area occupied by the capacitor.

As described above, the invention made by the present inventor is:
Although specifically described based on the embodiment, the present invention
It is needless to say that the present invention is not limited to the above-described embodiment, but can be variously modified without departing from the scope of the invention.

For example, according to the present invention, in order to prevent fluctuation of the power supply potential due to switching noise in the logic circuit portion,
The present invention can be applied to a capacitor inserted between power supply wirings for decoupling.

Further, the present invention can be applied to a capacitive element mounted as an oscillation stop in an analog circuit section.

[0037]

The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows. According to the present invention, a large-capacity element with a small area can be obtained.

[Brief description of the drawings]

FIG. 1 is a plan layout diagram of a semiconductor integrated circuit device according to an embodiment of the present invention.

FIG. 2 is an equivalent circuit diagram of a filter circuit mounted on the filter circuit unit of FIG.

FIG. 3 is a schematic cross-sectional view illustrating a schematic configuration of the capacitive element in FIG.

FIG. 4 is a schematic plan view showing an electrode pattern of the capacitive element in FIG.

FIG. 5 is a schematic cross-sectional view for explaining manufacturing of the capacitive element of FIG.

FIG. 6 is a schematic cross-sectional view for explaining manufacturing of the capacitive element of FIG.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Amplification circuit part, 2 ... Filter circuit part, 3 ... A / D conversion circuit part, 4 ... PLL circuit part, 5 ... Power supply circuit part, 6 ... Logic circuit part, 7 ... External terminal, 8 ... Amplifier, 10 ... Semiconductor substrate, 11, 15 ... interlayer insulating film, 11A, 11B, 15
A, 15B ... groove, 12, 16 ... conductive film, 13, 14, 1
7, 18 ... electrodes, 13A, 14A, 17A, 18A ... sub-electrode portions, 13B, 13C, 14B, 14C, 17B,
17C, 18B, 18C: Main electrode portion, HPF: High-pass filter circuit, C: Capacitance element.

Claims (1)

[Claims] 1. A semiconductor integrated circuit device having a capacitor in which a dielectric film is sandwiched between a first electrode and a second electrode, wherein the capacitor is arranged in a first direction in a plane direction and a thickness direction. So that the first and second electrodes face each other.
A semiconductor integrated circuit device having a structure in which a plurality of electrodes and a plurality of second electrodes are arranged.