JPH02281365A - Information processor - Google Patents

Abstract

PURPOSE:To increase a processing speed as the whole by using a control line provided for the processor, which executes a dedicated instruction, independently of an information bus at the time of judging that the dedicated instruction should be executed and giving an address to a program memory to start it and directly reading out the dedicated instruction from a memory. CONSTITUTION:An interpreter type general processor 1 is used for general instructions 1 to 4, and a dedicated processor 2 is used for dedicated instructions 1 to 4. An information processor is constituted in this manner, and general instructions 1 and 2 are successively read out of a program memory 3 by the processor 1 and are interpreted and executed, and the dedicated instruction 1 in an address X1 is read out and is interpreted; and when it is judged that the instruction is an instruction for the dedicated processor, the address X1 of the dedicated instruction 1 is transmitted to the processor 2 through a control line L to start the processor 2. Then, the processor 2 gets the use right of an information bus 2 and executes dedicated instructions 1 to 4 in accordance with the address X1. Thus, dedicated instructions are directly read out without passing the processor 1.

Description

DETAILED DESCRIPTION OF THE INVENTION <Field of Industrial Application> The present invention relates to an information processing device in which a first processor and a second processor operate alternately according to translated program instructions stored in a program memory. ,especially,
This improves the switching method between the first processor and the second processor.

<Prior Art> FIG. 7 shows an example of an apparatus in which a first processor and a second processor operate by alternately reading one program memory.

The device shown in this figure includes a general-purpose processor (e.g., 16-pit microprocessor eaooo) as the first processor 1, and a dedicated processor (e.g., 68,000 microprocessor, etc.) that executes numerical or logical operations as the second processor 2. family, etc.) are connected to the program memory 3 via an information bus b.

The program memory 3 normally stores machine language instructions as program instructions for the general-purpose processor 1, and the general-purpose processor 1 sequentially reads these machine language instructions and executes the processing, and the read instructions are transferred to the dedicated processor. 2
When an instruction is to be executed in the program memory 3, it gives operation instructions and data preparation to the dedicated processor 2.
sequentially supplies the instructions read from the dedicated processor 2,
Grant control execution rights.

In such a conventional information processing device, a general-purpose processor 1
and dedicated processor 2, the design problem is that the machine language instructions to be stored in program memory 3 must be distributed and set in advance for general-purpose processor 1 and dedicated processor 2 at the processor design stage. It was annoying.

On the other hand, recently, basic interpreter type instructions are often used, and interpreted type instructions (single station type program instructions) are stored in the program memory 3 independently of the machine language instructions specific to the general-purpose processor 1. are increasingly being stored.

In a device that uses such interpreted instructions, a pool of instructions executed by the general-purpose processor 1 is executed by the dedicated processor 2! There is no need to set instructions for general-purpose processor 1 and instructions for dedicated processor 2 separately at the design stage of general-purpose processor 1. Since the processor 1 or the dedicated processor 2 is designated for execution, it is efficient in practice, and the instructions to be executed by the dedicated processor 2 can be expanded.

<Problems to be Solved by the Invention> However, when a dedicated processor operates using machine language instructions or interpreted instructions, the general-purpose processor 1 sequentially reads program instructions from the program memory 3 and executes the dedicated processor. There was a problem in that there was wasted time in transferring the program to supply it to the processor.

In addition, when using interpreted instructions, the instructions read by the general-purpose processor 1 must be translated one by one, which takes extra time, especially in devices where the general-purpose processor and dedicated processor are frequently switched. It was occurring.

The present invention has been made to solve the above-mentioned problems, and aims to simplify the switching operation between a general-purpose processor and a dedicated processor, and to speed up the overall processing time.

Means to solve problems〉 The present invention that solves the above problems is as follows.

(1) A first processor, a second processor, and a program memory in which translated program instructions and dedicated instructions are stored are connected by an information bus, and the first processor and the second processor are connected to each other by an information bus. A control line is provided for bidirectional signal transmission between the two processors, and when one of the executing processors determines that the program command should be executed by the other processor, the command is sent to the other processor via the control line. An information processing device characterized in that the processor that executes the dedicated instruction reads and executes the dedicated instruction directly from the program memory by suddenly knowing the address of the program memory to be executed and activating the program memory.

(2) the first processor is connected via a first information bus to a program memory in which translated program instructions and dedicated instructions are stored; the first processor;
When the processor operates, it reads a program instruction from the program memory and executes it, and also gives a pseudo-instruction to the second processor, which is executed by the second processor in the first processor. An information processing apparatus characterized in that when determining that a program instruction is to be executed, the program instruction is supplied in place of the pseudo-instruction.

(3) a first processor, a first program memory area that stores program instructions to be executed by the first processor and instructions to instruct a second processor to execute; a second program memory area that stores program instructions to be executed by a second processor and instructions to instruct the first processor to execute; An information processing device comprising a signal synthesizing means that inputs an instruction to the processors to execute an instruction, instructs one processor to start operating, and instructs the other processor to stop operating.

(1) When it is determined that a dedicated instruction should be executed, the program memory address is given to the processor executing the dedicated instruction using a control line provided separately from the information bus, and the processor is started up. The processor that executes the dedicated instructions reads the dedicated instructions directly from the program memory and executes them without going through the other processor.

(2) While the first processor is executing, a pseudo-instruction is supplied to the second processor, and when the second processor determines that the instruction is to be executed, the instruction read from the program memory is sent to the second processor. supply to

(3) When one processor reads its own program memory area and reads out an instruction that instructs the other processor to operate during execution, the signal synthesis means instructs one processor to stop operating according to this instruction, and the other processor Instructs the processor to start operating.

<Embodiment> FIG. 1 is a block diagram of an embodiment of an information processing apparatus of the present invention.

A feature of this embodiment is that a control line is installed between the general-purpose processor 1 and the dedicated processor 2, separate from the information bus b, so that they can exchange signals with each other.

Using this control line, the two processors 1.2 notify each other of the current read address of the program memory 3 and the activation signal.

Note that the program memory 3 stores the above-mentioned interpreted instructions and also stores dedicated instructions for the dedicated processor 2.

The operation of such a device is described in the program memory 3 in Fig. 2.
This will be explained using an internal configuration diagram.

In this figure, general-purpose instructions 1 to 4 are general-purpose processor instructions (interpreter-type instructions), and special-purpose instructions 1 to 4 are special-purpose instructions for a special-purpose processor 2.

General-purpose processor 1 sequentially reads general-purpose instruction 1 and general-purpose instruction 2 from program memory 3 according to arrow A, translates and executes them.

Next, the general-purpose processor 1 reads the dedicated instruction 1 at the address Dedicated instruction 1 in 3
address X1, and activates the dedicated processor 2.

As a result, the dedicated processor 2 acquires the right to use the information bus b, and receives the program from the general-purpose processor 1.
Dedicated instructions 1, 2, 3, 4 are executed as indicated by arrow C according to address x1 of memory 3.

At this time, the dedicated processor 2 does not receive and receive the dedicated instructions via the general-purpose processor 1 as in the conventional device, but directly receives the dedicated instructions 1.2.3.
Read out 4.

Further, the dedicated instruction is a specific instruction of the dedicated processor 2,
During execution, the dedicated processor 2 does not perform any translation operations.

Now, when the special-purpose processor 2 reads the general-purpose instruction 3 at address x2 and determines that it is a general-purpose instruction that should be executed by the general-purpose processor 1 (arrow D), the special-purpose processor 2 then transfers the general-purpose instruction 3 to the general-purpose processor 1 via the control line. The program
The address X2 of the general-purpose instruction 1 in the memory 3 is transmitted, and the general-purpose processor 1 is activated.

As a result, after acquiring the right to use the information bus b, the general-purpose processor 1 moves from the address x2 to the program memory 3.
is read and the operation is executed (arrow E).

As described above, the general-purpose processor 1 and the special-purpose processor 2 transmit and receive the address of the program memory 3 and the start signal via the control line, and operate alternately. Since instructions are read directly from the program memory 3, high-speed processing is possible.

Further, as described above, the dedicated processor 2 does not require a translation operation when executing a dedicated instruction, and this time can also be omitted.

FIG. 3 shows another embodiment of the information processing apparatus of the present invention.

In this embodiment, the general-purpose processor 1 is connected to the first information bus b.
1 to the dedicated processor 2, and the dedicated processor 2 to the program memory 3 using the second information bus b2.
Connect to.

A program memory 3 is stored in the dedicated processor 2.
Program instruction acquisition circuit 2 connected to side information bus b2
1, a program instruction successive generation circuit 22 connected to the information bus b1 on the general-purpose processor 1 side, and a pseudo-instruction generation circuit 23 that holds a pseudo-instruction meaning "not executed" for the general-purpose processor 1. Install. The program instruction successive output circuit 22 also includes a program instruction acquisition circuit 21.
Alternatively, a switching circuit 24 for selecting the pseudo-instruction generation circuit 23 is installed.

In this embodiment, as in the embodiment shown in FIG. 1, the program memory 3 stores interface type instructions and also stores dedicated instructions for the dedicated processor 2.

The operation of the device of the present invention configured in this way is shown in FIG. 4(a).
This will be explained using (b).

FIG. 4(a) shows a case where the general-purpose processor 1 executes an instruction.

The dedicated processor 2 reads the instruction l read at address Y1.
is determined to be for the general-purpose processor 1, and switches the switching circuit 24 in the dedicated processor 2 to the program instruction import circuit 21 side. Then, the read instruction 1 passes through the dedicated processor 2 and is given to the general-purpose processor 1 by the program instruction successive output circuit 22, and the general-purpose processor 1 operates.

Note that even when the general-purpose processor 1 is operating, the program memory 3
The read address for is generated from the dedicated processor 2.

FIG. 4(b) shows a case where the dedicated processor 2 executes an instruction.

Dedicated processor 2 reads instruction 2 at address Y2.
is a command that should be processed by itself, and the switching circuit 24
The pseudo-instruction generation circuit 23 and the program instruction acquisition circuit 22 are connected using the. As a result, the dedicated processor 2 executes the program according to the read address generated by itself.
An instruction is read from the memory 3 and executed, and the general-purpose processor 1 does nothing due to a pseudo-instruction N meaning "do not execute" given from the special-purpose processor 2.

In this way, the instructions read from the program memory 3 are reliably given to the general-purpose processor 1 or the special-purpose processor 2 depending on their purpose, and switching between the general-purpose processor 1 and the special-purpose processor 2 is performed smoothly without wasting time.

In the example shown in FIG. 3, the dedicated processor 2 is installed between the general-purpose processor 1 and the program memory 3;
, program instruction successive generation circuit 22, pseudo-instruction generation circuit 23
, a configuration in which a circuit element corresponding to the switching circuit 24 is provided and the general-purpose processor 1 is placed in the middle is also equivalent.

In addition, in this example, the processor installed in the intermediate section generates the address for the program memory 3, so even if the processor that executes the instruction is switched, the processor in the intermediate section always knows the progress status of the program, and the processor in the intermediate section always knows the progress status of the program. The time required to send and receive addresses to and from the memory 3 can be saved.

On the other hand, FIG. 5 shows the embodiment shown in FIG. 3 in which the address generated by the general-purpose processor 1@ can be given to the program memory 3 side.

In this example, in the dedicated processor 2, there is an address reading circuit 25 that takes in an address generated by the general-purpose processor 1 on the information bus bl side, and an address sending circuit 26 that gives a read address of the program memory 3 on the information bus b2 side.
and a switching circuit 27. Furthermore, the switching circuit 27
The address output path 26 and the address reading circuit 25 or the address generating circuit 28 inside the dedicated processor 2 are connected.

The operation of this embodiment will be explained with reference to FIGS. 6(a) and 6(b).

FIG. 6(a) shows a case where the general-purpose processor 1 executes an instruction, and the switching circuit 24 in the dedicated processor 2 is connected to the program instruction acquisition circuit 21, and the switching circuit 27 is connected to the address reading circuit 25. Connected. Then, the address Z1 generated by the general-purpose processor 1 is given to the program memory 3 via the special-purpose processor 2, and the corresponding instruction 1 is given to the general-purpose processor 1 through the special-purpose processor 2.

FIG. 6(b) shows a case where the dedicated processor 2 executes an instruction, and the switching circuit 24 in the dedicated processor 2 is connected to the pseudo-instruction generation circuit 23, and the switching circuit 27 is connected to the address generation circuit 28. be done. Then, the special-purpose processor 2 reads the instruction 2 using the internally generated address Y3 and executes it, and the general-purpose processor 1 reads the pseudo-instruction N from the special-purpose processor 2 and does not execute anything.

The example shown in FIG. 5 is particularly advantageous in that the general-purpose processor 1 can access any location in the program memory 3 and execute a jump instruction or the like.

As described above, even in the embodiment shown in FIG. 3 or FIG. 5, the general-purpose processor 1 and the special-purpose processor 2 operate alternately according to instructions read from the program memory 3. 2 reads instructions directly from the program memory 3, which allows for faster processing.

Further, since the dedicated instruction is a unique instruction of the dedicated processor 2, no translation operation is required when the dedicated processor 2 executes it, and this time can also be omitted.

FIG. 7 shows another embodiment of the information processing apparatus of the present invention.

In this embodiment, a first program memory area 31 in which only general-purpose instructions are stored is connected to a general-purpose processor 1 via an information bus b1, and a first program memory area 31 in which only general-purpose instructions are stored is connected to a general-purpose processor 2 via an information bus b1.
2 to connect a second program memory area 32 in which only dedicated instructions are stored. Further, a first output port 41 is connected to the information bus b1, and a second output port 42 is connected to the information bus b2. The outputs of the output port 41 and the output port 42 are given to a signal synthesis section 43, and the signal synthesis section 43 instructs the general-purpose processor 1 and the special-purpose processor 2 to start or stop operation.

The contents of the program memory areas 31 and 32 are shown in Figure 8 (a).
) and (b).

The program memory area 31 stores general-purpose instructions 1 to 5 and the general-purpose instruction OUT that instructs the special-purpose processor 2 to start operation, and the program memory area 32 stores the special-purpose instructions 1 to 5.
.about.4 and a dedicated instruction 0tlT instructing the general-purpose processor 1 to start operation.

The operation of such an embodiment will be explained next.

First, assume that the general-purpose processor 1 is operating.

At this time, the signal synthesis unit 43 instructs the general-purpose processor 1 to operate, and instructs the dedicated processor 2 to stop operating.

The general-purpose processor 1 sequentially reads general-purpose instructions 1 and 2 from the program memory area 31 and executes them, and then reads the general-purpose instruction OUT that instructs the dedicated processor 2 to operate.
This is sent to the output port 41.

When the signal synthesis unit 43 reads the output port 41 and recognizes the general-purpose instruction OUT, it gives an instruction to the general-purpose processor 1 to stop operation, and gives an instruction to the special-purpose processor 2 to start operation.

As a result, the dedicated processor 2 starts operating,
A dedicated instruction is read from the program memory area 32 and executed. When the dedicated instruction 2 is executed and then the dedicated instruction OUT is read, it is sent to the output port 42.

When the signal synthesis unit 43 reads the output port 42 and recognizes the dedicated instruction OUT, it instructs the dedicated processor 2 to stop its operation and instructs the general-purpose processor 1 to start its operation.

As a result, the general-purpose processor 1 starts operating again.

In this way, switching between the general-purpose processor 1 and the dedicated processor 2 is smoothly performed by the signal synthesis section 43.

9(a) and 9(b) are almost the same as the embodiment shown in FIG. 7, and one information bus b includes output ports 41, 42,
This is an example in which a signal synthesis section 43 is connected.

In this example, the contents of program memory 3 are
As shown in figure (b), in one program memory 3,
An area A1 for storing only general-purpose instructions and an area A2 for storing only special-purpose instructions are set in advance.

The operation of this embodiment is exactly the same as the apparatus shown in FIG.

As described above, even in the embodiment shown in FIG. 7 or FIG. The dedicated processor 2 operates alternately in accordance with the instructions read from A2, and in particular, the dedicated processor 2 directly reads the dedicated instructions, which allows for faster processing.

Further, since the dedicated instruction is a unique instruction of the dedicated processor 2, no translation operation is required when the dedicated processor 2 executes it, and this time can also be omitted.

<Effects of the Invention> As described above, according to the information processing apparatus of the present invention, it is possible to simplify the switching operation between a general-purpose processor and a dedicated processor, and to realize faster overall processing time.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of an embodiment of the information processing device of the present invention, and FIG.
The figure shows the contents of the program memory 3 to explain the operation of the device shown in FIG. 1, FIG. 3 is a block diagram of another embodiment of the information processing device of the present invention, and FIG. 4(a) ,(b)
is a diagram representing the operation of the device shown in Figure 3, and Figure 5 is a diagram representing the operation of the device shown in Figure 3.
6(a) and 6(b) are diagrams showing the operation of the device shown in FIG. 5, and FIG. 7 is a diagram showing the operation of the device shown in FIG. FIGS. 8(a) and 8(b) are block diagrams of other embodiments of the information processing apparatus. Second program memory area 31.3
2, FIGS. 9(a) and 9(b) are configuration diagrams of an apparatus in which a part of the configuration of the embodiment shown in FIG. 7 is changed, and FIG. 10 is a configuration of a conventional information processing apparatus. It is a diagram. 1... General-purpose processor, 2... Dedicated processor, 2
DESCRIPTION OF SYMBOLS 1... Program instruction acquisition circuit, 22... Program instruction successive output circuit, 23... Pseudo-instruction generation circuit, 24.
...Switching circuit, 25...Address reading circuit, 26...
・Address exit circuit, 27...Switching circuit, 28...
Address generation circuit, 3...program memory, 31
...first program memory area, 32...second
program memory area, 41...first output port, 42...second output port, 43...signal synthesis unit, b...1 information bus, bl...first information bus ,b
2...Second information bus, L...Control line. Figure-2 Figure-2 Figure 4 (a)

Claims (3)

[Claims] (1) A first processor, a second processor, and a program memory in which translated program instructions and dedicated instructions are stored are connected by an information bus, and the first processor and the second processor are connected to each other by an information bus. A control line is provided for transmitting signals in both directions between the two processors, and when one of the executing processors determines that the program command is to be executed by the other processor, the command is sent to the other processor via the control line. An information processing device characterized in that an address of the program memory is notified and the processor is activated, and a processor executing the dedicated instruction directly reads and executes the dedicated instruction from the program memory. (2) the first processor is connected via a first information bus to a program memory in which translated program instructions and dedicated instructions are stored; the first processor;
When the processor operates, it reads a program instruction from the program memory and executes it, and also gives a pseudo-instruction to the second processor, which is executed by the second processor in the first processor. An information processing apparatus characterized in that when determining that a program instruction is to be executed, the program instruction is supplied in place of the pseudo-instruction. (3) a first processor, a first program memory area that stores program instructions to be executed by the first processor and instructions to instruct a second processor to execute; a second program memory area that stores program instructions to be executed by a second processor and instructions to instruct the first processor to execute; An information processing device comprising a signal synthesizing means that inputs an instruction to the processors to execute an instruction, instructs one processor to start operating, and instructs the other processor to stop operating.