JP3208789B2 - Information processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus, and more particularly to a memory request control of a transfer command between virtual spaces when a primary virtual space and a secondary virtual space are supported.

[0002]

2. Description of the Related Art When a conventional information processing apparatus supports a primary virtual space and a secondary virtual space, an ordinary instruction uses an access space designation flag which is a space designation means for designating a virtual space to be accessed. Although the space to be determined is the primary virtual space or the secondary virtual space, the move first instruction ignores the above-mentioned space specification flag and replaces the primary virtual space operand data. Access is performed to transfer the operand data of the secondary virtual space to the primary virtual space in the move second instruction. This is because, in the firmware stored in the control memory for performing the memory request control of the inter-virtual space transfer instruction, the primary virtual space designation information for ignoring the space designation flag and forcibly designating access to the primary virtual space And secondary virtual space designating information forcibly designating access to the secondary virtual space, when the memory access to the source operand data of the move first instruction and the destination of the move second instruction are performed. At the time of memory access to the operand data, access to the primary virtual space is specified by the above-described primary virtual space designation information of the firmware, and at the time of memory access to the destination operand data of the move first instruction,
The memory access to the source operand data of the move second instruction is performed by designating the access to the secondary virtual space by the secondary virtual space designation information of the firmware.

FIG. 4 is an explanatory diagram for explaining coding contents of a conventional memory request control firmware.

[0004] The distribution diagram (A) shows operands in the same space.
The content of the firmware coding of the move instruction for data transfer is displayed. As described above, the space accessed according to the move instruction depends on the designation of the access space designation flag. In this case, both the control of the source operand access (Step A0) and the control of the destination operand access (Step B0) are performed in the primary space. The value of the designated field and the secondary space designated field are “0”.

FIG. 1B shows the coding contents of the firmware of the move first command. As described above, the space accessed according to the move first instruction is a move operand access (Step A1).
Since the control is the primary virtual space designation, the value of the primary space designation field is set to "1" to force the designation of the primary virtual space access without depending on the designation of the access space designation flag. Since the access (Step B1) control specifies the secondary virtual space, the access to the secondary virtual space is forcibly specified.
The value of the secondary space designation field is "1".

[0006] The diagram (C) shows the coding contents of the firmware of the move / second command. As described above, the space accessed in accordance with the move second instruction is the reverse of the move first instruction, and the move operand access (Step A2) control specifies the secondary virtual space. Therefore, the value of the secondary space specification field is set to “1”. age,
Destination operand access (Step
B1) Since the control is the primary virtual space designation, the value of the primary space designation field is set to “1”.

[0007]

In the above-mentioned conventional information processing apparatus, the move first instruction ignores the designation of the space designation flag and transfers the operand data of the primary virtual space to the secondary virtual space. In the move second instruction, access is made to transfer the operand data in the secondary virtual space to the primary virtual space. In order to realize this control, the firmware stored in the control memory for performing the memory request control of the inter-virtual space transfer instruction ignores the above-mentioned space designation flag and forcibly designates the access to the primary virtual space. It has virtual space designation information and secondary virtual space designation information forcibly designating access to the secondary virtual space. Therefore, the move first instruction and the move second instruction require independent control of the request control firmware, even though they are all the same except for the virtual space specification. There is a problem that it is economically disadvantageous.

SUMMARY OF THE INVENTION An object of the present invention is to provide an information processing apparatus which can share request control firmware of each instruction and which is economical and requires no manufacturing labor.

[0009]

An information processing apparatus according to the present invention comprises: a primary virtual space designated by a primary virtual address converted by a first segment table;
Supports the secondary virtual space specified by the converted secondary virtual address in the table, and specifies whether the space to be accessed is the primary virtual space or the secondary virtual space
Comprising a space specifying means for outputting a first logic value, said move-first instruction and operand data to transfer to the secondary virtual space operand data without depending on the space specifying means from said primary virtual space two in information processing apparatus capable of executing the move seconds instruction to transfer the next virtual space in the primary virtual space, when decodes the instruction code received any instruction of the move-first instruction and the move seconds instruction Only each
Decoding means for outputting a second logical value designating the instruction of (1), and memory access or transfer to source operand data as transfer source data as control information in a control memory for controlling a memory access request first logical that has a Oh <br/> operand designating means for outputting a third logic value indicating whether the memory access is a previous data to destination operand data, and is the output
Input logical value to third logical value and access target of transfer command
This is a configuration for identifying a virtual space to be used.

[0010]

[0011]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention.

The register 1 receiving the instruction code is:
A decoder 2 indicating a specific output state only when one of a move first instruction and a move second instruction is received, and a register 1 for only the first step of the instruction
Is connected to the selector 3 for selecting Decoder 2
Sets the output 21 to the logical value "1" upon receiving the move-first command, and inputs the logical value to the register 4. When the move / second command is received, the output 22 is set to the logical value “1”.
And input to the register 5. The selector 3 selects an input and transfers it to the control storage 6. The control memory 6 stores the selector 3
The content of the firmware for request control is read out to the register 7 on the basis of the information input by. The space designation switching circuit 8 receives an output of a register 9 for holding an access space designation flag for designating a virtual space to be accessed under the control of the central controller separately, an output of the registers 4 and 5,
A logical value of destination access, which is a part of the firmware content of the register 7, is received, a logical operation is performed, and a virtual space to be accessed is specified.

FIG. 2 is a circuit diagram of the space designation switching circuit.

The space designation switching circuit 8 receives the output 16 of the register 4, the output 17 of the register 5, the output 19 of the register 7, and the output 15 of the register 9, performs a logical operation, and performs a logical operation on the virtual space to be accessed. The designated space designation 18 is output.

As a function, if both the outputs 16 and 17 have the logical value “0”, the same logical value as the output 15 is assigned to the space designation 1.
8 and the outputs 16 and 19 are both logic value "1", or the output 17 is logic value "1" and the output 19 is logic value "0".
If so, the logical value “1” is output to the space specification 18, and the logical value “0” is output to the space specification 1 in other possible output combinations.
8 is output.

FIG. 3 is an explanatory diagram for explaining coding contents of the memory request control firmware of the present invention.

Source operand access (Step
In the control of A), the value of the destination access field is set to "0", and in the control of the destination operand access (Step B), the value of the destination access field is set to "1".

Next, execution of each instruction will be described. The description will be made mainly with reference to FIG. 1, and reference will be made to FIGS. 2 and 3 as necessary.

First, a case where a move command is received will be described.

The register 1 receives the move command and inputs the command to the decoder 2 and the selector 3. At this time, the output of the decoder 2 does not change, and the outputs 21 and 22 indicate the logical value “0”. The outputs 16 and 17 of the registers 4 and 5 receiving this indicate the logical value “0” in the same manner, so that the space specification 18 of the space specification switching circuit 8 contains the contents of the access space specification flag held by the register 9. Output. In this case,
The selector 3 reads the firmware for performing the request control in the first step of the move instruction,
6 and 17 indicate the logical value “0”, so that the value of the space designation 18 does not change regardless of the value of the output 19.

Next, a case where a move first instruction is received will be described.

The register 1 receives the move fast command and inputs the command to the decoder 2 and the selector 3. The decoder 2 receives the move-first command, sets the output 21 to the logical value “1”, and sets the logical value “1” in the register 4. The register 5 still shows the logical value "0". On the other hand, the selector 3 reads the source operand access (Step A), which is firmware, and inputs it to the register 7 in order to perform request control in the first step of the move first instruction. The register 7 outputs the value “0” of the destination access field as the value of the output 19. As a result, the output 16 of the register 4 is a logical value "1", the output 17 of the register 5 is a logical value "0", and the output 19 is a logical value "0". Sets the space designation 18 to the logical value "0"
To specify the primary virtual space. Next, when the control of the destination operand access (Step B) is started, the value "1" of the field of the destination access is output as the value of the output 19, so that the output 1 is output.
6 and 19 both have the logical value "1", and the space designation switching circuit 8 receiving these outputs sets the space designation 18 to the logical value "1" and designates the secondary virtual space.

Next, a case where a move / second command is received will be described.

The register 1 receives the move / second command and inputs it to the decoder 2 and the selector 3. Decoder 2
Receives the move second instruction, sets the output 22 to the logical value "1", and sets the logical value "1" in the register 5. Register 4 remains at logical value "0". On the other hand, the selector 3 performs the request control in the first step of the move / second instruction, so that the source
Operand access (Step A) is read and input to the register 7. Register 7 is the destination
The value “0” of the access field is output as the value of the output 19. As a result, the output 16 of the register 4 has the logical value “0”, the output 17 of the register 5 has the logical value “1”, and the output 1
Since 9 is a logical value “0”, the space designation switching circuit 8 receiving these outputs sets the space designation 18 to a logical value “1” and designates a secondary virtual space. Next, when the control of the destination operand access (Step B) is started, the value "1" of the field of the destination access is output as the value of the output 19, so that the space designation switching circuit 8 The value is set to “0” to designate the primary virtual space.

As described above, in the circuit of this embodiment, the request control of the move instruction, the move first instruction, and the move second instruction can be performed using the same firmware.

[0027]

As described above, the present invention provides a decoder which decodes an instruction code and shows a specific output state only when one of a move first instruction and a move second instruction is received, Specifies whether the memory access to the source operand data, which is the source data, or the destination operand data, which is the destination data, as the control information in the control memory for controlling the access request to the destination. In normal times, a virtual space to be accessed is specified in accordance with a move-first instruction and a move-second instruction, and upon receiving the output of the decoding means, the value of the field in the control storage and the output state of the decoding means are determined. Switching to specify the virtual space to be accessed according to the combination of By providing the road, advantageous effect is attained that it is possible to obtain that possible with the manufacturing takes the hassle economically advantageous circuit configuration sharing request control firmware for each instruction.

[Brief description of the drawings]

FIG. 1 is a block diagram of one embodiment of the present invention.

FIG. 2 is a circuit diagram of a space designation switching circuit.

FIG. 3 is an explanatory diagram for explaining coding contents of a memory request control firmware of the present invention.

FIG. 4 is an explanatory diagram for explaining coding contents of a conventional memory request control firmware.

[Explanation of symbols]

 1, 4, 5, 7, 9 register 2 decoder 3 selector 6 control storage 8 space designation switching circuit 15, 16, 17, 19 output 18 space designation

Claims (1)

(57) [Claims] 1. A primary virtual space specified by a primary virtual address converted by a first segment table and a secondary virtual space specified by a secondary virtual address converted by a second segment table are supported . Space designating means for outputting a first logical value designating whether the space to be accessed is the primary virtual space or the secondary virtual space, and the operand data is stored without depending on the space designating means. in information processing apparatus capable of executing the move seconds instruction for transferring the move-first instruction and operand data to transfer to the secondary virtual space from the primary virtual space from said secondary virtual space on the primary virtual space, an instruction code Decrypt the move first instruction and
A second logical value designating each of the move second instructions is output only when any of the move second instructions is received.
And decoding means for force, destination operand data is a memory access or transfer destination of the data to the source operand data is transferred original data as control information in a control memory to control access requests to the memory The third to specify whether memory access to
Includes a means to specify operands for outputting a logic value, the said
Input and transfer the output first to third logical values
An information processing apparatus for identifying a virtual space to be accessed by an instruction .