JPH02267951A - Manufacture of semiconductor substrate - Google Patents

Abstract

PURPOSE:To enhance the reliability as well as the yield by a method wherein, two each of wafers overlapped with each other are bonded to each other by pressurizing the same positions from both sides with equal pressure. CONSTITUTION:In the manufacture of a semiconductor substrate comprising two wafers 1, 11 bonded to each other, the two wafers 1, 11 overlapped with each other are bonded to each other by pressurizing the same positions from both sides with equal pressure. That is, due to the bonding process by pressurizing the same positions from both sides of the overlapped two wafers 1, 11 with equal pressure, any conventional warp can be almost avoided. Accordingly, the later formation of the semiconductor substrate can be performed easily while troubles such as bubbling, transposition, etc., on the bonding interface lcan be avoided without fail. Through these procedures, the reliability upon the semiconductor substrate can be enhanced, thereby enabling a device to be formed in high yield.

Description

[Detailed Description of the Invention] [Industrial Field of Application] The present invention relates to a method for manufacturing a semiconductor substrate, and particularly to a method for manufacturing a semiconductor substrate by bonding wafers together to form an SOI (Silicon-on-insulator).
or) relates to a method of manufacturing a substrate.

[Summary of the invention]

The present invention provides a method for manufacturing a semiconductor substrate by bonding two wafers together, in which after the two wafers are stacked,
By pressing and bonding the same points from both sides with the same pressure, we can almost eliminate warping that occurs during bonding, thereby increasing the reliability of the semiconductor substrate and increasing the yield of devices formed on the substrate. It is also designed to improve the

[Prior Art] Recently, progress has been made in the development of fabricating an ultra-LSI using a so-called Sol substrate formed by forming a thin single-crystal silicon layer on an insulator. Among the various SOI substrate manufacturing methods, the bonding method is considered to have the best crystallinity and excellent characteristics.

FIG. 9 shows an example of an SO2 board using the bonding method.

As shown in FIG. 9A, a plurality of convex portions (
A predetermined pattern of steps is formed so that 42) is formed. Then, an insulating film such as a SiO□ film (4
3), and furthermore, a layer for planarization, such as a polycrystalline silicon layer (44), is formed on the entire surface to fill in the steps, and the surface of this polycrystalline silicon layer (44) is polished to make it flat.

Next, as shown in FIG. 9B, a mirror silicon wafer (45) is separately bonded to the flattened polycrystalline silicon layer (44) to form a bonded wafer (47), and then as shown in FIG. 9C. Yo5iOJ'l! (Using 432 as a polishing stopper, polish from the back side of the silicon wafer (41),
To obtain a 301 substrate (48) having a plurality of island-shaped silicon thin films (46) separated by membranes (43).

In bonding the wafer (41) and wafer (45) shown in FIG. 9B above, conventionally, a bonding method as shown in FIGS. 10 and 11 is used.

That is, in the method shown in FIG. 10, for example, one wafer (41) is attached to a vacuum chuck (51) for holding the wafer 7 by vacuum suction while bending the wafer 7 in an upwardly convex shape.
Then, another wafer (45) in a non-deformed state is first placed in the middle of the other wafer (41).
), and then the vacuum chuck (51)
The vacuum suction of the two wafers (41) and (45) is weakened and the two wafers (41) and (45) are bonded together using their self-adsorption effect.

On the other hand, in the bonding method shown in FIG. 11, for example, one wafer (41) is placed on a flat plate (52), and then another wafer (45) is placed on top of one wafer (41). The two wafers (41) and (45) are bonded together by applying pressure to the center of the upper surface of another wafer (45).

(Problem to be Solved by the Invention) However, in the conventional semiconductor substrate manufacturing method, the bonded wafer (47) after bonding has a tolerance (2
Warpage of 0 .mu.m or more occurs, which poses an inconvenience in that it impedes the subsequent fabrication of SO2 substrates and also reduces the yield of devices formed on the substrates.

The reason for this is that in the case of the bonding method shown in Fig. 10, one wafer (41) is attached to the vacuum chuck (5
1) because it is forcibly kept in a state of deflection.
When one wafer (41) is bonded to another wafer (45), even if the suction is weakened, both wafers (41)
, (45) are laminated in a warped state. Therefore, when this bonded wafer (47) is removed from the vacuum chunk (51), as shown in the contour map of FIG. 12, the central part (47a) is almost flat, but the peripheral part (47b) is extremely flat. The bonded wafer is warped (maximum warpage 66.8 μm). That is, it can be seen that the contour line interval in the peripheral part (47b) is narrow and is lifted upward. Incidentally, the uniform cotton shown in FIG. 12 shows 2 μm per 1 scale.

On the other hand, in the case of the bonding method shown in FIG. 11, since pressure is applied to the center of the wafer (45) from one side, the peripheral portion lifts up, as shown in the contour diagram of FIG. Although the case shown in FIG. 12) is not extreme, the bonded wafer is still warped (maximum warpage 26.4 μm). That is, it can be seen that the center portion (47a) is raised upward continuously and stepwise toward the peripheral portion (47b).

Incidentally, the uniform cotton shown in FIG. 13 shows 1 μm per scale.

In addition, if warpage occurs in the bonded wafer (47), it is considered that a considerable amount of stress is applied to the bonded wafer (47), and this stress may cause bubbles or dislocations to occur at the bonded interface. However, it is also considered that this causes a decrease in the yield of devices formed on the substrate.

The present invention has been made in view of these points, and its purpose is to be able to almost eliminate warping that occurs during bonding, thereby increasing the reliability of semiconductor substrates and improving the reliability of semiconductor substrates formed on the substrates. An object of the present invention is to provide a method for manufacturing a semiconductor substrate that can achieve a high yield of devices.

[Means to solve the problem]

In the manufacturing method of the present invention, two wafers (1), (11
), in which the two wafers (1) and (11) are stacked, and then the same points are pressed with the same pressure from both sides to bond them together. .

[Effect]

According to the manufacturing method of the present invention described above, since the two stacked wafers (1) and (11) are bonded together by pressing the same points from both sides with the same pressure, it is possible to bond the two stacked wafers (1) and (11) together by pressing them with the same pressure from both sides. Nasori rarely occurs.

Therefore, there is no problem with the subsequent production of semiconductor substrates (for example, problems such as extremely uneven polishing or poor polishing accuracy during selective polishing will not occur), and there will be no air bubbles or other problems at the bonding interface. Since dislocations and the like do not occur, it is possible to improve the reliability of the semiconductor substrate (16) and to form devices at a high yield.

[Example] Hereinafter, the present invention will be described in detail with reference to FIGS. 1 to 8.

FIG. 1 is a process diagram showing a method for manufacturing a semiconductor substrate (hereinafter referred to as a Sol substrate) according to this embodiment. The steps will be explained step by step below.

First, as shown in FIG. 1A, a plurality of convex portions (2) with a thickness of 1000 mm are formed on the main surface of a silicon wafer (1) whose both sides are mirror-finished using photolithography. A predetermined pattern of steps is formed.

Next, as shown in FIG.
A Si0g film (3) is formed by VD (chemical vapor deposition), and using this Si0g film (3) as a buffer, a polycrystalline silicon layer (4) is further formed on this film to a thickness of 5 μm by CVD.
It accumulates to some extent.

Next, as shown in FIG. Layer (4)
Perform flattening polishing on the surface. This polishing process is performed by applying abrasive grains (for example, Ce0
z+ Alumina, etc.) (8) and soft materials (hot melt wax, paraffin, pitch, pine tar, bonding agent, etc.) (9)
) is applied to a thickness of several tens to several hundred micrometers using a polishing disk (10). At this time, water or a suspension of water mixed with abrasive grains is injected between the polishing disk (10) and the wafer (1) to be polished. In this polishing, only the pattern convex portions (5) that are 0 steps smaller than about 1000 are polished due to the so-called co-printing effect, and the polycrystalline silicon layer (4) is flattened. still,
The mirror surface has a surface roughness (average roughness) of 10 Å or less.

Next, as shown in the first diagram, another silicon wafer (
(11) is also bonded directly to the flattened polycrystalline silicon layer (4) to form a bonded wafer (12). Eggplant.

During this bonding process, both wafers (1) and (11) are cleaned with a mixture of ammonia and hydrogen peroxide to clean the surfaces of both wafers (1) and (11), and then spin Dry with a hair dryer. Next, bonding is performed in a clean atmosphere (for example, a class 100 atmosphere). This bonding method uses a jig (21) made of synthetic resin, for example Teflon, as shown in FIG.

This jig (21) has a V-shaped recess (23) formed by two tapered surfaces (22j, (22r)) in the center, and each tapered surface (221), (22r) (7)
Predetermined locations (for example, tapered surface (22j'), (22r
), when the wafers (1) and (11) are respectively placed on the wafers (1) and (11), the through-holes (241) extend laterally from the locations facing approximately the center of each wafer (1) and (11).
, (24r) and each through hole <241>.

Two pressure rods (251) inserted through (24r),
(25r). Then, the wafers (1) and (11) are placed on each tapered surface (22t and (22r)) with orientation flat surfaces (if) and (l
lf) facing down, then open the left and right through holes (24
1) Pressure rod (25l) inside (24r), (2
5r) respectively toward the recess (23), and further press each wafer (1), (II) in the upright direction with the same pressure. Both wafers (1) and (11) are overlapped by pressure from both sides using pressure rods (251') and (25r), and their adhesion begins from the same pressure point at the center, and after that, the bonding is based on OH groups. Both wafers (1) and (11) are self-adsorbed by hydrogen bonds.
is completely bonded.

After that, 1100″C9 in oxygen atmosphere or nitrogen atmosphere
Heat treatment is performed for 2 hours to give the laminated interface (2) a degree of adhesion comparable to that of the bulk. In addition, wafer (1), (
The tapered surfaces (221) and (22r) of 11) are propped up using a Teflon bottle set.
By providing the step portions (261), (26r) on the upper part of each tapered surface (221>,' (22r), it becomes very easy to lean it up with tweezers.

As the jig used for bonding the wafers (1) and (11), in addition to the jig (21) shown above, a Teflon jig (31) shown in FIG. 4 may be used. This jig (31) has a tapered surface (32) formed only on one side,
The cross section with a free space on the other side has a roughly L-shape. A projection (33) is located at the center of the tapered surface (32).
) is formed on the bottom (34), and the tapered surface (32) is formed on the bottom (34).
A tapered surface (35) is formed with a substantially right angle. When using this jig (31), first, for example, place one wafer (1) with the orientation flat surface (1f) down and place the tapered surface (32) on the protrusion (33).
After leaning the wafer along the
) is placed on one of the wafers (1), also with the orientation flat side (llf) facing down.

At this time, both wafers (1),
(11) are superimposed with high accuracy. After that, press the pressure rod (36) on the wafer (11) at a location corresponding to the protrusion (33).
) to bond both wafers (1) and (11) together.

The above example shows the orientation flat plane (If)
, (llf) side down wafer (1), (11)
5, the jig (31) shown in FIG. 4 is placed at a slight angle, as shown in FIG.
Furthermore, a bottle (37) is placed at a predetermined location on the periphery of the tapered surface (32).
Provide one. And wafer (1), (
11) its orientation flat plane (if)
, (llf) along the tapered surface (35) of the bottom (34) and slide it toward the pin (37). This mechanism can also be applied to the jig (21) shown in FIG.

Next, Fig. 1E (from this figure E onward, the above figure A-
As shown in (the arrangement is reversed from D), the peripheral edges (la) and (lla) of the bonded wafer (12) are chamfered. This chamfering is performed by first grinding the peripheral edge (1a) of one wafer (1) with a coarse grindstone, and then grinding the peripheral edge (lla) of the other wafer (11) at the interface <
p-) should be slightly removed. Thereafter, the damaged layer caused by the grindstone on the polished surface is removed by etching to remove machining distortion. At this time, an R (arc) (13) is formed on the other main surface side of one wafer (1).

Usually, as shown in Figure 6, the peripheral edge of the wafer has an arcuate cross section, so one wafer (1) in the post-process
When polishing is performed to the vicinity of the bonding interface (2), the peripheral edge (1a) of one wafer (1) is in a floating state relative to the other wafer (11), and that part ( 14) becomes an emergency Iz'C book< and becomes easy to miss. If this portion (14) is missing, it becomes a source of dust and dirt, leading to a decrease in the yield of device production. Therefore, by chamfering the bonded wafers (12) as described above, the above-mentioned disadvantages can be avoided.

After that, one wafer (1) is flattened from its end face (that is, selectively polished) to form a plurality of island-like silicon thin layers (15) separated from each other by SiO2 films (3), and the desired Sol A substrate (16) is obtained. As already mentioned above, the polishing disk used in this polishing process is the polishing disk (10) shown in FIG. The wafer (12
), that is, the surface on the silicon wafer (1) side, is pressed against the surface of the soft material (9) of the polishing disc (10), and the polishing disc (1
0) while rotating it. Note that at this time, polishing liquid is injected.

The polishing liquid used is an alkaline solution that chemically reacts with silicon but does not chemically react with 5i02. As a result, Figure 1 F
The entire wafer was polished flat as shown in
By stopping the polishing at the position where the surface of the film (3) is exposed, a flat island-shaped silicon thin layer (15 ) is formed. Further, in this polishing, since the soft abrasive grains (8) have a lower hardness than silicon or Sin, polishing can be performed without causing scratches or damage to the polished surface of the wafer. This makes it possible to fabricate a suitable Sol substrate.

As described above, according to this example, in the bonding process shown in the first diagram, both wafers (1) and (11) are first stacked using jig (21) or (31), and then both wafers ( 1) and (11), press the pressure rod (25j, (25r) or the pressure rod (25r) from both sides.
36), since the projections (33) are pressed with the same pressure to bond, as shown in the contour map in Figure 7, the bonding is done with almost no warping from the central portion (12a) to the peripheral portion (12b). A wafer (12) can be obtained (maximum warpage 3.7 In+). In addition, the uniform cotton shown in FIG. 7 shows 0.50 μm per scale. As a result, problems such as extreme polishing unevenness or poor polishing accuracy do not occur during subsequent selective polishing, and there is no problem in the subsequent production of SO2 substrates. In addition, no bubbles, dislocations, etc. occur at the bonding interface C1) due to warpage stress.

Therefore, it is possible to improve the reliability of the Sol substrate (16) and to form devices at a high yield.

In addition, the wafer (1) is placed in the jig (21) or (31).
(11) Orientation flat surface (if) when leaning.

Since (llf) is used, it is possible to superimpose both parts (1) and (11) with high accuracy.

In the above embodiment, the pressure point for both wafers (1) and (11) was set at approximately the center of both wafers (1) and (11), but this pressure point is not limited to this, but can also be applied to the edges. often,
It can be selected arbitrarily.

In addition, during selective polishing as shown in FIG.
10) was used, but a polishing plate with a hard pad (polyester nonwoven fabric impregnated with polyurethane, polyurethane porous sheet, etc.) attached to the polishing surface plate may also be used. In this case, an alkaline solution (for example, an aqueous solution of ethylenediamine or potassium hydroxide) is used as the polishing liquid, and the wafer (12) is further pressurized at 50°C.
Press at ~250g/Cra, and reduce the supply amount of polishing liquid to 5~1
By performing the process at 80 cc/min, an island-shaped silicon layer with a uniform thickness can be formed.

On the other hand, in the above example, when laminating as shown in the first diagram,
Both surfaces (1) and (11) are surface roughness (average roughness) 1
It was shown that a mirror surface with a thickness of 0 Å or less can be achieved. The basis for this is explained below.

Normally, the optimum surface roughness of silicon wafers used to create devices is generally Ra (average roughness) of 15.20.
It is said to be a person. This is because when bonding is performed using wafers with a surface roughness of 30 Å or more, the wafers may not be bonded together at all, or even if they are bonded, large air bubbles will be present at the bonding interface. Therefore, as mentioned above, it is said that if the surface roughness is Ra of 15 to 20, there will be almost no bubbles.

Therefore, we investigated the limit of surface roughness for mirror-finished wafers that would not cause bubbles.

First, samples (wafers) with various surface roughnesses are prepared using mechanical-chemical polishing methods, and these samples are passed through a cleaning process as a pretreatment for bonding. After that, the surface roughness of each sample is accurately measured using a surface roughness meter (resolution: 3 people) using a laser. Thereafter, samples having similar surface roughness were bonded together, and it was examined whether bubbles were generated at the bonded interface. In the bonding process, the surfaces were cleaned with a mixed solution of ammonia and hydrogen peroxide as in the case of this example, and then dried with a spin dryer to perform bonding in a clean atmosphere. And 1
The wafer was heat-treated in a nitrogen atmosphere at 100"C, and the presence or absence of bubbles was examined. As a result, the surface roughness of the wafer without bubbles was 10 Å or less in terms of Ra, as is clear from the characteristic diagram in Figure 8. I understand.

The characteristic diagram shown in Figure 8 shows the correlation between surface roughness and bubble generation rate, with the horizontal axis representing the wafer surface roughness (average roughness Ra) and the vertical axis representing the bubble generation rate. It is something.

The bubble generation rate is expressed by the following formula.Thus, in the above embodiment, the bonding method shown in FIGS. ) by setting the surface roughness of Ra to 10 Å or less, the synergistic effect of completely adhering (adsorbing) both wafers (1) and (11) without generating air bubbles at the bonding interface results in the subsequent Inconveniences such as uneven polishing and poor polishing accuracy during selective polishing are eliminated, and unexpected accidents such as sudden separation of the wafer during selective polishing or subsequent device fabrication are no longer caused, and the reliability of SOI substrates is improved. It is possible to more effectively improve the trajectory and increase the yield of devices.

〔Effect of the invention〕

A method for manufacturing a semiconductor substrate according to the present invention is a method for manufacturing a semiconductor substrate formed by bonding two wafers together.
After stacking two wafers, they are bonded by pressing the same points from both sides with the same pressure, which eliminates almost all the warping that occurs during bonding, which improves the reliability of semiconductor substrates and increases the It is possible to increase the yield of formed devices.

[Brief explanation of drawings]

FIG. 1 is a process diagram showing the method for manufacturing the Sol substrate according to this example, FIG. 2 is a configuration diagram showing an example of a polishing plate used for flattening, and FIG. FIG. 4 is a configuration diagram showing another example of the jig for explaining the bonding method, FIG. 5 is a configuration diagram showing another mechanism of the jig shown in FIG. 4, and FIG. The figure is an explanatory diagram showing the effect of chamfering, Figure 7 is a contour diagram showing the state of warpage in this example, Figure 8 is a characteristic diagram showing the correlation between surface roughness and bubble generation rate, and Figure 9 10 is a process diagram showing a method for manufacturing a Sol substrate according to a conventional example, FIG. 10 is a block diagram showing a bonding method according to a conventional example, and FIG. 11 is a block diagram showing another example of a bonding method according to a conventional example. , FIG. 12 is a contour diagram showing the warpage state when the method of FIG. 10 is used, and FIG. 13 is a contour diagram showing the warpage state when the method of FIG. 11 is used. (1) is silicon wafer, (3) is SiO□ film, (4
) is a polycrystalline silicon layer, (10) is a polishing plate, (11) is a silicon wafer, (12) is a bonded wafer, (15) is a
) is an island-like silicon thin layer, (16) is a Sol substrate, (21
) is the jig, (221>. (22r) is the tapered surface, (23) is the concave part, (251)
, (25r) is a pressure rod, (31) is a jig, (32) is a tapered surface, (33) is a protrusion, (35) is a tapered surface, (3
6) is a pressure rod, and (37) is a pin.

Claims (1)

[Claims] A method for manufacturing a semiconductor substrate by laminating two wafers, characterized in that after the two wafers are laminated, the same points are laminated from both sides with the same pressure. Substrate manufacturing method.