JP2604488B2 - Bonded wafer and manufacturing method thereof - Google Patents
Bonded wafer and manufacturing method thereofInfo
- Publication number
- JP2604488B2 JP2604488B2 JP2159301A JP15930190A JP2604488B2 JP 2604488 B2 JP2604488 B2 JP 2604488B2 JP 2159301 A JP2159301 A JP 2159301A JP 15930190 A JP15930190 A JP 15930190A JP 2604488 B2 JP2604488 B2 JP 2604488B2
- Authority
- JP
- Japan
- Prior art keywords
- wafer
- bonded
- bonded wafer
- element substrate
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Mechanical Treatment Of Semiconductor (AREA)
Description
【発明の詳細な説明】 〔概要〕 接合ウエハおよびその製造方法、特に高品質なシリコ
ン・オン・インシュレータ(Silicon on Insulator,SO
I)ウエハを得るためのSOIウエハの構造とその製造方法
に関し、 接合SOIの製造において、素子基板の端面に鋭角な段
差が生じることによる素子基板の欠けとゴミの発生、お
よび素子基板の割れを防止することができる構造のSOI
とそれの製造方法を提供することを目的とし、 複数枚のウエハを接合して構成する接合ウエハの両面
に位置する2枚のウエハのうち、素子形成用のウエハの
表面を研削して表面を平坦化すると共にウエハ厚を調整
し、その後、前記接合ウエハの端面を研削して該端面を
断面方向に連続した曲面を持つように仕上げ、さらに、
該端面を研磨することを特徴とする接合ウエハの製造方
法、および複数枚のウエハを接合して構成する接合ウエ
ハの両面に位置する2枚のウエハのうち、素子形成用の
ウエハの厚さが素子形成に適した厚さであり、かつ、該
素子形成用ウエハの表面が平坦化されていること、及
び、接合ウエハの端面が断面方向に連続した曲面を持つ
ように鏡面仕上げされていることを特徴とする接合ウエ
ハを含み構成する。DETAILED DESCRIPTION OF THE INVENTION [Summary] Bonded wafer and method for manufacturing the same, particularly high quality silicon on insulator (SO)
I) Regarding the structure of an SOI wafer for obtaining a wafer and its manufacturing method, in the manufacture of a bonded SOI, chipping of the element substrate, generation of dust, and cracking of the element substrate due to generation of an acute step on the end face of the element substrate SOI with a structure that can be prevented
And a method for manufacturing the same, by grinding the surface of an element forming wafer by grinding the surface of a wafer for forming an element among two wafers located on both surfaces of a bonded wafer formed by bonding a plurality of wafers. Flattening and adjusting the thickness of the wafer, and then grinding the end face of the bonded wafer to finish the end face to have a continuous curved surface in the cross-sectional direction,
The method for manufacturing a bonded wafer, characterized by polishing the end face, and, among the two wafers located on both sides of the bonded wafer formed by bonding a plurality of wafers, the thickness of the wafer for element formation is reduced. The thickness is suitable for element formation, and the surface of the element formation wafer is flattened, and the end face of the bonded wafer is mirror-finished so as to have a continuous curved surface in a cross-sectional direction. And a bonding wafer characterized by the following.
本発明は接合ウエハおよびその製造方法、特に高品質
なシリコン・オン・インシュレータウエハを得るための
SOIウエハの構造とその製造方法に関する。The present invention relates to a bonded wafer and a method for producing the same, particularly to obtain a high quality silicon-on-insulator wafer.
The present invention relates to a structure of an SOI wafer and a manufacturing method thereof.
近年の半導体の利用分野は拡大して増々高性能、高品
質なものが求められ、特に、高速化と耐環境化されたデ
バイスが要求されている。このため、SOI基板を用いた
デバイスが提供されているが、通常のシリコン基板(ウ
エハ)並みの結晶性が得られず、形成される素子の特性
や歩留りが良くないので、SOIウエハの結晶性を向上さ
せる方法が要請されている。In recent years, the fields of use of semiconductors have expanded, and high performance and high quality devices have been increasingly demanded. In particular, devices with high speed and environmental resistance have been demanded. For this reason, devices using SOI substrates have been provided, but the crystallinity of a normal silicon substrate (wafer) cannot be obtained, and the characteristics and yield of the formed elements are not good. There is a need for a way to improve this.
従来のSOIウエハにおいては、メルト法、SIMOX(Sepa
ration by Implanted Oxygen)法、そして接合法(貼合
わせ法)等が知られている。For conventional SOI wafers, the melt method, SIMOX (Sepa
A ration by Implanted Oxygen) method and a joining method (laminating method) are known.
しかし、メルト法、SIMOX法は、各れもその製造方法
の原理的な問題から、良質な結晶を得ることが極めて難
しいとされている。一方、接合法は、良質な結晶同志を
接着させるので、良質なSOI基板が得られるという利点
がある。However, it is said that it is extremely difficult to obtain good-quality crystals in each of the melt method and the SIMOX method due to the principle problem of the manufacturing method. On the other hand, the bonding method has an advantage that a good quality SOI substrate can be obtained because good quality crystals are bonded to each other.
多層LSI構造に有利なメルト法を第4図を参照にして
説明すると、第4図(a)の模式的な斜視図に示される
ように、表面にSiO2膜32が形成されたウエハ31の複数個
の島33を形成する。島33は図面の簡略化のため6個しか
示していないが、実際にはもっと多くの島がウエハ31全
面にわたって形成される。この島33に単結晶シリコン領
域を形成してデバイスを作るのである。Referring to FIG. 4, a melt method which is advantageous for the multilayer LSI structure will be described. As shown in a schematic perspective view of FIG. 4 (a), a wafer 31 having a SiO 2 film 32 formed on the surface thereof is formed. A plurality of islands 33 are formed. Although only six islands 33 are shown for simplicity of the drawing, more islands are actually formed over the entire surface of the wafer 31. A device is formed by forming a single crystal silicon region on the island 33.
第4図(b)は島33の部分の断面図で、SOIを作るた
めに、全面に多結晶シリコン(ポリシリコン)34を堆積
し、次いでレーザビームを照射してポリシリコンを溶融
すると、第4図(c)に示されるように、溶融されたポ
リシリコンは島33内に流れ込み、次いで再結晶化して単
結晶シリコン層36となる。FIG. 4 (b) is a cross-sectional view of a portion of the island 33. In order to form SOI, a polycrystalline silicon (polysilicon) 34 is deposited on the entire surface and then irradiated with a laser beam to melt the polysilicon. 4 As shown in FIG. 4 (c), the melted polysilicon flows into the island 33, and is then recrystallized into a single crystal silicon layer 36.
このメルト法においては、図に線で示す結晶欠陥37が
SiO2膜32から発生し、例えば島33が1cm□の大きさのも
のである場合、周辺から2.5mm程度は結晶欠陥が多く、
その結果島の寸法の約3/4において単結晶シリコン領域
を作ることができないという歩留り上の問題がある。In this melt method, a crystal defect 37 indicated by a line in the figure is formed.
Generated from the SiO 2 film 32, for example, when the island 33 has a size of 1 cm square, there are many crystal defects about 2.5 mm from the periphery,
As a result, there is a problem in yield that a single crystal silicon region cannot be formed in about 3/4 of the size of the island.
SIMOX法では、第5図を参照すると、先ず第5図
(a)に示されるように、シリコン基板(ウエハ)41に
酸素イオン(O+)を上から注入し、シリコン基板41の
深さのほぼ中央部分に打ち込んで酸素注入層42(図に短
い線を交叉させて示す)を形成する。In the SIMOX method, referring to FIG. 5, first, as shown in FIG. 5 (a), oxygen ions (O + ) are implanted into a silicon substrate (wafer) 41 from above, and the depth of the silicon substrate 41 is reduced. The oxygen implantation layer 42 (shown by crossing short lines in the figure) is formed by being implanted substantially at the center.
次いで、第5図(b)に示すように、1200〜1250℃の
アニールを行うと、酸素注入層はSiO2層43となって、そ
の上方にSOI44が作られる。Next, as shown in FIG. 5B, when annealing is performed at 1200 to 1250 ° C., the oxygen injection layer becomes the SiO 2 layer 43, and the SOI 44 is formed thereon.
しかし、この方法では、SOI44内に砂地で示すように
酸素45が残留し、シリコン中の酸素が結晶欠陥の原因と
なるので、SIMOX法で高品質なSOIを得ることは難しい。However, in this method, oxygen 45 remains in the SOI 44 as shown by sand, and oxygen in silicon causes crystal defects, so that it is difficult to obtain high-quality SOI by the SIMOX method.
そこで、接合SOIが開発されるに至ったもので、この
方法では、表面を酸化した素子基板(素子を形成する方
の基板)とそれの支持基板とを接着した後に、素子基板
の表面を研削し、次いで周辺をエッチングし、最後に研
磨する方法を行う。Therefore, the bonding SOI was developed. In this method, the surface of the element substrate was ground after bonding the element substrate (the substrate on which the element is formed) whose surface was oxidized to the supporting substrate. Then, the periphery is etched, and finally a polishing method is performed.
接合SOIを第6図を参照してやや詳細に説明すると、C
Z法で引上げた単結晶シリコンのCZ結晶51の表面には引
上げに際してCZ結晶51を回転させるので多数の筋52が形
成されている(第6図(a))。そこで、円筒加工によ
ってCZ結晶51表面の面取りを行って表面を均一に滑らか
にする(第6図(b))。次いで、オリエンテーション
・フラット(オリフラ加工)によって第6図(c)に示
すように、CZ結晶51の一側面を除去する。The junction SOI will be described in some detail with reference to FIG.
A large number of streaks 52 are formed on the surface of the single crystal silicon CZ crystal 51 pulled by the Z method because the CZ crystal 51 is rotated at the time of pulling (FIG. 6 (a)). Therefore, the surface of the CZ crystal 51 is chamfered by cylindrical processing to make the surface uniform and smooth (FIG. 6 (b)). Next, as shown in FIG. 6C, one side surface of the CZ crystal 51 is removed by orientation flat (orientation flat processing).
次に、スライシングによって第6図(d)に示される
ウエハ53(厚さ約0.1mm)を作り、それに面取りを行っ
て第6図(e)に示すように、ウエハ53の端面を丸く
し、次いでラッピングによって第6図(f)に示される
厚さ500〜700μmのウエハ53を作り、次いで研磨によっ
てウエハ53の表面をミラー表面にする。ウエハの端面を
面取りする理由は、ラッピングにおいて砥粒のまわり込
みを良くし砥粒の停滞を防止することに加え、でき上が
ったウエハの搬送、処理において、面取りしてないとほ
ぼ垂直な端面の形成する角がかけてゴミを生じたりウエ
ハが割れたりすることを回避するためである。Next, a wafer 53 (approximately 0.1 mm thick) shown in FIG. 6D is formed by slicing, and chamfering is performed to round the end surface of the wafer 53 as shown in FIG. 6E. Next, a wafer 53 having a thickness of 500 to 700 μm shown in FIG. 6 (f) is formed by lapping, and the surface of the wafer 53 is turned into a mirror surface by polishing. The reason for chamfering the end face of the wafer is that, in addition to improving the wrapping of the abrasive grains in lapping and preventing the stagnation of the abrasive grains, in the transfer and processing of the completed wafer, the formation of an almost vertical end face if not chamfered This is in order to avoid the generation of dust and cracking of the wafer.
次に、面取り加工したウエハ53の表面を酸化してSiO2
膜54を形成し、かかるウエハ53の2枚を第6図(g)に
示すように接着する。図において、上方のものは素子基
板53a、下方は支持基板53bであり、ウエハの大きさ、酸
化膜の膜厚は説明のため誇張して模式的に画いてある。
ウエハ53の表面はミラー表面(鏡面仕上げ)になってい
るので、素子基板53aと支持基板53bは室温で貼合わされ
る。次いで、1200℃のアニールによってSiO2膜54に取込
まれた空気に含まれる水分のうち水素を除去し、酸素と
シリコンの結合によって素子基板53aと支持基板53bを強
固に接合させる。Next, the surface of the chamfered wafer 53 is oxidized to form SiO 2
A film 54 is formed, and two such wafers 53 are bonded as shown in FIG. 6 (g). In the figure, the upper one is an element substrate 53a, the lower one is a support substrate 53b, and the size of the wafer and the thickness of the oxide film are exaggerated and schematically illustrated for the sake of explanation.
Since the surface of the wafer 53 is a mirror surface (mirror finish), the element substrate 53a and the support substrate 53b are bonded at room temperature. Next, hydrogen is removed from the moisture contained in the air taken into the SiO 2 film 54 by annealing at 1200 ° C., and the element substrate 53a and the support substrate 53b are firmly joined by bonding of oxygen and silicon.
次いで、ラッピングによって素子基板53aを上方から
研磨し、第6図(h)に示すように、SiO2膜54を含め0.
2〜10μm程度素子基板53a側を残す。そして、前記ラッ
ピングによって鏡面仕上げされた素子基板53aの表面上
に次のエッチングによってマスク材となるテープ55を貼
りつける。Then, by polishing the element substrate 53a from above by wrapping, as shown in FIG. 6 (h), 0 including an SiO 2 film 54.
The element substrate 53a side of about 2 to 10 μm is left. Then, a tape 55 serving as a mask material is attached by the next etching on the surface of the element substrate 53a which has been mirror-finished by the lapping.
続いてウエットエッチングによってテープ55でマスク
されない周辺部分をエッチングする(第6図(i))。
この時、接着面でのSiO2膜の厚さは0.1〜5μm程度と
なり、このSiO2膜がSOIのインシュレータである。Subsequently, the peripheral portion not masked by the tape 55 is etched by wet etching (FIG. 6 (i)).
At this time, the thickness of the SiO 2 film on the bonding surface is about 0.1 to 5 μm, and this SiO 2 film is an insulator for SOI.
第6図(i)に示す周辺エッチング後の素子基板53a
を観察すると、その端面はほぼ垂直になっていて鋭角な
段差が生じているので、上部の角の部分がウエハの洗浄
や搬送中に生じる振動によって他の物につき当たると角
の部分が欠け、場合によっては素子基板53aが割れるこ
とが経験された。The element substrate 53a after the peripheral etching shown in FIG.
When observing, the end surface is almost vertical and a sharp step is generated, so if the upper corner portion hits another object due to vibration generated during wafer cleaning or transfer, the corner portion is missing, In some cases, cracking of the element substrate 53a was experienced.
また、第6図(i)に示される素子基板53aのラッピ
ングにおいて、素子基板53aの側面は同図に点線で示す
接着面56に対して鋭角になっているために、その部分に
ラッピングに用いる砥粒がたまり、砥粒の流れが全般的
にみて均一でないので、ラッピングが均一行われず、ラ
ッピング仕上げ面が完全なミラー表面にならない問題も
経験された。In the lapping of the element substrate 53a shown in FIG. 6 (i), the side surface of the element substrate 53a is at an acute angle with respect to the bonding surface 56 shown by the dotted line in FIG. Since the abrasive grains accumulated and the flow of the abrasive grains was not uniform in general, there was also a problem that the lapping was not performed uniformly and the lapping finished surface did not become a perfect mirror surface.
そこで本発明は、接合SOIの製造において、素子基板
の端面に鋭角な段差が生じることによる素子基板の欠け
とゴミの発生、および素子基板の割れを防止することが
できる構造のSOIとそれの製造方法を提供することを目
的とする。Therefore, the present invention relates to an SOI having a structure capable of preventing chipping of an element substrate and generation of dust due to generation of an acute step on an end face of the element substrate, and cracking of the element substrate in the production of a bonded SOI and the production thereof. The aim is to provide a method.
本願請求項1記載の接合ウエハの製造方法は、図2に
その原理を示すように、複数枚(図では便宜的に2枚)
のウエハ11、12を接合して構成する接合ウエハ14の両面
に位置する2枚のウエハ11、12のうち、素子形成用のウ
エハ11の表面を研削して表面を平坦化すると共にウエハ
厚を調節し、その後、前記接合ウエハ14の端面を研削し
て該端面を断面方向に連続した曲面を持つように仕上
げ、さらに該端面を研磨することを特徴とする。As shown in FIG. 2, the method for manufacturing a bonded wafer according to claim 1 of the present application includes a plurality of wafers (two shown in FIG. 2 for convenience).
Of the two wafers 11 and 12 located on both sides of the bonded wafer 14 formed by bonding the wafers 11 and 12, the surface of the device forming wafer 11 is ground to flatten the surface and reduce the thickness of the wafer. After the adjustment, the end surface of the bonded wafer 14 is ground so that the end surface has a continuous curved surface in the cross-sectional direction, and the end surface is polished.
また、本願請求項2記載の接合ウエハの製造方法は、
請求項1記載のものにおいて、素子形成用のウエハの表
面を平坦化すると共に該ウエハ厚を調節する際に、研磨
または研削及び研磨を行うことを特徴とする。The method for manufacturing a bonded wafer according to claim 2 of the present application is
The method according to claim 1, wherein polishing or grinding and polishing are performed when the surface of the wafer for element formation is flattened and the thickness of the wafer is adjusted.
また、本願請求項3記載の接合ウエハの製造方法は、
請求項1記載のものにおいて、接合ウエハの端面を研削
後、素子形成用のウエハの表面を研磨することを特徴と
する。Also, the method for manufacturing a bonded wafer according to claim 3 of the present application is as follows.
The method according to claim 1, wherein after grinding the end surface of the bonded wafer, the surface of the wafer for element formation is polished.
本願請求項4記載の接合ウエハは、複数枚のウエハを
接合して構成する接合ウエハの両面に位置する2枚のウ
エハのうち、素子形成用のウエハの厚さが素子形成に適
した厚さであり、かつ、該素子形成用のウエハの表面が
平坦化されていること、及び、接合ウエハの端面が断面
方向に連続した曲面を持つように鏡面仕上げられている
ことを特徴とする。The bonded wafer according to claim 4 of the present application is such that, of the two wafers located on both surfaces of the bonded wafer formed by bonding a plurality of wafers, the thickness of the wafer for element formation is a thickness suitable for element formation. In addition, the surface of the element forming wafer is flattened, and the end surface of the bonded wafer is mirror-finished so as to have a continuous curved surface in a cross-sectional direction.
第2図は本発明の原理図で、先ず、第2図(a)に示
すように、素子を形成すべき基板(以下、素子基板とい
う)11と素子基板11を支持すべき基板(以下、支持基板
という)12とを接着して接合ウエハ14を作る。次いで、
第2図(b)に示すように、素子基板11を研削し研磨す
る。続いて、第2図(c)に示すように、接合ウエハ14
の端面を面取りする。さらに、図中には示されていない
が、面取りした接合ウエハ14の端面を研磨する。なお、
接合ウエハの端面を研削後に、素子基板11の表面を研磨
する場合であってもよい。FIG. 2 is a diagram showing the principle of the present invention. First, as shown in FIG. 2 (a), a substrate 11 on which an element is to be formed (hereinafter referred to as an element substrate) and a substrate 11 on which the element substrate 11 is to be supported (hereinafter referred to as A bonding wafer 14 is formed by bonding the supporting wafer 12 and a supporting substrate 12. Then
As shown in FIG. 2B, the element substrate 11 is ground and polished. Subsequently, as shown in FIG.
Chamfer the end face of. Further, although not shown in the drawing, the chamfered end surface of the bonded wafer 14 is polished. In addition,
The surface of the element substrate 11 may be polished after grinding the end surface of the bonded wafer.
すなわち本発明によると、接合した素子基板11と支持
基板12(接合ウエハ14)の端面の形成する不連続面を断
面方向に連続した曲面を持つように仕上げられており、
角ばった部分がどこにもないので、この接合SOIの洗
浄、搬送中の振動によって端面が他の物に接触したとし
ても欠けたり割れたりすることが防止され、さらに、接
合ウエハの裏面以外の全ての面を研削又は研磨仕上げす
るため、異物の発生がほとんどないので、素子基板の表
面が精度の高いミラー表面として保持されるのである。That is, according to the present invention, the discontinuous surfaces formed by the end faces of the bonded element substrate 11 and the supporting substrate 12 (bonded wafer 14) are finished to have a continuous curved surface in the cross-sectional direction,
Since there is no angular part anywhere, this bonded SOI is prevented from being chipped or cracked even if the end surface comes in contact with other objects due to vibration during cleaning and transport, and all other than the back surface of the bonded wafer Since the surface is ground or polished, there is almost no generation of foreign matter, so that the surface of the element substrate is held as a highly accurate mirror surface.
以下、本発明を図示の実施例により具体的に説明す
る。Hereinafter, the present invention will be specifically described with reference to the illustrated embodiments.
本発明の実施例は、第1図(a)〜(c)に示すよう
に、接合ウエハ14の素子基板11(発明の要旨に記載の素
子基板用のウエハに相当)を研削および研磨(この研磨
は、次の面取り後に行ってもよい)した後、端面研削処
理による面取りを行い、さらに図示されていないが、接
合ウエハ14の端面を研磨する。これらの図において、説
明のためウエハの大きさ、酸化膜の膜厚は誇張して模式
的に示される。素子基板11と支持基板12はそれぞれ端面
が面取りされ、それぞれの表面には、形成される素子の
種類によって定められる膜厚のSiO2膜13が形成されてい
る。一般に2つのSiO2膜13を合わせたその膜厚は0.1〜
5.0μmの範囲内に設定される。これらの基板は、従来
例の場合と同様に先ず室温で機械的に接着され、次いで
1200℃のアニールを行い、SiO2膜13中に取込まれた水分
のうち水素を除去し、酸素とシリコンの結合によって強
固に接合されて接合ウエハ14を構成する。この状態で2
枚の基板によって形成される端面は不連続面となってい
る(第1図(a))。In the embodiment of the present invention, as shown in FIGS. 1 (a) to 1 (c), the element substrate 11 (corresponding to the element substrate wafer described in the gist of the invention) of the bonded wafer 14 is ground and polished. After polishing, the polishing may be performed after the next chamfering.) Then, chamfering is performed by an end surface grinding process, and although not shown, the end surface of the bonded wafer 14 is polished. In these drawings, the size of the wafer and the thickness of the oxide film are schematically shown exaggeratedly for the sake of explanation. The end surfaces of the element substrate 11 and the support substrate 12 are chamfered, and an SiO 2 film 13 having a thickness determined by the type of the element to be formed is formed on each surface. Generally, the total thickness of the two SiO 2 films 13 is 0.1 to
It is set within the range of 5.0 μm. These substrates are first mechanically bonded at room temperature as in the prior art, and then
Annealing at 1200 ° C. is performed to remove hydrogen from the moisture taken in the SiO 2 film 13, and the bonded wafer 14 is firmly bonded by bonding of oxygen and silicon. In this state 2
The end face formed by the two substrates is a discontinuous face (FIG. 1A).
次いで、第1図(b)に示すように、素子基板11の研
削と研磨(ラッピング)を行う。なお、研削には、例え
ばダイヤモンド砥石を用いてもよい。また、研磨には、
例えばアミン系水溶液とコロイダルミリカを研磨剤とし
て研磨面に供給し、研磨布(ポリエステル不織布等)で
磨いてもよい。Next, as shown in FIG. 1B, grinding and polishing (lapping) of the element substrate 11 are performed. For grinding, for example, a diamond grindstone may be used. Also, for polishing,
For example, an amine-based aqueous solution and colloidal milica may be supplied to a polishing surface as an abrasive and polished with a polishing cloth (a polyester nonwoven fabric or the like).
次に、第1図(c)に示すように、2枚の基板の接合
ウエハ14の端面の面取りを端面研削処理により行う。こ
れにより、不連続な面であった端面を連続した丸みを持
ち、かつ基板の面取形状が表裏面で対称となる曲面をも
つ完全に面取りされた状態に仕上げる。Next, as shown in FIG. 1 (c), the end surfaces of the bonded wafer 14 of the two substrates are chamfered by an end surface grinding process. As a result, the end face, which was a discontinuous face, is finished into a completely chamfered state having a continuous roundness and a curved surface in which the chamfered shape of the substrate is symmetrical on the front and back surfaces.
次に、図示されていないが、第1図(c)の面取り
後、接合ウエハ14の端面を研磨する。Next, although not shown, after chamfering in FIG. 1 (c), the end face of the bonded wafer 14 is polished.
このように本実施例では、接合ウエハ14の端面が断面
方向に連続した曲面を持つように仕上げられており、角
ばった部分がどこにもないので、洗浄や搬送中に振動が
生じたり取り扱い上の不注意があっても、欠けや割れを
生じるおそれがなくなる。さらに、接合ウエハ14の裏面
以外の全ての面を研削又は研磨仕上げするため、異物の
発生がほとんどなく、しかも、素子基板11の表面精度を
保持できるので、素子欠陥やパターン不良の発生を大幅
に抑制できる。As described above, in the present embodiment, the end surface of the bonded wafer 14 is finished so as to have a continuous curved surface in the cross-sectional direction, and there is no angular portion. Even if careless, there is no risk of chipping or cracking. Furthermore, since all surfaces except the back surface of the bonded wafer 14 are ground or polished, there is almost no generation of foreign matter, and the surface accuracy of the element substrate 11 can be maintained. Can be suppressed.
なお、他の変形例として、この端面研削処理後、更に
接合ウエハの素子基板11の表面を研磨してミラー面にす
る場合であってもよい。As another modified example, the surface of the element substrate 11 of the bonded wafer may be further polished to a mirror surface after the end surface grinding processing.
なお、接合ウエハ14の不連続な端面の面取りを行うに
は、第3図に示される周知のグランイダーを用い、チャ
ック21で保持した接合ウエハ14の端面をグラインダーの
グラインド面22に当て、次いでアーム23でチャック21を
矢印方向に動かして端面を研削する。アーム23は図示し
ていない駆動源に連結され、この駆動源はアーム23を自
動的に操作するようになっていて、面取り作業は機械的
に自動化して進められる。In order to chamfer the discontinuous end face of the bonded wafer 14, a known grinder shown in FIG. 3 is used to bring the end face of the bonded wafer 14 held by the chuck 21 into contact with the grind surface 22 of the grinder, and then the arm At 23, the chuck 21 is moved in the direction of the arrow to grind the end face. The arm 23 is connected to a drive source (not shown). The drive source automatically operates the arm 23, and the chamfering operation is mechanically automated.
本発明では、接合ウエハの端面が断面方向に連続した
曲面を持つように仕上げられており、角ばった部分がど
こにもないので、洗浄や搬送中に振動が生じたり取り扱
い上の不注意があっても、欠けや割れを生じるおそれが
ない、という独自な効果が得られるうえ、さらに、接合
ウエハの裏面以外の全ての面を研削又は研磨仕上げする
ため、異物の発生がほとんどなく、しかも、素子形成用
ウエハの表面を高精度に保持できるため、素子欠陥やパ
ターン不良の発生を大幅に抑制できる、という独自な効
果が得られる。In the present invention, the end surface of the bonded wafer is finished so as to have a continuous curved surface in the cross-sectional direction, and since there is no angular portion anywhere, vibration occurs during cleaning or transport and careless handling is caused. In addition, the unique effect that there is no risk of chipping or cracking is obtained, and further, since all surfaces except the back surface of the bonded wafer are ground or polished, there is almost no generation of foreign matter, and furthermore, element formation Since the surface of the wafer for use can be held with high precision, the unique effect that the occurrence of element defects and pattern defects can be significantly suppressed can be obtained.
第1図(a)〜(c)は本発明実施例の断面図、 第2図は本発明の原理を説明する断面図、 第3図は面取り工程を示す図、 第4図はメルト法を示す図で、その(a)は斜視図、そ
の(b)と(c)は断面図、 第5図はSIMOX法を示す断面図、 第6図は接合SOI法を示す図で、その(a)はCZ結晶の
正面図、(b)はCZ結晶の円筒加工後の正面図、(c)
はCZ結晶のオリフラ加工後の正面図、(d)〜(f)は
ウエハの斜視図、その(g)〜(i)は接合ウエハの断
面図である。 11……素子基板(素子形成用の基板)、12……支持基板
(素子基板を支持すべき基板)、13……SiO2膜、14……
接合ウエハ、15……接着面、21……チャック、22……グ
ラインド面、23……アーム、51……CZ結晶、52……筋、
53……ウエハ、53a……素子基板、53b……支持基板、54
……SiO2膜、55……テープ、56……接着面。1 (a) to 1 (c) are cross-sectional views of an embodiment of the present invention, FIG. 2 is a cross-sectional view for explaining the principle of the present invention, FIG. 3 is a view showing a chamfering step, and FIG. 5A is a perspective view, FIGS. 5B and 5C are cross-sectional views, FIG. 5 is a cross-sectional view showing a SIMOX method, and FIG. 6 is a view showing a junction SOI method. ) Is a front view of the CZ crystal, (b) is a front view after the cylindrical processing of the CZ crystal, (c)
1 is a front view of a CZ crystal after orientation flat processing, (d) to (f) are perspective views of a wafer, and (g) to (i) are cross-sectional views of a bonded wafer. 11 (substrate for device formation) ...... element substrate, 12 ... supporting substrate (substrate should support element substrate), 13 ... SiO 2 film, 14 ...
Bonded wafer, 15 Adhesive surface, 21 Chuck, 22 Grind surface, 23 Arm, 51 CZ crystal, 52 Streaks
53 …… Wafer, 53a …… Element substrate, 53b …… Support substrate, 54
...... SiO 2 film, 55 ...... tape, 56 ...... adhesive surface.
Claims (4)
エハの両面に位置する2枚のウエハのうち、素子形成用
のウエハの表面を研削して表面を平坦化すると共にウエ
ハ厚を調節し、その後、前記接合ウエハの端面を研削し
て該端面を断面方向に連続した曲面を持つように仕上
げ、さらに、該端面を研磨することを特徴とする接合ウ
エハの製造方法。1. A wafer for element formation, of two wafers located on both sides of a bonded wafer formed by bonding a plurality of wafers, is planarized by grinding the surface and adjusting the thickness of the wafer. Then, an end surface of the bonded wafer is ground to finish the end surface to have a continuous curved surface in a cross-sectional direction, and further, the end surface is polished.
共に該ウエハ厚を調節する際に、研磨または研削及び研
磨を行うことを特徴とする請求項1記載の接合ウエハの
製造方法。2. The method for manufacturing a bonded wafer according to claim 1, wherein polishing or grinding and polishing are performed when the surface of the wafer for element formation is flattened and the thickness of the wafer is adjusted.
ウエハの表面を研磨することを特徴とする請求項1記載
の接合ウエハの製造方法。3. The method for manufacturing a bonded wafer according to claim 1, wherein after grinding the end surface of the bonded wafer, the surface of the wafer for forming an element is polished.
エハの両面に位置する2枚のウエハのうち、素子形成用
のウエハの厚さが素子形成に適した厚さであり、かつ、
該素子形成用ウエハの表面が平坦化されていること、及
び、接合ウエハの端面が断面方向に連続した曲面を持つ
ように鏡面仕上げされていることを特徴とする接合ウエ
ハ。4. A wafer for element formation among two wafers located on both sides of a bonded wafer formed by bonding a plurality of wafers, the thickness of which is suitable for element formation, and
A bonded wafer characterized in that the surface of the element forming wafer is flattened, and the end surface of the bonded wafer is mirror-finished so as to have a continuous curved surface in a cross-sectional direction.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2159301A JP2604488B2 (en) | 1989-06-21 | 1990-06-18 | Bonded wafer and manufacturing method thereof |
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15690289 | 1989-06-21 | ||
JP1-156902 | 1989-06-21 | ||
JP2159301A JP2604488B2 (en) | 1989-06-21 | 1990-06-18 | Bonded wafer and manufacturing method thereof |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH0387012A JPH0387012A (en) | 1991-04-11 |
JP2604488B2 true JP2604488B2 (en) | 1997-04-30 |
Family
ID=26484528
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2159301A Expired - Fee Related JP2604488B2 (en) | 1989-06-21 | 1990-06-18 | Bonded wafer and manufacturing method thereof |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2604488B2 (en) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1170801B1 (en) * | 1999-10-14 | 2006-07-26 | Shin-Etsu Handotai Company Limited | Bonded wafer producing method |
JP4304879B2 (en) | 2001-04-06 | 2009-07-29 | 信越半導体株式会社 | Method for determining the implantation amount of hydrogen ions or rare gas ions |
WO2004008527A1 (en) * | 2002-07-17 | 2004-01-22 | S.O.I.Tec Silicon On Insulator Technologies | A method of increasing the area of a useful layer of material transferred onto a support |
JP5953705B2 (en) * | 2011-11-02 | 2016-07-20 | トヨタ自動車株式会社 | SOI wafer and method for manufacturing SOI wafer |
JP6699515B2 (en) * | 2016-11-07 | 2020-05-27 | 株式会社デンソー | Semiconductor wafer and manufacturing method thereof |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61256621A (en) * | 1985-05-08 | 1986-11-14 | Toshiba Corp | Production of bound-type semiconductor substrate |
JPS6471655A (en) * | 1987-09-11 | 1989-03-16 | Nippon Denso Co | Semiconductor substrate |
-
1990
- 1990-06-18 JP JP2159301A patent/JP2604488B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JPH0387012A (en) | 1991-04-11 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP3169120B2 (en) | Method for manufacturing semiconductor mirror-surface wafer | |
EP0854500B1 (en) | Method of manufacturing a bonded substrate | |
JPS62154614A (en) | Method for manufacturing a bonded semiconductor substrate | |
JPH0376118A (en) | Manufacture of substrate for semiconductor element formation | |
JPH01312828A (en) | Manufacture of semiconductor | |
JP3328193B2 (en) | Method for manufacturing semiconductor wafer | |
US20030060020A1 (en) | Method and apparatus for finishing substrates for wafer to wafer bonding | |
JP5233111B2 (en) | Manufacturing method of bonded SOI wafer | |
JP2662495B2 (en) | Method for manufacturing bonded semiconductor substrate | |
JP3352129B2 (en) | Semiconductor substrate manufacturing method | |
JP2604488B2 (en) | Bonded wafer and manufacturing method thereof | |
JPH05226305A (en) | Manufacture of laminated wafer | |
JPH08274285A (en) | Soi substrate and manufacture thereof | |
JPH0897111A (en) | Method for manufacturing soi substrate | |
JPH10209408A (en) | Manufacture of soi substrate | |
JPH02267950A (en) | Semiconductor substrate | |
JPH044742B2 (en) | ||
JPH04226031A (en) | Method of manufacturing a semiconductor wafer and method of manufacturing a semiconductor device comprising the wafer | |
JP2002176013A (en) | Semiconductor substrate planarization method | |
JPH02267949A (en) | Manufacture of semiconductor substrate | |
JP2890450B2 (en) | Polishing method | |
JPH09213593A (en) | Adhesive substrate and manufacturing method thereof | |
JP2024171189A (en) | Multilayer SOI wafer manufacturing method and multilayer SOI wafer | |
JPH04243132A (en) | Semiconductor substrate and manufacture thereof | |
JP2004319910A (en) | Method for manufacturing semiconductor wafer |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
LAPS | Cancellation because of no payment of annual fees |