JPH02266568A - Mos transistor - Google Patents

Abstract

PURPOSE:To control avalanche breakdown of both high impurities concentration region and to enable high power supply voltage to be applied to by forming high impurities concentration region of source/drain so that it may not contact the isolation region of high impurities concentration. CONSTITUTION:A MOS type transistor is configured so that a high impurities concentration region 3 of source/drain may not contact an isolation region 2 of high impurities concentration. Thus, the source/drain region 3 is formed being away from the isolation region 2. Therefore, since both high concentration impurities region do not contact each other, a depletion layer is formed at a region between the high concentration regions to relax electric field even if a high voltage is applied to the drain region, thus controlling occurrence of avalanche breakdown.

Description

DETAILED DESCRIPTION OF THE INVENTION FIELD OF INDUSTRIAL APPLICATION The present invention relates to a MOS type transistor of a semiconductor integrated circuit.

BACKGROUND OF THE INVENTION In recent years, MOS transistors have become increasingly finer due to advances in manufacturing equipment and processing technology, leading to higher density and higher integration of semiconductor integrated circuits.

A conventional MOS transistor will be explained below.

FIG. 4 is a sectional view of a main part of a conventional N-channel MOS transistor. ■ is a P-type semiconductor substrate, 2 is a semiconductor substrate 1
3 is a P-type isolation region with a higher impurity concentration than the source, and 3 is a hole-concentration N-type impurity region (hereinafter referred to as source) that constitutes the source and drain.
(referred to as drain region), 4 is LDD (Light
ly Doped drain), 5 is a gate, and 6 is a gate insulator.

The operation of the MO8 type transistor configured as described above will be explained below. With the semiconductor substrate 1 as a reference voltage, the voltage of the source region (hereinafter referred to as Vs) to which the lower voltage of the source and drain regions 3 is applied to the gate 5.
By applying a voltage equal to or higher than the sum of the threshold voltage (hereinafter referred to as vth) of the MO3 type transistor, a current can flow from the drain region to the source region. gate 5
．． If the voltage is below vi+vth, no current will flow. Using this operation, semiconductor integrated circuits with various operations can be realized using MO3 type transistors.

Problems to be Solved by the Invention When miniaturizing such a conventional MO8 type transistor, the impurity concentration of the isolation region 2 that isolates adjacent transistors is increased, and the depletion layer is connected between adjacent transistors, resulting in a current flow. It is necessary to suppress the so-called bunch-through current that flows.

The width W of the depletion layer in a stepped junction is as follows. Here, KSi: relative permittivity of silicon Eo: permittivity of vacuum q: charge of electrons ND: concentration of N-type impurities constituting the source and drain N^: amount of P i! ! In the impurity concentration of the region: Built-in voltage V: Voltage between source, drain and P-type isolation region Ns: P
It can be seen that the width of the depletion layer can be narrowed by increasing the concentration of the type separation region. On the other hand, the maximum electric field EMAX in the depletion layer increases, and so-called avalanche breakdown tends to occur (this causes a problem in that the withstand voltage of the source and drain decreases).

Furthermore, in semiconductor integrated circuits that incorporate a booster circuit that generates a voltage higher than the power supply voltage, punch-through can be prevented by increasing the distance between adjacent transistors, but avalanche breakdown in the source, drain and isolation regions cannot be prevented. There was also the problem that the boosted voltage was not generated as designed.

These issues also apply to P-channel MO8 type transistors.
This is a similar problem even if the MO8 type transistor is formed not in the semiconductor substrate 1 but in a well.

Means for Solving the Problems In order to achieve this object, the MO3 type transistor of the present invention has a structure in which the high impurity concentration regions of the source and drain do not contact the #@ region of high impurity concentration.

Effect This configuration allows the highly impurity regions of the source and drain to
Similarly, since it does not contact the isolation region with high impurity concentration, even if a high voltage is applied to the drain region, a depletion layer is formed between the high concentration regions, relaxing the electric field and suppressing the occurrence of avalanche breakdown. can do.

EXAMPLE Hereinafter, an example of the present invention will be described with reference to five drawings.

FIG. 1 shows an N-channel MO in the first embodiment of the present invention.
FIG. 5 is a cross-sectional view of a main part of a type 5 transistor. 1st
In the figure, 1 is a P-type semiconductor substrate, 2 is a P-portion i11 region with a higher impurity concentration than the semiconductor substrate 1, and 3 is a high-concentration N-type impurity region constituting the source and drain (hereinafter referred to as source).
(referred to as drain region), 4 is LDD (Lightly
5 is a gate, and 6 is a gate insulator.

The operation of the MO3 type transistor configured as described above is similar to that of the conventional MO3 type transistor, but by forming the source and drain regions 3 apart from the two isolation regions, the high concentration impurity regions can be separated from each other. Since they are not in contact with each other, even if a high voltage is applied to the drain region, a depletion layer is formed in the region between the high concentration regions, which alleviates the electric field and suppresses the occurrence of avalanche breakdown.

When forming the source and drain regions 3, we take care not to overlap the isolation region 2 during impurity diffusion or impurity ion implantation, and take into account lateral diffusion during impurity diffusion or post-implantation heat treatment. A window of a resist mask used for impurity diffusion or impurity ion implantation is set apart from the second isolation region.

FIG. 2 shows an N-channel MO in a second embodiment of the present invention.
1 is a cross-sectional view of a main part of an S-type transistor. Second
In the figure, 1 is a P-type semiconductor substrate, 2 is a P-type isolation region with a higher impurity concentration than the semiconductor substrate 1, 7 is a high-concentration N-type impurity region forming the drain, and 8 is a high-concentration N-type impurity region forming the source. , 4 is an N-type impurity concentration region having a lower impurity concentration than 7 and 8 constituting the LDD, 5 is a gate, and 6 is a gate insulator.

The difference from the configuration shown in FIG. 1 is that only the drain region 7 to which a high voltage is applied between the semiconductor substrate 1 and the isolation region 2 is formed apart from the isolation region 2.

Only the drain region to which a high voltage is applied is formed apart from the isolation region 2 to suppress the occurrence of avalanche breakdown, and the source region 8 is formed by a conventional method. This eliminates the need for the area required to separate the MOS transistors, suppresses an increase in the surface area of the MOS transistor, and is more suitable for higher density than the first embodiment.

FIG. 3 shows an N-channel MO in the third embodiment of the present invention.
1 is a cross-sectional view of a main part of an S-type transistor. Third
In the figure, 1 is a P-type semiconductor substrate, 2 is a P-type isolation region with a higher impurity concentration than the semiconductor substrate 1, 9 is a high-concentration N-type impurity region to which a voltage higher than the power supply voltage is applied from the booster circuit, ]O 4 is a high concentration N-type impurity region to which a voltage lower than the power supply voltage is applied, and 4 is a region 9 and 10 constituting the LDD.
5 is a gate, and 6 is a gate insulator.

The difference from the configurations in FIGS. 1 and 2 is that in a semiconductor integrated circuit incorporating a booster circuit, only the high concentration N-type impurity region 9 to which a voltage higher than the power supply voltage is applied is formed separately from the isolation region 2. There are many things.

With this configuration, the MOS transistor to which only a voltage lower than the power supply voltage is applied and the high-1 degree N-type impurity region are formed using conventional methods, so avalanche breakdown in the region to which the boosted voltage is applied can be prevented. It is possible to realize a high-density, highly integrated semiconductor integrated circuit while suppressing the amount of noise.

Although the above embodiments have been explained using LDD type MOS transistors, similar effects can be obtained even if the transistors do not have an LDD structure.

Further, although the above embodiment has been explained using an N-channel MOS type transistor, it goes without saying that similar effects can be obtained using a P-channel MO8 type transistor.

Further, in the above embodiment, 1 is a semiconductor substrate, but it may be a well formed on a semiconductor substrate.

Effects of the Invention As described above, the present invention suppresses avalanche breakdown in the high impurity concentration regions by forming the high impurity concentration regions of the source and drain so as not to contact the high impurity concentration isolation regions. Therefore, it is possible to realize an excellent MOS type transistor that can be used as a semiconductor integrated circuit to which a high power supply voltage can be applied.

[Brief explanation of drawings]

FIG. 1 shows an N-channel MO in the first embodiment of the present invention.
FIG. 2 is a cross-sectional view of the main parts of an S-type transistor, which is the second embodiment of the present invention.
FIG. 3 is a cross-sectional view of a main part of an N-channel MOS transistor according to a third embodiment of the present invention, and FIG. 4 is a cross-sectional view of a main part of an N-channel MOS transistor according to a third embodiment of the present invention. FIG. ■...P' type semiconductor substrate, 2...P type isolation region, 3.7.8.9.10...High concentration N
type impurity region, 4...LDD (Lightl
y Doped Drain) configuration 1--P pear semiconductor main board 4-N S! No S! , Mg area 5--Gate 6--Kate earth object 9.10-High prefecture N-made non-phrase area

Claims (3)

[Claims] (1) A high impurity concentration region of a conductivity type opposite to that of the semiconductor substrate or well constituting the source and drain regions is isolated from an isolation region of the same conductivity type as the substrate or well and of a higher impurity concentration than the substrate or well. A MOS transistor characterized by: (2) A high voltage is applied to two high impurity concentration regions of the source and drain, which are formed in a semiconductor substrate or well and have a conductivity type opposite to that of the semiconductor substrate or well, with the semiconductor substrate or well as a reference. A MOS type transistor characterized in that a high impurity concentration region on the other side is isolated from an isolation region having the same conductivity type as the substrate or well and having a higher impurity concentration than the substrate or well. (3) A high impurity concentration region of the opposite conductivity type to the semiconductor substrate or well constituting the source or drain region to which a voltage boosted than the power supply voltage is applied is of the same conductivity type as the substrate or well, and A MOS transistor characterized by being isolated from an isolation region with a higher impurity concentration.