JPH02251890A - Circuit and system for dot clock switching control - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a frequency switching control circuit for dot clocks corresponding to each display in a display device that controls a plurality of displays.

(Prior Art) Due to the wide variety of display displays, in one CPU system, multiple display displays, such as CR
Two displays, a T display and a liquid crystal display, are connected and the display between the CRT display and the liquid crystal display is switched depending on the purpose.

A conventional device is as described in Japanese Patent Laid-Open No. 60-250396. Its configuration and operation will be explained using FIG. 2. As shown in FIG. 2, a plurality of display displays 1
5.16, a dedicated display controller 12.13 is provided for each display. The dot clock signal that serves as the reference clock is
A signal with a frequency corresponding to each display is input to each display controller 12, 13. In this case, a plurality of different displays are controlled by converting a signal for displaying one display into a signal for displaying the other display. In this conventional example, the display is controlled by converting a C:RT display signal into an LCD signal. In this case, the display to be displayed is limited, and many types of displays,
For example, it cannot support high-definition displays, standard displays, etc.

However, display controllers are now becoming more multi-functional and integrated, and as shown in Figure 3, instead of having built-in display controllers that correspond to each display individually, they are now built-in controllers that can be used universally for multiple different displays. Display controllers with this feature have also been commercialized. When using a display controller having this versatility, some controllers can control display switching by switching the dot clock signal input to the display controller corresponding to the display. Even when this general-purpose controller is used, when changing the display, the entire system must be reset once, the setting of the input dot clock signal changed, and then the system is restarted.[Problems to be Solved by the Invention] ] In the above conventional technology, when switching the dot clock signal input to the display controller, the entire system of the display device must be reset once. The problems caused by this will be explained using FIG. In the figure, 21 is a clock generator that generates a dot clock signal compatible with a CRT display, 22 is a clock generator that generates a dot clock signal that is compatible with a flat display, 23 is a selector, 24 is a general-purpose display controller, and 25 is a display memory. , 26 is C
The RT display 27 is a flat display. The selector 23 receives the dot clock signals of different frequencies generated by 21 and 22, and receives the dot clock select signal (24) from the general-purpose display controller.
The output of the dot clock signal is switched by the DC8 signal (hereinafter referred to as the DC8 signal). Operation of selector 23-Q,
Operates the same as a switch. In this case, do ``l''
-; Hazard occurs in the output of the no-sit clock signal because the dot-clock signal is switched instantaneously. The occurrence of this hazard causes problems such as noise occurring on the display screen, the contents of one display memory being destroyed, and the system going out of control. These problems will be explained in detail using FIG. 4. The dot clock signals generated by the dot clock generator 21 compatible with CRT displays and the clock generator 22 compatible with flat displays are respectively DCKI, DCK2 . The dot clock output signal from the selector 23 is ○DCK.

If the signal input from the general-purpose display controller 24 to the selector 23 is a DC8 signal, the above-mentioned signals will become a timing chart as shown in FIG. Since the DCS signal is switched by the general-purpose display controller 24 without considering the timing or state of the dot clock signal, immediately after switching, the dot clock output signal (○DCK signal) from the selector 23 has a temporary effect that can cause circuit malfunction. Hazard, which is a sudden change in output, occurs. The timing chart of the control signal to the memory when accessing the display memory when a hazard as shown in the figure occurs in the 0DCK signal is also shown in Figure 4. RAS signal 2, which is the strobe signal of the row address of the 0 display memory. C, which is the row address strobe signal
The AS signal, address signal, and data signal are shown. Due to the change in the dot clock signal due to the hazard, R
Although the active time of the AS and CAS signals has been greatly shortened and an address has been generated, no data is being output, so the display data cannot be accessed during the read cycle, causing noise on the display. During the write cycle, data in the display memory may be destroyed, or there is no data to be written, so if the system accesses that data, the system may run out of control. Therefore, it is impossible to switch to another display without changing the content of the screen that was being displayed before switching the dot clock. If the same display screen is displayed, it is necessary to repeat the steps required to display the same screen again. Repeating the same operation to make the contents of the display the same is extremely tedious and a waste of time. Therefore, it is an object of the present invention to control switching of dot clock signals so that no hazard occurs when switching dot clock signals corresponding to a display.

[Means to solve the problem]

The dot clock control circuit of the present invention is a switching circuit that selects and outputs one dot clock from a plurality of dot clocks having different frequencies, and when switching dot clocks, synchronizes the old dot clock with the edge portion. The device is provided with a holding circuit that holds and outputs at timing, and a switching circuit that switches the output from the old dot clock to the new dot clock when the logic state of the held old dot clock matches the logic state of the new dot clock.

The holding circuit holds the logic state of the output in synchronization with one edge (for example, a falling edge) of the old dot clock during switching. That is, if switching occurs at a falling edge, it is held in a logical state. Then, the switching circuit switches the output from the old dot clock to the new dot clock when the new dot clock becomes the same logic state as the old dot clock after switching, or in this case, when it falls. As a result, the logic state before switching matches the logic state after switching, so it is possible to prevent hazards from occurring due to switching.

(Embodiment) The first embodiment of the present invention will be explained below using the drawings. Fig. 1 is an overall system block diagram of the present invention. 1 and 2 shown in the figure indicate a plurality of different frequencies. This is a clock generator that generates a dot clock signal compatible with the display. 3 is a dot clock switching control circuit, which has a selector inside. 4 is a general-purpose display controller 5- (hereinafter abbreviated as display controller) compatible with various displays. ) 5 is the display memory of the display controller 4, 6 is the CR
T display, 7 is a flat display. Here, a flat display will be explained using a liquid crystal display (hereinafter referred to as LCD) as an example. The frequency of the dot clock signal corresponding to the display differs depending on the type and display format of the display. C
Dot clock signal DTC compatible with RT display
K1 is generated by a clock generator 1, and a dot clock signal DTCK2 corresponding to the LCD is generated by a clock generator 2. The dot clock switching control circuit 3 makes it possible to switch the dot clock signal corresponding to the display to be displayed without causing any hazard. This dot clock signal switching control is performed using a don't clock select signal (hereinafter referred to as DO8 signal). This DC8 signal is input from the display controller 4 to the dot clock switching control circuit 3. The dot clock switching control circuit 3 inputs the dot clock signal of the frequency selected by the DO8 signal to the display controller 4. FIG. 5 shows the internal circuit of the dot clock switching control circuit. The operation of the dot clock switching control circuit will be explained in detail using this circuit diagram. This dot clock switching circuit consists of four D-type flip-flops that hold data input at the falling edge of the clock input, five AND (logical product) circuits, and an OR (logical sum) circuit.
It consists of 4 circuits. D-type flip-flops, 31 is DFFI, 32 is DFF2, 33 is DF
F3, 34 to DFF4. AND circuit each 35A
NDI, 36 AND2.37 AND3, 38 AN
D4,43 AND5. OR circuit 39 each
1 and 40 are OR2, 41 is OR3, and 42 is OR4.

Also, the output of DFF1 is DC8L, XQI, the output of DFF2 is DO82, the output of DFF3 is Q3. DC822, DF
The output of F4 is DC8II, and the output of ANDI is 05. AN
The output of D2 is 06. The output of AND3 is 07. The output of AND4 is 08. The output of OR1 is Q9. QI the output of OR2
O,0R3(7) output is Qll, output of OR4 is Q12
．． Let the output of AND5 be the output ○DTCK of the dot clock switching control circuit. Circuit operation from DTCKl to DT
The explanation will be divided into the case of switching to CK2 and the case of switching from DTCK2 to DTCKl. First, a case will be described in which the dot clock signal is switched from the DTCKI signal to the DTCK2 signal. When switching from DTCK1 signal to DTCK2 signal, DO8 signal changes from 'H' state to (#
The state changes to L jj. DFFI changes the DO8 signal from the “H99 state to 1” at the falling edge of DTCKI.
1 Switch to the L'' state and keep the DC8L signal in the a L'''' state and the XQI signal in the IL H11 state. The XQI signal is a signal obtained by inverting the DC3L signal, and is input to DFF2. At the falling edge of DTCK2, the XQI signal switches from the IL" state to the 11" state and the D
Outputs O82 signal. In ANDl, the DCSL signal is R
Since it is held in the L I+ state, the Q5 output is 11 L.
The I+ state is output, and the 1 signal is no longer output to DT(,).

In AND2, the DC82 signal is held in the "JIH" state, so the Q6 output outputs the DTCK2 signal.OR1
The Q6 signal, which is the DTCK2 signal, and the It L I+
The Q5 output held in the state is input, and the Q9
The DTCK2 signal is output, and the DTCK2 signal is output to OR3.
The Q9 output, which is the CK2 signal, and the DCSL signal held in the L I+ state are input, and the Qll output is D.
TCK2 signal is output. In DFF3, the DC8 signal is switched from the "H" state to the It L11 state at the falling edge of the DTCK2 signal, and the Q3 signal held in the 1 (L11 state) and the DCS22 held in the "Htp state"
Output a signal. In AND3, the DC811 signal is “L”
Since the Q7 output is held in the "11 L" state, the DTCKI signal is not output, and the AND4 inputs the DC522 signal and the DTCK22 signal in the "1" state. Output. In OR2, the Q7 output held in the it L n state and the DTCK2 signal are input, and the QIO output is DTCK2.
A signal is output. The QIO signal, which is a uH″′-like signal, is input to OR4, and the Q12 output is It HP
Outputs an I state signal. AND5 is the Qll signal which is the DTCK2 signal and the it Hl (Q held in state).
12 signals are input, the output of the dot clock switching control circuit ○DTCK is outputted as the DTCK2 signal, and the D
The dot clock signal is switched from TCKl to DTCK2 signal. Conversely, when switching the dot clock signal from the DTCK2 signal to the DTCKI signal, the DC5 signal is
Changes from L 7+ state to H” state. DFFI is DT
At the falling edge of CKI, the DC84M signal is switched from l(L" state to ttH" state, and the DC8I signal is switched to Nl(
+? Hold the XQI signal in the “LIT” state. D
The XQI output input to FF2 switches from the II HI+ state to the 11 LI+ state at the falling edge of the DTCK2 signal, and holds the DO82 signal in the ``L'' state.

Since ANDl is held in the DC31C31 signal II HI+ state, the DTCK1 signal is output as the Q5 output. In AND2, the DC82 signal and the ttL II state signal are output, and the DTCK2 signal is not output. OR
Since the Q5 signal, which is the DTCKI signal, and the Q6 signal held in the 'L' state are input to I, the Q9 output outputs the DTCKI signal.OR3 receives the DC8L signal in the 'H' state. The Q9 output, which is the DTCK1 signal, is input, and the Qll output outputs a signal in the It Hlj state.

In DFF3, DC is set at the falling edge of the DTCK2 signal.
8 signal from ``L'' state to (I Hn state,
Since the Q3 signal is held in the "JH" state and the DTCK1 signal is held in the "L" state, the Q7 output is the DTCK1 signal.The AND4 inputs the DOS22 signal in the 71 L I+ state and the DTCK2 signal, and Output is “L”
The status signal is output, and the DTCK2 signal is not output.

In 0R22, Q7 output which is DTCK1 signal and 11 L
71 state Q8 output is input, QIO output is DTC
A KI signal is output. In OR4, DC in 'L' state
The QIO output, which is the 822 signal and the DTCKI signal, is input, and the Q12 output outputs the DTCKI signal.

In AND5, the Qll output in the 'H' state and the Q12 output which is the DTCK1 signal are input, and the DTCK1 signal is output from the output 0DTCK of the dot clock switching control circuit.This operation causes the DTCK1 signal to be changed from the DTCK2 signal.
The dot clock signal is switched to the signal. By operating the circuit as described above, it is possible to control switching of dot clock signals without causing hazards when switching dot clocks. In Figure 6, the dot clock signal is
FIG. 7 shows a timing chart when the dot clock signal is switched from DTCK2 to DTCK1. When switching the dot clock signal from DTCKI to DTCK2, the DCSL signal changes from the 11 HII state to the I L l'' state at the falling edge of the DTCKI signal, and then changes to DC8 at the falling edge of DTCK2.
2 signal from the II L I+ state to the IIH" state. Conversely, when switching from DTCK2 to DTCKI, after changing from the DTCK state to the (J L" state,
At the falling edge of DTCKI, the DC811 signal is set to L”
state to II H19 state. Regarding the timing of access to the display memory, since no hazard occurs in the 0DTCK signal, the active time of the RAS signal and CAS signal is not shortened, and no problem occurs in the exchange of addresses and data. Therefore, there is no risk of generating noise on the display or destroying the contents of the display memory.

In the first embodiment, the case where the dot clock signal to be switched is asynchronous is described. Next, in a second embodiment, a case where the dot clock signal to be switched is a synchronization signal will be described. In the case of synchronized signals, the dot clock switching control circuit can be implemented with a simple configuration. FIG. 8 describes a dot clock switching control circuit when the dot clock signal to be switched is a synchronous signal. This dot clock switching control circuit controls the DFF of the D-type flip-flop 51 that holds data at the falling edge of the input signal to the clock.
5 and 52 DFF6 AND (logical product) circuit 52 A
ND6 and 53 AND7.54 OR (logical sum) circuit O
It consists of R5. DCK the synchronized dot clock signal
I, DCK2, the output of DFF5 is Q5, XQ5,
The output of DFF6 is Q6. The output of AND6 is Q13. AN
The output of D7 is connected to Q14. The output of OR5 is set to 0DTCK1.

First, the case of switching the dot clock signal from DCK1 to DCK2 will be described. Similar to the first embodiment, when switching the dot clock signal from DCKI to DCK2, D
The O3 signal changes from the II HI+ state to the 11 LI+ state. DFF5 becomes D at the falling edge of DCKI.
Switch the O8 signal to hold the signal in the it L n state at the Q5 output and the signal in the I HJ+ state at the XQ5Q5 output. AND6 is the Q5 output held in “L” state and DC
The KI signal is input, and the Q13 output outputs a signal in the "L" state. DFF6 is switched at the falling edge of the XQ5Q5 output CK2 signal, and the Q6 output is ``H''.
Holds state signals. Since the Q6 output held in the "H" state and DC:K2 are input to AND7, the Q14 output is the DCK2CK2 signal. O
In R5, Q13 output in II L” state and DCK2CK2
Since 0DTCKI is signaled, DCK2CK2 is signaled. Conversely, when switching the dot clock signal from DCK2 to DCKl, the DC8 signal changes from the 11L77 state to the H" state, so DFF5
The DOS signal changes from “L” state to II at the falling edge of
Switch to HIT state and keep Q5 output in II HII state and XQ5 output in 11 L I7 state. AN
D6 contains Q5 and D, which are held in the trH” state.
Since the CKI signal is input, Q13 output is DCK
1 signal is output. DFF6 switches the XQ5 output from the H" state to the "L" state at the falling edge of DCK2 and outputs the Q6 output which is maintained in the LI L + state.

AND7 is the Q6 signal held in the uLu state,
Since DCK2 is input, Q14 output is II L
This becomes a PI state signal.

Since the DCKI signal and the Q14 signal held in the "L It" state are input to OR5, the 0DTCKI signal causes a hazard when switching the synchronized dot clock signal due to an operation of 0 or more that outputs the DCK1 signal. This makes it possible to switch and control the dot clock signal without causing noise on the display or destroying the contents of the display memory.

FIG. 9 shows a timing chart when the dot clock signal is switched from DCKI to DCK2 in the second embodiment.
The timing chart when the dot clock signal is switched from DCK2 to DCKI is shown in Fig. 10. Even if the dot clock signals are synchronized signals such as 0 or more, the dot clock signal switching control can be performed without causing a hazard. can be done. According to this embodiment, switching control of the dot clock signal can be performed without causing any hazards, and noise may be generated on the display.
There is no fear that the contents of the display memory will be destroyed and the system will run out of control.

〔Effect of the invention〕

According to the present invention, it is possible to share a display controller for a plurality of display displays. Furthermore, by sharing the display controller, multi-functionality and improved performance can be achieved. Furthermore, since a shared display controller can be used, the display can be switched by switching the dot clock signal without resetting the entire system. It also prevents noise on the display by preventing hazards from occurring when switching dot clock signals.

This also has the effect of protecting the contents of the display memory.

[Brief explanation of drawings]

Fig. 1 is a system block diagram of an embodiment of the present invention, Fig. 2 is a system block diagram of a conventional example, Fig. 3 is a system block diagram of a conventional example using a general-purpose display controller, and Fig. 4 is a system block diagram of a conventional example. , Fig. 3 is a timing chart of each signal in the system, Fig. 5 is a circuit diagram of an embodiment of the dot clock switching control circuit, and Fig. 6 is a diagram when the dot clock switching control circuit shown in Fig. 5 is used. DTCKl to D
Timing chart diagram when switching to TCK2, No. 7
The figure is a timing chart diagram when switching from DTCK2 to DTCKl when using the dot clock switching circuit shown in FIG. FIGS. 9 and 10 are timing charts at that time. 1...Clock generator. 2... Clock generator. 3... Dot-crotch switching control circuit. 4...General-purpose display controller. 5...Display memory. 6... Display display. 7...Display display/Fig. LCf) TEMPLAY DATA 22/Fig. ATA Foil drawing

Claims (1)

[Claims] 1. A first dot clock and a second dot clock having a different frequency from the first dot clock are input, and the first dot clock is switched to the second dot clock. In the dot clock switching control method, a switching signal is generated at a timing corresponding to an edge portion of the first dot clock, and the logic state of the output signal is changed to the first dot clock immediately after the switching timing signal is generated. , and the output dot clock is switched to the second dot clock when the second dot clock reaches the same logic state as the logic state of the held output signal. Clock switching control method. 2. Dot clock switching in which a first dot clock and a second dot clock having a different frequency from the first dot clock are input, and the first dot clock is switched to the second dot clock and output. In the control circuit, holding means holds the logic state of the output signal at a timing corresponding to an edge portion of the first dot clock at the time of switching; When the output signal matches the logic state, the output signal is
1. A dot clock switching control circuit comprising switching means for switching to a dot clock.