JPH0419894A - Elastic store circuit - Google Patents

Abstract

PURPOSE:To suppress the energy consumption of a memory by executing a frequency dividing operation by a frequency dividing means according to a clock signal and outputting a memory clock signal by a memory clock output means when the output value becomes a specified value. CONSTITUTION:When a read control signal RC is turned to an 'H' level, the '1' level is supplied through an inverter 23 of an up-counter 21 and AND gates 24-26 to a data terminal D of a D flip-flop 27-29 and therefore, this level is latched by the next clock signal CK so as to reset the output of the up-counter 21 to '0'. The output of this up-counter 21 is successively stepped by the clock signal CK and returned to '0' after it becomes '7'. Accordingly, a RAM clock signal RCK is a pulse signal having eight-fold cycle as much as the clock signal CK. Thus, the operating rate of a RAM 8 is suppressed to 1/8, and the energy consumption is suppressed to about 1/8 as well.

Description

DETAILED DESCRIPTION OF THE INVENTION Fields of Industrial Application The present invention performs write/read operations in response to write/read requests that occur asynchronously, and immediately reads data when a read request is made. The present invention relates to an elastic store circuit that outputs , and particularly relates to an elastic store circuit suitable for low power consumption circuits such as CMOS circuits.

[Prior Art] Conventionally, this type of elastic store circuit is configured as shown in FIG.

That is, the clock signal CK inputted via the clock input terminal 1 is inputted to each clock input terminal C, CLK of the D-type flip-flop 4, read address counter 5, and write address counter 6. Further, the read control signal RC input from the read control signal input terminal 2 is input to the data terminal of the D-type flip-flop 4 and the count control terminal C0NT of the read address counter 5, and is input from the write control signal input terminal 3. The write control signal WC to be
It is input to the count control terminal C0NT of the write address counter 6.

The read address RAD and write address WAD respectively output from the two address counters 5.6 are input to selection input terminals A and B of the address selector 7, respectively.

On the other hand, a write enable signal WE, which is the Q output of the D-type flip-flop 4, is supplied to the selection control terminal S of the address selector 7. The artless selector 7 selects the selection input terminal A1, that is, the read address RAD, when the level of the selection control terminal S is "H", and selects the selection input terminal B1, that is, the write address, when the level of the selection control terminal S is "L It". The selected address is output from the output terminal Y of the address selector 7.
It is applied to an address input terminal ADR of a RAM (random access memory) 8 as a RAM address AD.

A RAM clock signal (memory clock signal) RCK obtained by inverting the clock signal CK by an inverter 9 is supplied to the clock input terminal CLK of this RAM. Further, the write enable signal WE from the D-type flip-flop 4 is input to the read/write control terminal R/W of the RAM 8 .

Furthermore, the input data DI from the data input terminal 10 is input to the data input terminal IN of the RAM 8, and the output data Do is output from the data output terminal OUT of the RAM 8 to the data output terminal 11. .

FIG. 6 is a timing diagram showing the operation of this circuit.

The RAM 8 is normally in the write state, but when the read control signal RC goes to the "H" level, the D-type flip-flop 4 goes to the "H" level at the next rise of the clock signal CK.
”Since the level is latched, the write enable signal WE
rises, and the RAM 8 enters the read state. At this time, the read address counter 5 counts up and the read address RAD is updated. When RAM8 enters the read state,
Read address RAD is selected by address selector 7,
This is given to RAM8 as the RAM address AD, so the output data DO of the corresponding address from RAM8
is read out. This reading is performed using the RAM clock signal RC.
It is done according to K.

At the next rise of the clock signal CK, the D-type flip-flop 4 latches the "L" level as the read control signal RC, so the write enable signal WE falls and the R
AM8 returns to write state.

When RAM8 returns to the write state, write address WAD is selected by address selector 7, and this is written to RAM8.
It is given as address AD. As a result, RAM8
The input data DI from the data input terminal 10 is written into the storage area specified by the write address WAD.

This writing is also performed according to RAM clock signal RCK.

When write control signal WC goes to "H" level, write address counter 6 counts up at the next rise of clock signal CK, and write address WAD is updated.

[Problems to be Solved by the Invention] In the elastic store circuit described above, read/write requests occur asynchronously, and data must be output immediately in response to the read requests. For this reason, in conventional circuits, the memory clock signal RCK for operating the memory is set to the same period as the clock signal CK, and the RAM 8 is set so that the data can be read out immediately no matter when there is a read request. It operates in synchronization with a clock signal. For this reason, the memory operation frequency is extremely high, and redundant write operations are frequently performed.
There was a problem that power consumption was wasted.

The present invention has been made in view of such problems, and includes:
It is an object of the present invention to provide an elastic store circuit that can significantly reduce power consumption while operating without any problem in response to read/write requests that occur asynchronously.

[Means for Solving the Problems] An elastic store circuit according to the present invention includes a read address counter that updates and outputs a read address in synchronization with a clock signal based on a read control signal, and a clock signal based on a write control signal. a write address counter that updates and outputs a write address in synchronization with the read address counter, and a read address output from the read address counter and a write address output from the write address counter in accordance with the read control signal. a read/write memory that is controlled to be in a read state or a write state by the read control signal and receives the address selected by the address selector; frequency dividing means that is set to a value and performs a frequency dividing operation according to the clock signal; and memory clock output means that outputs a memory clock signal that operates the read/write memory when the output of the frequency dividing means is the specific value. It is characterized by having the following.

[Operations] According to the present invention, the frequency dividing means performs a frequency dividing operation in response to a clock signal, and when the output value thereof reaches a specific value, the memory clock output means outputs a memory clock signal. In other words, the memory clock signal that puts the read/write memory into operation is output at a longer cycle than the clock signal, so the operating rate of the read/write memory is limited and the power consumption of the memory can be significantly reduced. can.

Further, according to the present invention, when there is a read request, the output of the frequency dividing means is set to the specific value by the read control signal. Data can be immediately read and output from the read/write memory. Therefore, it is possible to ensure operation that does not interfere with read/write requests.

[Embodiments] Hereinafter, embodiments of the present invention will be described based on the accompanying drawings.

FIG. 1 is a block diagram showing the configuration of an elastic store circuit according to a first embodiment of the present invention.

In FIG. 1, the same parts as those of the conventional circuit shown in FIG. 5 are given the same reference numerals, and the explanation of the overlapping parts will be omitted.

This circuit differs from the conventional circuit shown in FIG.
It is a means for generating and outputting the RAM clock signal RCK that drives AM8. That is, in the circuit of this embodiment, the clock signal CK is input to the up counter 21,
The output of this up counter 21 and the clock signal CK are input to the four-man NOR gate 22, and the output of the NOR gate 22 is input to the RAM 8 as the RAM clock signal RCK.
is supplied to the clock input terminal CLK of.

Here, assuming that both the write request and the read request are output at intervals of 20 clocks or more, a 3-bit up counter can be used as the up counter 21. That is, the up counter 21 includes two D-type flip-flops 28 and 29 connected in cascade in a three-stage configuration.
and an inverter 23 that inverts the read control signal RC.
AND gates 24, 25, 26 for forcibly resetting each flip-flop 27 to 29 by the output of this inverter 23, AND gate 31 and EX-OR (exclusive (OR) gates 30 and 32.

Next, the operation of the elastic store circuit according to this embodiment configured as described above will be explained.

FIG. 2 is a timing diagram showing the operation of this circuit.

The RAM 8 is normally in the write state, but when the read control signal RC goes to "H" level, the D-type flip-flop 4 latches the "81 level" at the next rising edge of the clock signal CK, so that the write state is not performed. The enable signal WE rises and the RAM 8 enters the read state.At this time, the read address counter 5 counts up and the read address R
AD is updated.

Furthermore, when the read control signal RC goes to the "H'" level, it is supplied to the data terminals of the D-type flip-flops 27 to 29 at the "L" level via the inverter 23 of the up counter 21 and the ANDNO gate 226. It is latched by the next clock signal CK, and the output of the up counter 21 is reset to "0". This up counter 2
The output of 1 is sequentially stepped by the clock signal CK,
When it reaches 6'7'', it returns to '0' again. Then, only during the period when the output of the up counter 21 is at 'OII', the RAM corresponding to the period at which the clock signal CK is at the 'L II level' is
The clock signal RCK is sent from the NOR gate 22 to the RAM 8.
is output to. Therefore, the RAM clock signal RCK is
This becomes a pulse signal with a period eight times that of the clock signal CK.

When this RAM clock signal RCK is applied to the RAM 8, the RAM 8 outputs the output data D from the storage area specified by the read address RAD selected by the address selector 7.
o is read and outputted to the data output terminal 11.

At the next rise of the clock signal CK, the D-type flip-flop 4 latches the "L" level as the read control signal RC, so the write enable signal WE falls and the R
AM8 returns to write state.

When the RAM 8 returns to the write state, the address selector 7 selects the write address WAD and provides it to the RAM 8 as the RAM address AD. As a result, the input data DI from the data input terminal 10 is written into the storage area specified by the write address WAD of the RAM 8. This writing is also performed in accordance with the RAM clock signal RCK output from the NOR gate 22 every time the output of the up counter 21 reaches 6 "O".

In this way, according to the circuit of this embodiment, the output period of the RAM clock signal RCK is made eight times that of the conventional one.
8 is suppressed to 1/8, and power consumption is also suppressed to about 1/8.

In this embodiment, the write request interval and the read request interval are set to 20 clocks or more, and the period of the RAM clock signal RCK is set to 8 clocks.
The period of is not limited to this. However, the cycle of this RAM clock signal RCK is desirably set to 1/2 or less of the write request interval and the read request interval in order to prevent addresses from being written to before and after the read request is generated. .

In addition, in this first embodiment, a 3-bit up counter with a count value of "8" was used as the frequency dividing means, but if the count value is a power of 2 in this way, it is possible to optimize the counter. be able to. Further, in the first embodiment, an up counter is used, but a down counter can also be used.

FIG. 3 is a block diagram of an elastic store circuit according to a second embodiment of the present invention. In FIG. 3, the same parts as in the first embodiment shown in FIG. 1 are given the same reference numerals, and the explanation of the overlapping parts will be omitted.

In this embodiment, an 8-bit ring counter 41 is used as the frequency dividing means in place of the 3-bit up counter 21 used in the previous embodiment. ring counter 4
1 is a cascade-connected eight-stage D-type flip-flop 51 to 5 that performs a latch operation in response to a clock signal CK.
8, NOR gates 43-49 and an OR gate 50 for forcibly resetting the D-type flip-flops 51-58 by a read control signal RC.

The output of the ring counter 41 is 2 along with the clock signal CK.
It is input to a human-powered NOR gate 42. And N
The output of OR gate 42 is supplied to RAM 8 as RAM clock signal RCK.

FIG. 4 is a timing diagram showing the operation of this circuit.

As shown in this figure, the output of the final stage of the ring counter 41 reaches the "L" level once every eight clocks;
” level period and the clock signal GK °“l, I
RAM clock signal RCK is supplied to RAM8 during the I level period.

In this embodiment as well, as in the previous embodiment, the operation rate of the RAM 8 can be suppressed to ⅛, thereby reducing power consumption.

[Effects of the Invention] As explained above, according to the present invention, the memory clock signal that puts the read/write memory into operation is obtained by dividing the clock signal. The operation rate is limited, and the power consumption of the memory can be suppressed to a proportion corresponding to the frequency division ratio.

Further, according to the present invention, the output of the frequency dividing means is set to the specific value by the read control signal, so that when there is a read request, the output from the read/write memory is set to the specific value. Data can be read and output immediately.

Therefore, according to the present invention, it is possible to significantly reduce the power consumption of the circuit while performing operations without any problem in response to read/write requests that occur asynchronously.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an elastic store circuit according to a first embodiment of the present invention, FIG. 2 is a timing diagram showing the operation of the circuit, and FIG. 3 is an error diagram of an elastic store circuit according to a second embodiment of the present invention. A block diagram of the stick store circuit, FIG. 4 is a timing diagram showing the operation of the circuit in FIG. 3, FIG. 5 is a block diagram of a conventional elastic store circuit, and FIG. 6 is a diagram showing the operation of the circuit in FIG. 5. FIG. 1; Clock input terminal, 2; Read control signal input terminal, 3
;Write control signal input terminal, 4.27-29.51-58
; D-type flip-flop; 5; read address counter;
6; Write address counter, 7; Address selector, 8
;RAM, 9, 23;Inverter, 10;Data input terminal, 11;Data output terminal, 21;Up counter, 22.42-49;NOR gate, 24-2B, 31
;AND gate, 30,32;EX-OR gate,
41; Ring counter, 50; OR gate

Claims (1)

[Claims] (1) A read address counter that updates and outputs a read address in synchronization with a clock signal based on a read control signal, and a write address counter that updates and outputs a write address in synchronization with a clock signal based on a write control signal. an address selector that selects and outputs a read address output from the read address counter and a write address output from the write address counter according to the read control signal; a read/write memory that is controlled to be in a read/write state and receives an address selected by the address selector; and a frequency divider whose output is set to a specific value by the read control signal and performs a frequency dividing operation by the clock signal. and,
An elastic store circuit comprising memory clock output means for outputting a memory clock signal for operating the read/write memory when the output of the frequency dividing means is the specific value.