JPH02250332A - MOS type transistor - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION FIELD OF INDUSTRIAL APPLICATION The present invention relates to MO3 type transistors, particularly MOS type transistors with improved gate electrode structure.

2. Description of the Related Art A conventional method for forming an MO3 type transistor formed in an element region will be described with reference to the plan view and cross-sectional view of FIGS. 2(a) and 2(b).

In forming a conventional MOS transistor, first the surface of the substrate 2 in the element region 1 is gate oxidized, then polysilicon is grown on it, and then the polysilicon is patterned using a phosphorography process and then etched. Gate electrode 3 and gate oxide film 4 are formed.

By the way, (100) of the 81 wafer forming the substrate 2
When a surface is used, a so-called channeling phenomenon occurs in which the implanted ions penetrate through the 81 lattices. This phenomenon causes the source part (region) and drain part (region) of the rRIfAMO3 type transistor to be brought close to each other, making punch-through more likely to occur when voltage is applied. For this reason, ion implantation is performed at an angle of 7° with respect to the normal to the wafer using the gate electrode 3 as an implantation mask to form impurity implanted regions 5 that will become the source/drain portions.

Problems to be Solved by the Invention However, when ion implantation is performed parallel to the middle direction of the gate electrode 1i3 when forming the source/drain part of a conventional MO3 type transistor (A in FIG. 2(a)), However, if the implantation is perpendicular to the middle direction of the gate '@S3 (the implantation is performed from the B direction in FIG. 2(a)), there is no problem.
As shown in FIG. 2(aL(b)), an offset region 6 is generated in the impurity implanted region 5, which is in the shadow of the gate electrode 3 and becomes the source/drain portion, resulting in an asymmetric structure.

When structural asymmetry occurs in the impurity implanted region 5 of a transistor, a large difference occurs in electrical characteristics depending on which impurity implanted region 5 is used for the source and drain. 41I When a circuit is constructed using transistors that are structurally asymmetric and have different electrical characteristics, even if the circuit is constructed in the same way, the circuit operation may be completely different unless the direction of injection is taken into consideration when making connections. There is a possibility that it will happen. For example, if a plurality of sense amplifier circuits are formed using such structurally asymmetric transistors on the same chip, there is a problem that the sensitivity of each sense amplifier circuit increases. One way to solve this problem is to align the gate directions, especially in transistors that require uniform electrical characteristics. However, it is difficult to align the gate directions due to layout constraints, especially with large transistors in the gates.

The present invention solves these conventional problems,
The object of the present invention is to provide a MOS transistor with improved asymmetry in the transistor structure.

Means for Solving the Problems In order to solve the above problems, the present invention changes the shape of the gate electrode on the element region to the direction of ion implantation when forming the impurity implanted regions that will become the source/drain regions.
It has a parallel part and a perpendicular part, and the parallel part and the perpendicular part have equal lengths.

Effect With the above configuration, by forming the gate electrode by bending it perpendicularly at the center in the direction of the ion implantation direction,
No matter which direction ions are implanted from any direction perpendicular to the center direction of the gate electrode using the gate electrode as a mask, the impurity implantation region corresponding to 1/2 of the gate electrode, that is, the source region.
The drain portion is symmetrical, and only the remaining source/train portions corresponding to 172 are asymmetrical. Therefore, differences in electrical characteristics due to MO3 type transistor ellipse zero asymmetry are reduced.

Example An embodiment of the present invention will be described below based on the drawings.

FIG. 1 is a plan view of an MO3 type transistor showing one embodiment of the present invention.

The shape of the gate electrode 12 on the element region 11 is
When forming an impurity implantation region that will become a drain part, the ion implantation direction has a part whose middle direction is parallel and a part perpendicular to the direction, and the length of the part which is perpendicular to the parallel part.
, Ω2 have the same structure.

A method for forming a MOS transistor having the above structure will be explained.

First, the surface of the substrate in the element region 11 is gate oxidized, and polysilicon is further grown thereon, and then the polysilicon is grown by a lithography process to a length ρ1 of the parallel portion and the perpendicular portion. A gate ti12 and a gate oxide film (not shown) are formed by uniformly patterning ρ2 and etching.

Then, using the gate ti12 as an implantation mask, the element region 11
Ion implantation is performed from direction C or direction at an angle of 7° with respect to the normal to the Sl wafer forming the substrate to form impurity implanted regions 13 and 14 that will become the source/drain portions. For example, if ion implantation is performed from direction C, the first
The shaded area 15 in the figure is the gate voltage [! 12, no ions are implanted, and the source and train regions become asymmetrical.Ions are implanted into the region 16 shown by the mesh in FIG. 1, and the source and drain regions become symmetrical. The same holds true when ion implantation is performed from any direction.

The MO3 type transistor formed in this way has a source
The asymmetric region of the drain part is 17 of the gate electrode 12.
Since the region corresponds to 2, differences in electrical characteristics due to asymmetry can be reduced.

Note that the ion implantation directions E and F are opposite to the ion implantation directions C and D.
Ion implantation may be performed from the beginning.

Effects of the Invention As described above, according to the present invention, ion implantation is performed using the gate electrode formed by bending the middle direction perpendicularly at the center to the ion implantation direction as a mask, thereby eliminating the asymmetrical source/drain regions. The region can correspond to the region 172 of the gate electrode, and differences in electrical characteristics due to asymmetry can be reduced without increasing the number of process steps or increasing the transistor area.

[Brief explanation of drawings]

FIG. 1 is a plan view of a MOS type transistor showing an embodiment of the present invention, and FIGS. 2(a) and 2(b) are a plan view and a sectional view, respectively, of a conventional MO3 type transistor. 11... Element region, 12... Gate electrode, 13.1
4... Impurity implantation region, 15... Region that becomes the shadow of gate t@ and is not implanted with ions, 16... Region that does not become the shadow of gate electrode, C, D, E, F... Ion implantation direction. Agent Yoshihiro Morimoto Figure 1 If, -0 element analysis U or 12, -, Gate electrode 13.14. -, impurity implantation region

Claims (1)

[Claims] 1. The shape of the gate electrode on the element region has a part whose width direction is parallel to the ion implantation direction when forming the impurity implanted region to become the source/drain part, and a part which is perpendicular to the ion implantation direction, and A MOS transistor with parallel and perpendicular parts of equal length.