JPH02250185A - Method and device for accessing picture memory - Google Patents

Abstract

PURPOSE:To increase the access speed by accessing a memory continuously plural times in the quick access mode based on coordinate values in the arrangement direction of sectioned memory areas and a common coordinate value in the direction orthogonal to this direction. CONSTITUTION:A picture memory 1 where the capacity of one plane is plural times as large as the resolution for display is sectioned with the resolution as the unit, and a coordinate value (y) in the direction orthogonal to the arrangement direction of sectioned memory areas 11 to 13 is denoted as the common coordinate value. With respect to coordinate values x1 to x3 in the arrangement direction of sectioned memory areas 11 to 13, not only a prescribed increment value DELTAx is accumulated to an initial value x0 but also offset values xf1 to xf3 corresponding to memory areas 11 to 13 are added to obtain peculiar coordinate values x1 to x3 corresponding to memory areas 11 to 13. The memory is quickly accessed based on both coordinate values (y) and x1 to x3. Thus, the capacity of the picture memory having many functions is reduced to a required minimum value, and the memory access speed is increased.

Description

DETAILED DESCRIPTION OF THE INVENTION <Field of Industrial Application> The present invention relates to an image memory access method and apparatus, and more specifically, to an image memory (color buffer, depth) access method and apparatus using a large capacity memory device.・It greatly suppresses the unnecessary increase in the number of memory devices required when configuring buffers, sectioning buffers, mapping memory', and -Relates to a novel image memory access method and device that enables access.

<Prior art and problems to be solved by the invention> There has been a strong demand for multifunctionality and high functionality in graphics display devices, and in addition to color buffers, depth buffers for hidden surface processing have been required. , a sectioning buffer for cross-section processing, a mapping memory for texture mapping processing, etc. are becoming common.

For example, the resolution of the color buffer, depth buffer, and sectioning buffer are all set to 1024x.
If 2048 pixels are set and the number of planes is set to 24, 16, and 16, the total memory capacity will be 112 Mbits. However, recently there has been a strong demand to make the color buffer dual-plane, and to improve the accuracy of the depth buffer and sectioning buffer (for example, converting depth data and sectioning data to 24 bits), and it is difficult to satisfy these demands. If this were attempted, the total memory capacity would increase by 80 Mbits, leading to increased costs and larger hardware. In other words, as the capacity increases, the number of memory devices increases, resulting in an increase in the mounting area of the memory device.Also, as the number of planes increases, the number of bits for linear interpolation calculators, etc. increases. As a result, the circuit becomes complicated.

Recently, 256K x 4-bit DRAM (hereinafter referred to as
IM bit DRAM (abbreviated as IM bit DRAM) has become available, and if an image memory is configured using this IM bit DRAM, the DRAM will be smaller than when using a 64 x 4 bit DRAM. Since the number of elements can be reduced to 174, an increase in the mounting area can be considerably suppressed. However, in this case, since one plane is composed of two 1M bit DRAMs, the bit width is reduced to 8 bits. In order to access the memory, the host computer must perform the access four times, and the image display speed decreases to I11. Since image display speed is the most important factor in graphics display devices, it was thought that it would be impossible to use a 1M bit DRAM.

<Object of the invention> This invention was made in view of the above problems,
It is an object of the present invention to provide an image memory access method and apparatus that can reduce the capacity of an image memory having a large number of functions to the necessary minimum and speed up memory access.

<Means for Solving the Problems> The image memory/image memory of the present invention to achieve the above object
The access method is to partition the image memory, in which one plane has a capacity multiple times the display resolution, using the above resolution as a unit, and set the coordinate values in the direction in which the partitioned memory areas are lined up as initial values. By cumulatively adding a predetermined increment value to each memory area and adding the offset value corresponding to each memory area, the obtained coordinate value is orthogonal to the direction in which the memory areas are lined up. In this method, memory access is continuously performed multiple times in a high-speed access mode based on a common coordinate value in the direction in which the data is stored.

To achieve the above object, the image memory and
The access device has a capacity of one plane having a plurality of resolutions for display, and an image memory partitioned in units of the above-mentioned resolutions, and an image memory in a direction perpendicular to the direction in which the partitioned memory areas are lined up. a first address generating means that obtains a coordinate value by cumulatively adding a predetermined increment value to an initial value; and a first address generating means that obtains a coordinate value by cumulatively adding a predetermined increment value to an initial value; A second address generation means which obtains each value corresponding to each memory area by cumulatively adding the values and adding an offset value corresponding to each memory area, and a high speed processing based on the coordinate values obtained by both address generation means. The memory access control means continuously performs memory access a plurality of times depending on the access mode.

However, one plane of the image memory is a 1M bit DRAM.
It consists of four memory areas and is divided into units of 1024 x 1280 pixels, and at least one of the three divided memory areas is allocated to the color buffer, and the other memory area is used for other purposes. It may also be something that is allocated to a buffer.

With the above image memory access method, the image memory, in which one plane has a capacity multiple times the resolution for display, is partitioned using the above resolution as a unit, and the partitioned memory areas are lined up. Obtain the coordinate values in the direction orthogonal to the direction in which the partitioned memory areas are located and use them as common coordinate values for each memory area. Also, calculate the coordinate values in the direction in which the partitioned memory areas are lined up by increasing a predetermined increment value from the initial value. Multiple memory areas are partitioned by cumulatively adding and adding offset values corresponding to each memory area to create a unique coordinate value corresponding to each memory area, and performing high-speed memory access based on both coordinate values. Memory access can be performed continuously and at high speed.

In the image memory access device having the above configuration, one plane of the image memory has a capacity multiple times the resolution for display, and is partitioned using the resolution as a unit, so the first address generating means It is possible to obtain coordinate values in a direction perpendicular to the direction in which the memory areas partitioned by the second address generating means are arranged, and to obtain coordinate values of each memory area in the direction in which the partitioned memory areas are arranged by the second address generation means. , the memory access control means performs memory access in high-speed access mode based on the obtained coordinate values, and the high-speed access control means performs memory and access based on the coordinate values obtained by both address generation means. By performing this multiple times in succession, memory access to a plurality of partitioned memory areas can be performed continuously and at high speed.

One plane of the image memory is a 1M bit DRA.
Consists of 4 M pieces and 1024X1280
The image is divided into pixels, and if at least one of the three divided memory areas is allocated to a color buffer and the other memory areas are allocated to buffers for other purposes, the image The total memory capacity may be 96 Mbits, and it may be possible to have a dual-plane color buffer configuration with a hidden surface processing function, or a single-plane color buffer configuration with a hidden surface processing function and a color buffer with a hidden surface processing function. It becomes possible to provide a cross-section display function, a hidden surface processing function and a texture mapping function in addition to a single plane configuration of the color buffer.

To explain in more detail, if the resolution per plane of the image memory is increased and partitioned into multiple memory areas with display resolution as a unit, the memory area can be partitioned regardless of the capacity of the memory device. Because it is possible to
The memory can be used effectively as a whole, and the surplus area generated as a whole can be significantly reduced. When accessing an image memory configured in this way, the coordinate value in the direction perpendicular to the direction in which the memory areas are lined up is taken as the row address, and the coordinate value in the direction in which the memory area is lined up is called the column address. if,
By applying fast access modes such as fast page mode access, page mode access, static column mode access, etc., it is possible to significantly speed up access to multiple memory areas as a whole.

<Example> Hereinafter, embodiments will be described in detail with reference to the accompanying drawings showing examples.

FIG. 3 is a diagram schematically showing the configuration of the image memory.
Four M-bit display dual port DRAMs are used to configure a plane with a resolution of 4096 x 1024 pixels, and by using 24 of these planes, the image memory (1
). And set all planes to 1280
Three memory areas of x1024 pixels (11) (12)
(13) and a surplus area of 256 x 1024 pixels (14
).

In addition, the above three memory areas (11) (12) (+3)
For example, an index dual plane using 12 planes each, a depth buffer, a sectioning buffer, or a single plane of RGB 16.7 million colors, a depth buffer, a sectioning buffer, or an RGB 167
00,000 colors single plane color buffer, depth buffer, mapping memory or RGB16
Dual φ plane color 〇 buffer and depth buffer of 700,000 colors are allocated.

Therefore, the number of IM bit DRAMs constituting the image memory (1) with such a configuration is only 96, which significantly reduces the number of memory devices compared to the case where each memory area is configured with physically separate memory devices. In addition, the precision of all memory areas can be improved to 24 bits.

FIG. 1 is a block diagram schematically showing the configuration of an address generation unit for generating access addresses for three memory areas. an X-coordinate value increment value calculation unit (21) that obtains an increment value Δy of (22) and the increment value △ of the coordinate value in the scan line direction (hereinafter abbreviated as the X coordinate value)
x, and an offset value xr1xf2 . corresponding to each memory area with respect to the initial value XO output from the X coordinate value increment value calculation unit (23). x
f3 (in the case of the specific example in Fig. 3, x f'l=0, x
f2-1280. xf'1=256'0)) and a new initial value x01.x to which the offset value is added.
x 02X03 (in the case of the specific example in Figure 3, xol
=xO.

x02=xO+1280. x03=x'0 12560
) by cumulatively adding the increment value Δx, the X coordinate value x of any pixel is calculated. x2. It has a cumulative addition unit (27) (2g) (29) that obtains x3.

Therefore, if memory access is performed in fast page mode, the W signal is set low as shown in Figure 2.
The image memory (
1), and then by lowering only the m signal to the low level three times, the cumulative adder (27) (28) (
29), the X coordinate values xi, x2. By sequentially supplying x3 to the image memory (1) as a column address, three memory areas (11) (12) (1
Data corresponding to the same pixel in 3) can be accessed at high speed.

That is, three memory areas (11), (12), and (13) each contain a single plane color buffer of 16.7 million RGB colors, a depth buffer, and a sectioning buffer.
When allocated to the buffer, the delay time associated with the output of the comparator flag for hidden surface processing and the comparator flag for section processing is significantly reduced, and the access to depth data, sectioning, etc.
Since data can be accessed much faster, the overall memory cycle time can be significantly reduced.

FIG. 4 is a block diagram showing an example of the configuration of a pixel circuit for image memory access, and corresponds to a state in which an 8×2 pixel double buffer memory is provided.

Initial value yO supplied from the upper processor (not shown)
. The y-coordinate value y and the X-coordinate value xl, x2 . Lower digit of x3 (
A pixel buffer selection signal is generated by supplying the least significant bit of the X coordinate value and the lower three bits of the do.

The contents of the pipeline registers (3[i) (37) (38) that temporarily hold the initial values RO, GOBO and the incremental values ΔR1ΔG, ΔB supplied from the upper processor are added to the cumulative adder (39). (40) (41
) and each cumulative adder (39) (
40) The color values R, G, and B output from (41) are supplied to the register (43) for the selected pixel through the multiplexer (42).

A pipeline register (4
4) are respectively supplied to the cumulative adder (45), and the depth value 2 outputted from the cumulative adder (45) is supplied to the register (46) for the selected pixel.

Then, the contents of the register (43) are converted into the logical operation unit (
47), the contents of the register (46) are supplied to a pair of comparators (48) (49), and the output data from the logic operation unit (47) is sent to the bus Φ buffer (50).
is supplied to the image memory (1) through. In addition, the contents of the latch circuits (51), (52), and (53) that temporarily hold the data read through the bus bus (50) are transferred to the logical operation unit (47) and the comparator (53), respectively.
48) It supplies to (49). Furthermore, comparator flag f1. output from comparator (48) (49). f2 is supplied to the logic operation unit (47). The above registers (43) (4B), logic operation unit (47), comparators (48) (49), bus buffer (50) and latch circuits (51) (52)
) (53) is required for the number of pixels in the double buffer memory, but only one pixel is shown in the above block diagram. Then, as shown in FIG. 5, the X coordinate value y and the X coordinate value x1. x2. x 3 are registers (54) (55) (5B) (57
) - a multiplexer (58) and a bus buffer (59) which are held in time and controlled by a control unit (60).
) is selectively output as an access address to the image memory (1).

When the above configuration is adopted, the X coordinate value for each pixel,
The X coordinate value, depth value and color value are output from the corresponding accumulators, respectively. Then, the X coordinate value and
The lower digit of the coordinate value is decoded by the decoder (35) and stored in the corresponding register (43) of the double buffer memory.
(411i) and supplying both of the coordinate values as access addresses to the image memory (1), the pixel data is read out and temporarily held in the corresponding latch circuit.

Next, a comparator (48) compares the new depth value held in the register (46) with the depth value read out from the memory area (12), and compares the new depth value with the depth value read out from the memory area (13). The comparator (49) compares the size with the sectioning value read out from A new color value to be written can be obtained by performing a logical operation based on the value and whether hidden surface processing or cross section processing is necessary, and written into the memory area (11) through the bus buffer (50). In addition, regarding the new depth value, the above comparators (48) (49)
), the memory area (
12).

FIG. 6 is a timing chart schematically explaining hidden surface processing and cross section processing. By lowering the RAS signal to a low level, the y coordinate value y held in the register (54) is set to the low address. image memory (1
) and then lowers only the stone signal to low level twice, lowers the °C knee signal to low level twice, and
Coordinate value X3. By sequentially supplying x2 as a column address to the image memory (1), the sectioning value zI3L and the depth value 2 are sequentially read out from the memory areas (13) and (12) of the image memory (1). Then, the new depth value z new held in the register (46) is zBL>znew>z or zBL<znew
Comparators (4, 8) (49) determine whether < z (which is determined by either one based on the coordinate system) is satisfied.
If it is determined that the stone is satisfied, a new depth value z n is determined by lowering the WE- signal to a low level while keeping the stone signal at a low level.
Write ew to the memory area (12). In addition, in this case, the color value must also be updated as the depth value is updated, so at the same time, the prisoner signal is lowered to a low level, the W- signal is lowered to a low level, and the register By supplying the X coordinate value X1 held in (55) to the image memory (1) as a column address, the color value RGB is stored in the memory area (11) of the image memory (1).
can be written. Note that the RAS signal continues to be held at a low level until the above series of operations is completed.

As is clear from the above explanation, since both the comparators (4B) (49) and the logic operation unit (47) are built into the same pixel buffer, the propagation delay time of the comparator flags fl and f2 is mostly taken into account. This eliminates the need for timing design.

Furthermore, the configuration of the bus buffer (50) itself can be simplified by time-division control. Furthermore, the address output section and the pixel buffer can be easily integrated into LSI. Furthermore, since the clearing operation for memory areas (12) and (13) can be performed in the same way as for memory area (11), it is possible to significantly speed up the clearing of the depth buffer, which previously took a long time. can.

Note that the above describes the memory area (11) of the image memory (1) (
12) We have explained the case where (13) is allocated as a single plane color Φ buffer, depth buffer, and sectioning buffer with RGB 16.7 million colors, but even when other allocations are selected, pixels are This can be resolved by simply changing the buffer configuration.

It should be noted that the present invention is not limited to the above-mentioned embodiment. For example, the present invention is not limited to the above embodiment.
In addition to increasing the coloring speed by providing two sets of linear interpolation calculators, it is also possible to increase the resolution per plane of the image memory and partition it into four or more memory areas. Yes, and furthermore,
In addition to being able to set the offset value arbitrarily,
Various design changes can be made without departing from the gist of the invention.

<Effects of the Invention> As described above, the first invention can configure a large number of memory areas with a small memory capacity, and moreover, by simultaneously obtaining access addresses corresponding to the same pixel in each memory area, all memory areas can be configured with a small memory capacity. This has the unique effect of speeding up access to the memory area.

The second invention is to be able to configure a large number of memory areas with a small memory capacity, and to speed up access to all memory areas by simultaneously obtaining access addresses corresponding to the same pixels in each memory area. Furthermore, the present invention has nine unique effects: it simplifies the configuration for memory access, and it simplifies timing design.

The third invention is that the image memory having three memory areas can be configured with a small number of IM bit DRAMs to make the entire image compact, and data related to each other can be stored in the three memory areas. This has the unique effect of making it possible to achieve higher functionality and higher speed of the graphic display device.

[Brief explanation of drawings]

FIG. 1 is a block diagram schematically showing the configuration of an address generation unit for generating access addresses for three memory areas, and FIG. 2 is a timing diagram schematically showing memory access.
3 is a diagram schematically showing the structure of the image memory, FIG. 4 is a block diagram showing an example of the structure of a pixel buffer for accessing the image memory, and FIG. 5 is a diagram showing an example of the structure of the address buffer. FIG. 6 is a timing chart schematically explaining hidden surface processing and cross-section processing. (1)...Image memory, (11) (12) (13
)・Memory area, (21)...X-coordinate value increment value calculation unit, (22) (27) (28) (29)...cumulative addition unit, (23)...X-coordinate value increment value calculation Department, (24
) (25) (26)...Offset addition section, (5
8) Multiplexer, (59) Bus buffer, (60) Control unit, (x0) (y0) Initial value, (x I) (x 2) (x 3) ...X coordinate value,
(y)...y coordinate value, (△x) (Δy)...incremental value, (x'fl) (xf2) (xf3) -...offset value Patent applicant Agent of Daikin Industries, Ltd.

Claims (1)

[Claims] 1. An image memory (1) in which each plane has a capacity multiple times the resolution for display is divided into units of resolution, and the divided memory areas (11) (12) The coordinate values (x1) (x2) (x3) in the direction in which (13) are lined up are set to the initial value (
By cumulatively adding a predetermined increment value (△x) to x0) and adding offset values (xf1) (xf2) (xf3) corresponding to each memory area (11) (12) (13). Coordinate values (x1) (x2) (x3) obtained corresponding to each memory area (11) (12) (13)
) and a common coordinate value (y) in a direction perpendicular to the direction in which the memory areas (11, 12, and 13) are lined up. An image memory access method characterized by: 2. An image memory (1) in which one plane has a capacity multiple times the resolution for display and is partitioned using the above resolution as a unit, and partitioned memory areas (11), (12), and (13). First address generating means (21) (22) that obtains a coordinate value (y) in a direction orthogonal to the direction in which the coordinates are arranged by cumulatively adding a predetermined increment value (△y) to an initial value (y0). and the coordinate values (x1) (x2) (x3) in the direction in which the partitioned memory areas (11) (12) (13) are lined up are set to the initial value (x0).
By cumulatively adding a predetermined increment value (△x) to each memory area, and adding offset values (xf1) (xf2) (xf3) corresponding to each memory area (11) (12) (13), each memory Second address generation means (23) (24) respectively obtained corresponding to areas (11) (12) (13)
(25) (26) (27) (28) (29) and both address generation means (22) (23) (24) (25) (26
)(27)(28)(29) The coordinate value (y
) (x1) (x2) (x3)
An image memory access device characterized by comprising memory access control means (58), (59), and (60) for sequentially performing memory access a plurality of times depending on the mode. 3. One plane of image memory (1) is 1M bit DR
It is composed of four AMs and is partitioned into units of 1024 x 1280 pixels, and at least one of the three partitioned memory areas (11), (12), and (13) is allocated to the color buffer. 3. The image memory access device according to claim 2, further comprising allocating other memory areas to buffers for other uses.