JP3309253B2 - Apparatus for writing to and reading from a multi-bank frame buffer random access port and method for increasing the speed of writing pixels to a multi-bank frame buffer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a computer system and, more particularly, to accessing a frame buffer used to supply output signals to an output display device so that vertical lines can be drawn quickly. And a method and apparatus for doing so.

[0002]

2. Description of the Related Art Computer devices use a buffer memory called a frame buffer for storing data to be written to an output display device. The information in the frame buffer is written to the display as a whole line by line, starting from the upper left corner of the display to the lower right corner. As the picture in one frame changes to a picture in the next frame, one of the information is presented so that a continuous motion is presented.
One frame is followed by the next.

[0003] Typically, the frame buffer is composed of a video random access memory (VRAM). The video random access memory includes a first random access port that allows reading or writing of a frame buffer, and a second random access port that is used to supply pixel data to a circuit that controls an output display device. 1 is different from a normal random access memory in that it has one line output port. With this structure, information can be written to the frame buffer while the frame buffer continuously supplies information to the output display device.

One physical device used for frame buffers is on a horizontal line, where the first pixel to be displayed is stored in a first VRAM bank and the second pixel in that line is a second pixel. Several banks of VRAM so that the storage operation can be continued until the last VRAM bank, such as the third pixel in that line is stored in the third VRAM bank, and so on. Is composed. Then, storage of the pixels in the first VRAM bank is started. With this configuration, several pixels can be written together into the frame buffer, so that a pixel that draws one horizontal line can be written very quickly. In addition, page mode addressing, which allows faster intra-page addressing of memory than typical random access memory of a frame buffer, enhances this effect on horizontal lines.

However, drawing a vertical line on a display device is
The use of the above-mentioned multi-bank frame buffer is greatly affected. The reason is that drawing a vertical line requires that the same VRAM bank of the frame buffer be used for each pixel in the line. Therefore, pixel accesses in the same VRAM bank must be addressed sequentially through the random access port to draw the line. Since the same bank is addressed to write to the frame buffer, there has been no way to access in parallel or overlap those accesses. Since the size of the page is typically only about one or two lines of the display, using page mode access does not increase the speed of addressing the pixels that draw the vertical lines.

[0006] With the advent of various screen control programs that display a plurality of different application programs in a plurality of windows on a display device, drawing vertical lines has recently become important. The number of vertical lines used by those screen programs reduces the time required to draw those vertical lines. Therefore, it would be advantageous to be able to accelerate the operation of drawing a vertical line on the output display of a computer device.

[0007]

SUMMARY OF THE INVENTION It is therefore an object of the present invention to increase the speed of drawing straight and non-horizontal lines in an output display of a computer without sacrificing the speed of drawing lines. is there.

Another object of the present invention is to provide an improved method and apparatus for accessing a frame buffer that allows vertical lines to be drawn more quickly on an output display.

[0009]

SUMMARY OF THE INVENTION These and other objects of the present invention are directed to a method for storing individual pixels to be provided to draw vertical lines on an output display from the top in various banks of a frame buffer. It is implemented in an apparatus for writing to and reading from a random access port of a frame buffer so that access to the frame buffer can be superimposed so as to be sequentially arranged to the bottom.

[0010] Some portions of the detailed description that follows are presented in symbolic representations of operations on data bits within a computer memory. These descriptions and expressions are used by data processing technology professionals to most effectively convey their work to other data processing technology professionals. The operations and expressions are those requiring physical manipulation of physical quantities. Usually, but not necessarily, these quantities take the form of electrical or magnetic signals that can be stored, transferred, combined, compared, and otherwise processed. It has proven convenient at times, principally for reasons of common usage, to refer to those signals as bits, values, symbols, characters, terms, numbers, or the like. However, it should be remembered that all of these and similar terms should be associated with the appropriate physical quantities and that they are merely convenient labels applied to those quantities.

Further, the processing performed is often referred to in terms, such as adding or comparing. These processes are related to mental activities performed by humans. In most cases in any of the processes described herein that form part of the present invention, such a person's ability is necessary and desirable. The operation is a machine operation. Devices useful for performing the operations of the present invention include general purpose digital computers and other similar devices. In any case, the difference between the way the computer operates and the processing itself should be remembered. The present invention relates to an apparatus and method for operating a computer to process electrical and other (eg, mechanical, chemical, and physical) signals to generate other desired physical signals. It is.

[0012]

DETAILED DESCRIPTION As described above, one physical design used for a frame buffer memory is that the first pixel on the horizontal line to be displayed is a video random access memory (VR).
AM), a second pixel is stored in a second VRAM bank, and a third pixel is stored in a third VRA.
Several banks of video random access memory are configured so that pixels are stored sequentially up to the last VRAM bank, stored in M banks, and so on. With this configuration, a pixel that draws one horizontal line can be written very quickly on the output display device, but it is extremely difficult to draw a vertical line on the display device. The reason is that drawing a vertical line requires that the same bank of the frame buffer be addressed to the same bank of the frame buffer using random access addressing of each sequential pixel of the vertical line. Since the same bank is addressed by sequentially accessing the frame buffer, there has been no method of superimposing accesses.

FIG. 1 shows the arrangement of individual VRAMs in a frame buffer associated with an output display. Figure 3
As can be seen, the four VRAMs V0-V3 are physically arranged to provide pixels for display. Each VRAM bank holds one pixel in a series of four pixels in a horizontal line. In FIG. 1, each pixel supplied by the bank of the VRAM is shown at a position on a shortened horizontal line. Because of the typical addressing scheme of the prior art, which will be described in more detail below, V is used to read and write horizontal lines using a random access port.
RAM access is very fast because it can be performed almost in parallel.

However, when a vertical line is drawn, the time to access the frame buffer increases significantly. This can be understood by looking at the first four pixel positions in the left column of VRAM bank 10 in FIG. As can be seen from the descending X depicting the pixels in the short vertical line, each location storing those four pixels is stored in the same bank 10 of the frame buffer. Therefore, to draw a vertical line, the VRAM bank V0 must be sequentially accessed four times through the random access port of the frame buffer, or four pixels must be written.
Since these pixels are in the same VRAM bank 10, heavy
It cannot be accessed more than once . For this reason, drawing vertical lines is much more time-consuming than accessing the frame buffer to draw horizontal lines.

FIG. 2 shows a repeating pattern of pixels held in a typical frame buffer having four individual video random access memory banks arranged as described with reference to FIG. As can be seen, pixel patterns 0, 1, 2, and 3 represent a series of VRAM banks that store the pixel patterns to be displayed in the line.
Each pixel in a series of VRAM banks that draws a horizontal line has a VRA
It can be seen that the data is stored in the repetition column of the M banks. On the other hand,
All pixels that draw a vertical line are stored in the same VRAM bank. It is worth noting here that any diagonal is drawn by a series of pixels stored in the various VRAM banks of the frame buffer. However, since the typical number of diagonals presented is much less than the number of vertical lines, it is the task of drawing the vertical lines that slows down the rendering of the display.

FIG. 3 shows a VRA in a conventional frame buffer.
FIG. 3 is a block diagram illustrating a circuit that controls access to M banks. This illustrates better why horizontal lines can be drawn faster than vertical lines. Circuit 20 includes four VRAM banks individually labeled V0-V3. The X and Y addresses are provided via multiplexer 22 (which generally indicates a random access circuit for addressing the frame buffer).
The multiplexed addresses are stored in the individual banks V0-VRAM.
Supplied to all of V3. All of these banks have the same address for the four individual pixels in a horizontal series 0, 1, 2, 3 shown in FIG. When each pixel is supplied to the same data line DATA 0~DATA 3, the control signal CNTRL 0~CNTRL 3,
Select a particular bank of VRAM to write the pixel to. Assuming that pixel information can be used simultaneously for all data lines,
It can be written simultaneously to four VRAM locations on the horizon. This is clearly a very quick action. Similarly, pixel information describing a horizontal line can be read from the random access port in the same rapid manner.

To supply pixels for display, a pixel counter 24 multiplexes select signals P0 and P1 with multiplexer 2.
Supply to 6. Multiplexer 26 provides a specific 4
Pixels from four VRAM banks are received simultaneously for one pixel horizontal segment. The signals P0 and P1 from the pixel counter 24 are transferred to a digital-to-analog (D / A) converter circuit 28, which in turn causes the multiplexer 26 to sequentially select the pixels for display in a manner well known in the art. .

When writing to the frame buffer 20 of FIG. 3 to draw a vertical line, each pixel location must be addressed individually since the pixel locations are in the same VRAM bank. Therefore, the simultaneous availability of data on the four data lines DATA 0-3 does not speed up writing vertical lines to the frame buffer. The reason is that only one VRAM is written. Reading information describing a vertical line through the random access port of its frame buffer 20 is performed in much the same manner.
The reason is that the same means is used. Therefore, the time required to access information for drawing a vertical line through the random access port of the frame buffer 20 is much slower than the access time required for drawing a horizontal line.
No.

FIG. 4 is a diagram showing a pattern which enables pixel information to be stored in a VRAM bank constituting a frame buffer according to the present invention. Using this pattern, information describing a vertical line can be stored in the VRAM bank faster than in the configuration shown in FIG. In the figure, letter A is used to indicate a pixel stored in a first VRAM bank, letter B is used to indicate a pixel stored in a second VRAM bank, and letter C is used to indicate a third VRA.
The letter D is used to indicate a pixel stored in the M bank, and the letter D is used to indicate a pixel stored in the fourth VRAM bank.

As can be seen from this pattern, the pixels within the horizontal line to be presented to the output display are stored in the same order as in the prior art above, except that certain lines begin with different pixels. However, the pixel that draws a vertical line has a completely different pattern from the conventional configuration. In fact, the pixels that draw the vertical lines are VRAMs in which each pixel in the four pixel columns is different.
In the order included in the bank. This is true for any four pixels in the vertical column, as can be seen from the lines surrounding some such sequences in FIG.

Pixels in a vertical column of four pixels have the same VRA
Since they do not enter the M bank, the writing to the frame buffer and the access of the frame buffer via the random access port for reading from the frame buffer are superimposed, and their operation speed and vertical line The operation speed of drawing can be improved.

Providing a frame buffer storage pattern as shown in FIG. 4 such that a pixel in a vertical line is not adjacent to another pixel in a line stored in the same VRAM bank stores the pixel. examine the number of lines, and the turn of the line
This can be done by a circuit that aligns those pixels according to the signal. FIG. 5 illustrates, in order to enjoy the benefits of the present invention,
FIG. 3 is a block diagram showing a circuit 30 for controlling access to a VRAM bank in a frame buffer. As can be seen, FIG. 5 includes other circuits in addition to those included in the circuit shown in FIG.

The circuit accesses the correct address in the frame buffer to store the pixel information in accordance with the diagram shown in FIG. 4, reads the pixel information through a random access port, and displays the information on a display device. Used to write to Here, the circuit 30
Although only four individual VRAM banks (VA, VB, VC, VD) are described in the pattern shown in FIG. 4 in the frame buffer circuit 30 of FIG. 5 , different numbers of VRAM banks can be employed. For example, eight banks of VRAM can be used in the frame buffer for faster access. However, the details of such a configuration are felt to outweigh the benefits of the understanding so performed with only the four banks shown in this description. VRAM
Those skilled in the art will understand how to modify the circuit to increase the number of banks.

The circuit 30 of FIG. 5, in addition to that shown in the circuit of FIG. 3, allows data describing a particular pixel to be stored in the VRAM bank of the frame buffer 30.
To enable state appropriate VRAM bank, and a gate circuit 32 to replace the normal control signal CNTRL 0~CNTRL 3. Circuit 30, a bidirectional swapping circuit Ruge over preparative to transfer data to and from appropriate VRAM banks to provide the storage pattern shown in FIG. 4 3
4 is also included. In addition to being that circuitry used to access <br/> scan the random access port of the circuit 30, first to operate the multiplexer 39 to return data describing to its original order of pixels to be sent to the display device One pair of XOR gates 35 and 36 and a line counter circuit 37 are used.

The operation of the circuit 30 for storing pixels according to the pattern shown in FIG. 4 will now be described. To write to the frame buffer, the X and Y addresses of the pixel are supplied to the X and Y address lines, respectively. It should be noted that the X address is all the same for each of the four adjacent bit positions, while the Y address increases by one for each line. The reason is that, in the preferred embodiment device, four 8-bit pixel values are
This is because the data can be transferred in a 2-bit word. 4 consecutive 8
Bit pixels can be formed from words having the same X address
You . The two lower digits of the Y address forming the pattern shown in FIG. 2 are shown to the left of the pattern.

The address provided is the address provided in a typical device and is the address provided to the X and Y address lines in circuit 30 of the present invention. Also, the data supplied to describe the pixels at each location appears on the DATA0-DATA3 data lines in the same order as in the conventional circuit 20. These four pixel values can appear in one address data word and address adjacent pixel locations. To do this, they are divided into 8-bit groups. 8 of them
The bit group is placed on four adjacent data lines DATA0 to DATA3. In this way, four pixels can be stored simultaneously as described above.

An address usually places pixel data at a location at the intersection of any two such addresses, as in the pattern of FIG. However, unlike circuit 20 of FIG. 3, circuit 30 places its data in the pattern shown in FIG. 4 instead of the expected intersection of addresses. To do this, two bits from the least significant of the Y address are used to actuate the swapper circuits 32 and 34. With address shown, Oite the beginning of the line the total
It can be seen that all Y addresses end in binary 00 . Therefore, the selection terminals S0 and S0 of the swapper circuits 32 and 34
The value at 1 transfers the value shown in the truth table of FIG. From the truth table, it can be seen that the Y0 and Y1 values for each vertical line are shown on the left. Immediately to the right is the selection value supplied to the selection terminals of the swapper circuits 32 and 34. The data terminals are shown on the right. Input signals appear at those data terminals, and above each data terminal the generated enable signal is shown, thus the bank to which the data is sent.

Thus, for a four pixel horizontal line starting at address 00,00, the truth table of FIG. 5 shows that the first pixel selected appears on DATA 0 and the first control signal A
Sends that pixel to the VRAM bank. The selected second pixel appears on DATA 1 and a second control signal B sends the pixel to VRAM bank B. The selected third pixel appears on DATA 2 and the third control signal C sends the pixel to VRAM bank C. The selected fourth pixel is DA
At TA3, a fourth control signal D causes the pixel to
Send to M bank D. Since their pixel data values appear simultaneously in one data word, they are stored simultaneously in four banks of VRAM. Thus, the four pixels of the horizontal line are placed in their standard order.

However, the least significant bits of the Y address value for any vertical column will change in a pattern of 0101 for Y0 and 0011 for Y1 as the vertical line moves down from address 00,00. Thus, the value selected and generated by the two lower digits of the Y address for the pixels in the first vertical column is the vertical line at address 0
It changes as it moves down from 0:00. Therefore,
For a 4-pixel vertical line starting at addresses 00, 00,
The truth table of FIG. 5 shows that the selected first pixel is DATA
Appearing at 0, the first control signal A sends the pixel to the VRAM bank VA.

The selected second pixel appears on DATA 0, and a second control signal C causes the pixel to be transferred to the VRAM bank VC.
Send to The selected third pixel appears on DATA 0,
A third control signal B sends the pixel to the VRAM bank VB. The selected fourth pixel appears on DATA 0 and the fourth
Sends the pixel to the VRAM bank VD.
Thus, a four pixel vertical line is placed at the position shown for the first column in FIG.

Although the additional vertical and horizontal lines can be examined using the truth table of FIG. 5, it will be apparent that the pattern of FIG. 4 is generated for a standard input address.

Similarly, values are supplied from the display line counter and the pixel counter to the XOR gates 35 and 36, and are sequentially supplied to the display device when they are arranged in series on the line 0 of the multiplexer 39 according to the pattern of FIG. Produce an output value that controls multiplexer 41 so that the values are in regular ABCD order as in a typical buffer configuration.

As can be seen from the above description,
The circuit of the present invention functions to place pixel data in the pattern shown in FIG. Since the pattern enables superimposition of access when writing a vertical line to the frame buffer, access to the frame buffer when drawing a vertical line on the output display device becomes quick. It can be seen from FIG. 4 that the multiple diagonals depicted require sequential access of the same VRAM bank, but there is no vertical line to do so.
The display speed is expected to increase sharply, since it is much more than the diagonal that appears statistically on the display in a windowed environment. Without interleaving, there is no sequence of four pixels even on the diagonal. Therefore, it is expected that the performance will improve three to four times. Thus, the map of chip select lines provided by the present invention greatly improves the performance of vertical lines without giving up horizontal performance.

[Brief description of the drawings]

FIG. 1 is a diagram showing the arrangement of individual VRAMs in a frame buffer associated with an output display device.

FIG. 2 is a diagram illustrating a pattern for selecting a VRAM to present pixels in a typical arrangement according to the prior art.

FIG. 3 is a VRAM in a prior art frame buffer.
FIG. 3 is a block diagram showing a circuit for controlling access to the data.

FIG. 4 is a diagram illustrating a pattern for selecting a VRAM to present pixels in a typical arrangement, in accordance with the present invention.

FIG. 5 is a block diagram showing a circuit for controlling access to a VRAM in the frame buffer of the present invention.

[Explanation of symbols]

 Reference Signs List 20 frame buffer 22, 26, 39 multiplexer 24 pixel counter 28 A / D converter 37 line counter 32 swapper circuit 34 bidirectional swapper

──────────────────────────────────────────────────続 き Continued on the front page (73) Patentee 591064003 901 SAN ANTONIO ROAD PALO ALTO, CA 94303, U.S.A. S. A. (56) References JP-A-63-67655 (JP, A) JP-A-2-288924 (JP, A) L. Ostapko, 'A mapping and memory chip hardware (58) Fields investigated (Int. Cl. ⁷ , DB name) G09G 5/00-5/42 G06F 12/00-12/08 G06T 1/60 450

Claims (4)

(57) [Claims] 1. An image display device comprising a frame buffer for storing data of a plurality of pixels each having an X address and a Y address, wherein the frame buffer is configured as a plurality of VRAM banks and each VR
The AM bank has a control input and a data input, and the frame buffer has a multiplexer and a pixel counter, and is a VRAM access circuit of a display device arranged to display data from the VRAM bank. Means for selectively mapping pixel data to the VRAM under the control of the VRAM, and a plurality of control signals to the VRAM under the control of the second selection.
Means for mapping to the control input of the bank; counter means for generating a plurality of line signals indicating the line number of the output pixel when the output pixels are arranged from the frame buffer; and receiving the line signal and the pixel counter Logic means for receiving a plurality of pixel number signals from a plurality of pixel signals and generating a plurality of multiplexer selection signals coupled to a multiplexer for arranging the pixel data to be displayed, wherein said pixel data is selectively stored in said VRAM bank. A VRAM access circuit characterized by being mapped. 2. The VRAM access circuit according to claim 1, wherein said first selection and said second selection are respectively coupled to lower bits of a Y address of said pixel. 3. An image display device comprising a frame buffer for storing data of a plurality of pixels each having an X address and a Y address, wherein said frame buffer is configured as a plurality of VRAM banks,
The AM bank has a control input and a data input, and the frame buffer has a multiplexer and a pixel counter, and is a VRAM access circuit of a display device arranged to display data from the VRAM bank. First swapping means coupled to receive pixel data for the pixel to be transmitted and to send the pixel data to the VRAM bank, wherein the pixel data comprises:
A first input, a second input, a third input, and a fourth input that are mapped to a first output, a second output, a third output, and a fourth output according to states of the pair of first selection signals; The first output is coupled to a data input of a first VRAM bank, the second output is coupled to a data input of a second VRAM bank, the third output is coupled to a data input of a third VRAM bank, and the fourth output is A first swapping means coupled to a data input of a 4 VRAM bank; a second swapping means coupled to receive control signals of four adjacent pixels and to transmit the control signals to the VRAM bank; The control signal includes a fifth input mapped to a fifth output, a sixth output, a seventh output, and an eighth output according to a state of the pair of second selection signals;
A sixth input, a seventh input, an eighth input,
An output is coupled to a data input of a first VRAM bank, the sixth output is coupled to a data input of a second VRAM bank, the seventh output is coupled to a data input of a third VRAM bank, and the eighth output is coupled to a fourth VRAM bank. Second swapping means coupled to the data input of the counter; and when the output pixels are sequentially sent from the frame buffer, counter means for generating a pair of line signals indicating a line number for the output pixels; and Logic means for receiving a signal and receiving a pair of pixel numbers and generating a pair of multiplexer selection signals for the multiplexer.
The pixel data of the four adjacent pixels is the four VRs.
VRAM access circuit selectively mapped to AM bank. 4. A method for accessing a VRAM in an image display device having a frame buffer configured as a plurality of VRAM banks, each storing a plurality of pixels having an X address and a Y address, the method comprising: First pixel, second pixel, third for four pixels
Receiving pixel data including a pixel and a fourth pixel;
Selectively swapping the pixel data into a VRAM bank, a second VRAM bank, a third VRAM bank, and a fourth VRAM bank, receiving a first control signal, a second control signal, a third control signal, and a fourth control signal; Control signal, second control signal, third control signal, fourth control signal
A control signal is applied to the control input of the first VRAM bank,
Selectively swaps to the control input of the RAM bank, the control input of the third VRAM bank, and the control input of the fourth VRAM bank, and generates a pair of line signals indicating the line number of the output pixel when the output pixel is sequentially sent from the frame buffer. And generating a pair of pixel number signals, wherein the first VRAM bank, the second VRAM bank, and the third
The pixel data is read from the RAM bank and the fourth VRAM bank according to the state of the line signal and the pixel number, and the pixel data of the four adjacent pixels is changed to the four VRs.
A method of accessing a VRAM selectively mapped to an AM bank.