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JPH02240955A - Lead frame for semiconductor device - Google Patents

Lead frame for semiconductor device

Info

Publication number
JPH02240955A
JPH02240955A JP6086989A JP6086989A JPH02240955A JP H02240955 A JPH02240955 A JP H02240955A JP 6086989 A JP6086989 A JP 6086989A JP 6086989 A JP6086989 A JP 6086989A JP H02240955 A JPH02240955 A JP H02240955A
Authority
JP
Japan
Prior art keywords
resin
rear surface
substrate supporting
supporting part
lead frame
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6086989A
Other languages
Japanese (ja)
Inventor
Joji Nakane
譲治 中根
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP6086989A priority Critical patent/JPH02240955A/en
Publication of JPH02240955A publication Critical patent/JPH02240955A/en
Pending legal-status Critical Current

Links

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To alleviate stress concentration and to control the occurrence of cracks by performing corner chamfering on the rear surface side of the outer edge part of a substrate supporting part. CONSTITUTION:Corner chamfering 1b is performed to the corner of the rear surface side of the outer edge of a substrate supporting part 1. The corner chamfering 1b of the rear surface of the substrate supporting part 1 is achieved only by changing the mask pattern of the rear surface forming a lead frame into the size smaller than the mask pattern of the upper surface by etching effect. Even if residual tensile stress due to the difference in thermal expansion coefficients of the a resin 4 and the substrate supporting part 1 is generated in the resin 4 in the vicinity of the rear surface of the substrate supporting part 1 at the trim of resin sealing, the stress concentration at the outer surface part is alleviated. Thus, the occurrence of cracks can be suppressed.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は、樹脂封止形半導体装置に用いられるリードフ
レームに関するものである。
DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a lead frame used in a resin-sealed semiconductor device.

(従来の技術) 一般に、半導体チップは、量産性、コストパフォーマン
スの点から樹脂材料を用いた封止方法が用いられている
(Prior Art) Generally, a sealing method using a resin material is used for semiconductor chips in terms of mass productivity and cost performance.

従来の樹脂封止形半導体装置について、第2図の要部断
面図により説明する。
A conventional resin-sealed semiconductor device will be explained with reference to a cross-sectional view of a main part in FIG.

従来の樹脂封止形半導体装置は、鋼板をプレス加工また
はエツチング加工して基板支持部lおよびリード端子部
2を有するリードフレームを形成し、上記の基板支持部
1に銀ペーストあるいは金の共晶により半導体チップ3
を装着した後、上記のリード端子部2の末端部を含め樹
脂4で封止し、さらに樹脂4から突出したリード端子部
2を所定の形状に折曲げ成形したものである。
In a conventional resin-sealed semiconductor device, a lead frame having a substrate support part l and a lead terminal part 2 is formed by pressing or etching a steel plate, and the substrate support part 1 is coated with silver paste or gold eutectic. Semiconductor chip 3
After mounting, the end portion of the lead terminal portion 2 is sealed with a resin 4, and the lead terminal portion 2 protruding from the resin 4 is bent into a predetermined shape.

(発明が解決しようとする課M) しかしながら、上記の構成では、リードフレームがプレ
スによる打抜き加工や型を用いたエツチングで形成され
るため、基板支持部1の外周端は面取りのない、鋭角1
aとなっている。
(Problem M to be Solved by the Invention) However, in the above configuration, since the lead frame is formed by punching with a press or etching using a mold, the outer peripheral edge of the substrate support portion 1 has an acute angle 1 without a chamfer.
It is a.

さらに、す・〒ドフレーム、半導体チップ3および樹脂
4の熱膨張係数を比較すると、42−アロイを用いたリ
ードフレームは4.14 X 10−” 、シリコン基
板の半導体チップは2.4 X 10−’に対し、樹脂
は約170 X tG″′と極めて大きいため、樹脂封
止の工程で基板支持部1の裏面に接する周辺部に引張り
の残留応力が発生し、しかも上記の外周端の鋭角laに
よるエツジ効果で応力が集中してひび割れが発生し、甚
しい場合には隙間が発生して半導体装置の耐湿性を著し
く低下させるという問題があった・ さらに、半導体チップ3が大きくなる程、ひび割れや隙
間の発生が顕著になるという問題があった。
Furthermore, when comparing the thermal expansion coefficients of the lead frame, semiconductor chip 3, and resin 4, the lead frame using 42-alloy has a coefficient of 4.14 x 10-", and the semiconductor chip using a silicon substrate has a coefficient of 2.4 x 10". -', the resin is extremely large at approximately 170 X tG"', so tensile residual stress is generated in the peripheral area that contacts the back surface of the substrate support part 1 during the resin sealing process, and the acute angle of the outer peripheral edge mentioned above is generated. There was a problem in that stress was concentrated due to the edge effect caused by la and cracks were generated, and in severe cases, gaps were generated, significantly reducing the moisture resistance of the semiconductor device.Furthermore, as the semiconductor chip 3 becomes larger, There was a problem in that the occurrence of cracks and gaps became noticeable.

本発明は上記の問題を解決するもので、応力集中が発生
しない半導体装置用リードフレームを提供するものであ
る。
The present invention solves the above problems and provides a lead frame for a semiconductor device in which stress concentration does not occur.

(課題を解決するための手段) 上記の課題を解決するため1本発明は、基板支持部の外
周部裏面側に角面取を施すものである。
(Means for Solving the Problems) In order to solve the above problems, one aspect of the present invention is to chamfer a corner on the back side of the outer peripheral portion of the substrate support portion.

(作 用) 上記の構成により、エツジ効果により残留引張り応力が
集中する基板支持部の外周部の裏面側に面取が施される
ので、応力集中が大幅に緩和され、ひび割れの発生が抑
制される。
(Function) With the above configuration, the back side of the outer periphery of the substrate support part where residual tensile stress is concentrated due to the edge effect is chamfered, so the stress concentration is significantly alleviated and the occurrence of cracks is suppressed. Ru.

(実施例) 本発明の一実施例を第1図の要部断面図により説明する
(Example) An example of the present invention will be described with reference to a sectional view of the main part in FIG.

同図に示す本実施例が、第2図に示した従来例と異なる
点は、基板支持部の外周端と裏面の角に角面取1bを施
したことである。その他は従来例と変わらないので、同
じ構成部品には同一符号を付してその説明を省略する。
The present embodiment shown in the same figure differs from the conventional example shown in FIG. 2 in that corner chamfers 1b are applied to the outer circumferential edge of the substrate support portion and the corners of the back surface. Since the rest is the same as the conventional example, the same components are given the same reference numerals and their explanations will be omitted.

なお、基板支持部1裏面の角面取1bは、エツチング加
工でリードフレームを形成する裏面のマスクパターンを
表面のマスクパターンより小さくする変更のみでよい。
Note that the corner chamfer 1b on the back surface of the substrate support portion 1 may be changed only by making the mask pattern on the back surface, on which the lead frame is formed by etching, smaller than the mask pattern on the front surface.

上記のように構成することによって、基板支持部1の裏
面近傍の樹脂4に残留引張り応力が発生しても、外周部
に角面取1bが施されているため、応力集中が大幅に緩
和されるので、ひび割れを発生することがない。
With the above configuration, even if residual tensile stress occurs in the resin 4 near the back surface of the substrate support part 1, the stress concentration is significantly alleviated because the outer peripheral part is chamfered 1b. Therefore, cracks will not occur.

(発明の効果) 以上説明したように、本発明のリードフレームは、基板
支持部裏面外周部に角面取が施されているため、樹脂封
止時に樹脂と基板支持部の熱膨張係数の差による残留引
張り応力が発生しても、基板支持部裏面外周部に大きな
集中応力が発生することがなくなる。従って、樹脂のひ
び割れに起因する耐湿性低下が発生しないので、信頼性
の高い樹脂封止形半導体装置を得ることができる。
(Effects of the Invention) As explained above, in the lead frame of the present invention, since the outer periphery of the back surface of the substrate support portion is chamfered, there is a difference in the coefficient of thermal expansion between the resin and the substrate support portion during resin sealing. Even if residual tensile stress is generated due to this, a large concentrated stress will not be generated at the outer periphery of the back surface of the substrate support portion. Therefore, a highly reliable resin-sealed semiconductor device can be obtained since moisture resistance does not deteriorate due to cracks in the resin.

【図面の簡単な説明】[Brief explanation of drawings]

第1図および第2図は本発明の一実施例および従来例を
それぞれ示す樹脂封止形半導体装置の要部断面図である
。 1・・・基板支持部、  la・・・鋭角、1b・・・
角面取、 2・・・リード端子部、 3・・・半導体チ
ップ、 4・・・樹脂。 第 1 因 4 樹脂 特許出願人 松下電子工業株式会社
1 and 2 are sectional views of essential parts of resin-sealed semiconductor devices showing an embodiment of the present invention and a conventional example, respectively. 1... Board support part, la... Acute angle, 1b...
Corner chamfer, 2... Lead terminal portion, 3... Semiconductor chip, 4... Resin. No. 1 Cause 4 Resin patent applicant Matsushita Electronics Co., Ltd.

Claims (1)

【特許請求の範囲】[Claims] 基板支持部の裏面外周部に角面取を施したことを特徴と
する半導体装置用リードフレーム。
A lead frame for a semiconductor device, characterized in that the outer periphery of the back surface of the substrate support part is chamfered.
JP6086989A 1989-03-15 1989-03-15 Lead frame for semiconductor device Pending JPH02240955A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6086989A JPH02240955A (en) 1989-03-15 1989-03-15 Lead frame for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6086989A JPH02240955A (en) 1989-03-15 1989-03-15 Lead frame for semiconductor device

Publications (1)

Publication Number Publication Date
JPH02240955A true JPH02240955A (en) 1990-09-25

Family

ID=13154826

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6086989A Pending JPH02240955A (en) 1989-03-15 1989-03-15 Lead frame for semiconductor device

Country Status (1)

Country Link
JP (1) JPH02240955A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2019116457A1 (en) * 2017-12-13 2019-06-20 三菱電機株式会社 Semiconductor device and power conversion device

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2019116457A1 (en) * 2017-12-13 2019-06-20 三菱電機株式会社 Semiconductor device and power conversion device
JPWO2019116457A1 (en) * 2017-12-13 2020-05-28 三菱電機株式会社 Semiconductor device and power converter
CN111448653A (en) * 2017-12-13 2020-07-24 三菱电机株式会社 Semiconductor device and power conversion device
US11257768B2 (en) 2017-12-13 2022-02-22 Mitsubishi Electric Corporation Semiconductor device and power conversion device
CN111448653B (en) * 2017-12-13 2024-05-24 三菱电机株式会社 Semiconductor device and power conversion device
DE112017008277B4 (en) 2017-12-13 2025-03-13 Mitsubishi Electric Corporation SEMICONDUCTOR DEVICE AND POWER CONVERSION DEVICE

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