JPH0613526A - Lead frame for semiconductor device and manufacturing method thereof - Google Patents
Lead frame for semiconductor device and manufacturing method thereofInfo
- Publication number
- JPH0613526A JPH0613526A JP16784192A JP16784192A JPH0613526A JP H0613526 A JPH0613526 A JP H0613526A JP 16784192 A JP16784192 A JP 16784192A JP 16784192 A JP16784192 A JP 16784192A JP H0613526 A JPH0613526 A JP H0613526A
- Authority
- JP
- Japan
- Prior art keywords
- lead frame
- semiconductor device
- die pad
- chamfered portion
- manufacturing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 14
- 238000004519 manufacturing process Methods 0.000 title claims 3
- 238000000034 method Methods 0.000 claims abstract description 9
- 238000005530 etching Methods 0.000 claims abstract description 7
- 238000003825 pressing Methods 0.000 claims abstract description 6
- 229920005989 resin Polymers 0.000 claims abstract description 5
- 239000011347 resin Substances 0.000 claims abstract description 5
- 239000002184 metal Substances 0.000 claims abstract description 4
- 238000000465 moulding Methods 0.000 claims abstract 2
- 239000000758 substrate Substances 0.000 abstract description 3
- 230000008642 heat stress Effects 0.000 abstract 1
- 230000035882 stress Effects 0.000 description 7
- 238000010586 diagram Methods 0.000 description 3
- 238000003672 processing method Methods 0.000 description 2
- 230000008646 thermal stress Effects 0.000 description 2
- 239000012141 concentrate Substances 0.000 description 1
- 229920006332 epoxy adhesive Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
(57)【要約】
【目的】半導体装置を基板実装する際に、熱ストレスが
ダイパット辺部に集中することを防ぎ、樹脂モールド部
にクラックが発生することを防止できる構造の半導体装
置用リードフレームを提供する。
【構成】ICチップとリードフレームと金属細線とを覆
うように樹脂モールドして組立てる半導体装置におい
て、前記リードフレームのダイパット辺部の少なくとも
一部分には面取り部を形成し、この面取り部をエッチン
グ法またはプレス法で行なう構成の半導体装置用リード
フレーム。
(57) [Abstract] [Purpose] When mounting a semiconductor device on a substrate, a lead frame for a semiconductor device having a structure capable of preventing heat stress from concentrating on the side of the die pad and preventing a crack from being generated in the resin mold part. I will provide a. In a semiconductor device assembled by resin molding so as to cover an IC chip, a lead frame and a thin metal wire, a chamfered portion is formed on at least a part of a die pad side portion of the lead frame, and the chamfered portion is formed by an etching method or A lead frame for a semiconductor device, which is constructed by a pressing method.
Description
【0001】[0001]
【産業上の利用分野】本発明は、半導体装置用リードフ
レームの構造に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a lead frame structure for semiconductor devices.
【0002】[0002]
【従来の技術】ICチップをプラスチックパッケージに
組立てる場合の一般的構造は、図3のように、ダイパッ
ト1上にICチップ2をエポキシ系接着材などで固定
し、パッド電極3とリード電極4を金属細線5で接続
し、しかる後にこれらを覆うように樹脂モールド6を施
すものであった。2. Description of the Related Art A general structure for assembling an IC chip into a plastic package is as shown in FIG. 3 in which the IC chip 2 is fixed on a die pad 1 with an epoxy adhesive and the pad electrode 3 and the lead electrode 4 are connected. The metal thin wires 5 were connected, and then the resin mold 6 was applied so as to cover them.
【0003】[0003]
【発明が解決しようとする課題】しかし、前述の従来技
術の図3に示す構造では、ダイパット辺部7に突起が生
じやすく基板実装する際に熱ストレスにより突起部に応
力が集中し、この部分からクラック8が発生するという
問題を有する。However, in the structure shown in FIG. 3 of the prior art described above, protrusions are likely to occur on the die pad side portion 7, and stress is concentrated on the protrusion portion due to thermal stress when mounting on a substrate. Therefore, there is a problem that cracks 8 are generated.
【0004】本発明は、この様な問題を解決するもの
で、その目的とするところは、ダイパット辺部における
応力集中を防止し、クラックの生じ難い半導体装置用リ
ードフレームを提供するところにある。The present invention solves such a problem, and an object of the present invention is to provide a lead frame for a semiconductor device in which stress concentration at the side of the die pad is prevented and cracks hardly occur.
【0005】[0005]
【課題を解決するための手段】本発明の半導体装置用リ
ードフレームは、リードフレームのダイパット辺部の少
なくとも一部分には面取り部を形成した事また面取り部
の形成をエッチング法またはプレス法により行なう事を
特徴とする。In a lead frame for a semiconductor device according to the present invention, a chamfered portion is formed on at least a part of a die pad side portion of the lead frame, and the chamfered portion is formed by an etching method or a pressing method. Is characterized by.
【0006】[0006]
【実施例】図1は本発明の実施例の模式図である。なお
前述の従来例と同一部分には同じ符号を付してある。1 is a schematic view of an embodiment of the present invention. The same parts as those in the conventional example described above are designated by the same reference numerals.
【0007】前述のように、基板実装する際の熱ストレ
スは、構造上ダイパット辺部7に集中しやすい。この場
合、辺部7にはリードフレームの加工の過程で突起が生
じやすいため更に応力集中の度合が高まる。そのため突
起を起点としてクラック8が生ずる。As described above, the thermal stress when mounting on a substrate tends to concentrate on the die pad side portion 7 due to its structure. In this case, the side portions 7 are likely to have protrusions during the process of processing the lead frame, so that the degree of stress concentration is further increased. Therefore, the crack 8 is generated starting from the protrusion.
【0008】しかし、辺部7に図1の9または図2の1
0に示す様な面取りを形成することにより辺部への著し
い応力集中を低減する事が可能でこの事によりパッケー
ジクラックを大幅に減少させることが出来る。However, the side portion 7 is provided with 9 in FIG. 1 or 1 in FIG.
By forming a chamfer as shown in 0, it is possible to reduce the remarkable stress concentration on the side portion, and this can greatly reduce the package cracks.
【0009】辺部への応力集中はダイパットの上側の4
辺にも、又、下側にも起こる。従って、これらダイパッ
トの8つの辺に面取り部を施す事が望ましい。The stress concentration on the side is 4 at the upper side of the die pad.
It happens on the sides and on the bottom. Therefore, it is desirable to chamfer the eight sides of these die pads.
【0010】しかし、下側の4辺には上側の4辺よりも
高い応力集中が生じやすいため、下側の4辺を優先的に
面取りを施すことが望ましい。However, since stress concentration is more likely to occur on the lower four sides than on the upper four sides, it is desirable to chamfer the lower four sides preferentially.
【0011】図1に示すような面取り形状はリードフレ
ームをエッチング加工する際に予め面取り部9のみを部
分的にエッチングし、その後でリードフレームの板厚分
を貫通するように通常のエッチングを行う事により得ら
れるものである。In the chamfered shape as shown in FIG. 1, only the chamfered portion 9 is partially etched in advance when the lead frame is etched, and then the normal etching is performed so as to penetrate the lead frame by the plate thickness. It is obtained by the thing.
【0012】上に述べた部分的エッチングの程度を適切
に調整することにより面取り部の大きさを目的の大きさ
に合わせ込むことができる。By appropriately adjusting the degree of the partial etching described above, the size of the chamfered portion can be adjusted to the target size.
【0013】図2は本発明の実施例における別の模式図
を示すものである。即ち、プレス加工によって面取り部
10を形成したものである。リードフレームをプレス加
工する前に予め面取り部10のみに部分的に圧力を加え
面取り部を形成しておいてその後にこの部分を切断する
ことによって所定の形状が得られる訳である。FIG. 2 shows another schematic diagram in the embodiment of the present invention. That is, the chamfered portion 10 is formed by pressing. Before the lead frame is pressed, only the chamfered portion 10 is partially pressurized in advance to form the chamfered portion, and then this portion is cut to obtain a predetermined shape.
【0014】リードフレームの加工法については、電極
数と加工数量によりエッチング方またはプレス方が選ば
れる。これに合わせて面取りの形成方法も図1又は図2
の説明の通りにほぼ定まってくる。Regarding the processing method of the lead frame, the etching method or the pressing method is selected depending on the number of electrodes and the number of processing. In accordance with this, the chamfer forming method is also shown in FIG.
It is almost fixed as explained.
【0015】以上に示すものは実施例でありその加工方
法を規制するものではない。What has been described above is an embodiment, and the processing method thereof is not restricted.
【0016】[0016]
【発明の効果】以上に述べたように本発明によれば、リ
ードフレームのダイパット辺部の少なくとも一部にエッ
チング法またはプレス法により面取り部を形成した事に
よりダイパット辺部への応力集中を防ぐことができ、ク
ラックの発生を大幅に低減できるという効果を有する。As described above, according to the present invention, the chamfered portion is formed on at least a part of the die pad side portion of the lead frame by an etching method or a pressing method, so that stress concentration on the die pad side portion can be prevented. Therefore, it is possible to significantly reduce the occurrence of cracks.
【図1】本発明の半導体装置用リードフレームの一実施
例を示す模式図。FIG. 1 is a schematic view showing an embodiment of a lead frame for a semiconductor device of the present invention.
【図2】本発明の半導体装置用リードフレームの他の実
施例を示す模式図。FIG. 2 is a schematic diagram showing another embodiment of the lead frame for a semiconductor device of the present invention.
【図3】従来の半導体装置リードフレームの模式図。FIG. 3 is a schematic diagram of a conventional semiconductor device lead frame.
1:ダイパット 2:ICチップ 3:パッド電極 4:リード電極 5:金属細線 6:樹脂モールド 7:ダイパット辺部 8:クラック 9:面取り部 10:面取り部 1: Die pad 2: IC chip 3: Pad electrode 4: Lead electrode 5: Metal thin wire 6: Resin mold 7: Die pad side part 8: Crack 9: Chamfer part 10: Chamfer part
Claims (3)
とを覆うように樹脂モールドして組立てる半導体装置に
おいて、前記リードフレームのダイパット辺部の少なく
とも一部分には面取り部を形成した事を特徴とする半導
体装置用リードフレーム。1. A semiconductor device assembled by resin molding so as to cover an IC chip, a lead frame and a thin metal wire, wherein a chamfered portion is formed on at least a part of a die pad side portion of the lead frame. Lead frame for equipment.
特徴とする請求項1記載の半導体装置用リードフレーム
の製造方法。2. The method for manufacturing a lead frame for a semiconductor device according to claim 1, wherein the chamfered portion is formed by an etching method.
とする請求項1記載の半導体装置用リードフレームの製
造方法。3. The method for manufacturing a lead frame for a semiconductor device according to claim 1, wherein the chamfered portion is formed by a pressing method.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16784192A JPH0613526A (en) | 1992-06-25 | 1992-06-25 | Lead frame for semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16784192A JPH0613526A (en) | 1992-06-25 | 1992-06-25 | Lead frame for semiconductor device and manufacturing method thereof |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0613526A true JPH0613526A (en) | 1994-01-21 |
Family
ID=15857076
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP16784192A Pending JPH0613526A (en) | 1992-06-25 | 1992-06-25 | Lead frame for semiconductor device and manufacturing method thereof |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0613526A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007516952A (en) | 2003-12-26 | 2007-06-28 | 日産化学工業株式会社 | Crystalline form of quinoline compound and process for producing the same |
-
1992
- 1992-06-25 JP JP16784192A patent/JPH0613526A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007516952A (en) | 2003-12-26 | 2007-06-28 | 日産化学工業株式会社 | Crystalline form of quinoline compound and process for producing the same |
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