JPH02236899A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To enable high integration by setting a voltage, which is lower among voltages applied to memory elements, lower than a voltage applied to a peripheral circuit. CONSTITUTION:An external voltage Vcc is inputted to a substrate voltage generating circuit 20, which generates, for example, -3V as the bias voltage of a substrate 10. The degree of integration of a memory is determined normally by the degree of integration of a circuit part 40 consisting of the peripheral circuit connected directly to a memory array. For the purpose, the operating voltage of an MOSFETQm is lowered to reduce the size of the FETQm. The circuit 50 consisting of other control circuits, i.e. circuits controlling peripheral circuits directly, on the other hand, occupies the total area of the chip by about 10%, so an MOSFET of small size need not be used specially. Therefore, an MOSFETQp of large size is used to set the drain voltage of the FETQp to the voltage Vcc higher than the drain voltage VDP of the FETQm. Consequently, the voltage Vcc is used as the operating voltage to enable the FETs Qp and Qm to operate.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a high-density integrated circuit, and particularly to an integrated circuit suitable for a high-density semiconductor memory.

[Conventional technology]

Conventionally, in order to achieve high integration of semiconductor memory, Japanese Patent Application Laid-Open No. 1986-
No. 104276 proposes a technique that combines two types of gate oxide film thicknesses and two types of gate region surface concentrations. Furthermore, Japanese Patent Application Laid-Open No. 50-119543 discloses that by implanting ions into the Si surface of a part of the memory array at a high concentration, the channel length of the transistor in the memory array can be made smaller, and the distance between the diffusion layers can be made smaller. Techniques to improve the degree of integration have been proposed. [Problems to be Solved by the Invention] When the dimensions of circuit elements such as transistors are reduced using the above-described techniques, the withstand voltage of these circuit elements against dielectric breakdown becomes smaller. On the other hand, from the user's perspective, there is a desire for the externally applied voltage (the voltage applied to the power supply pin of the memory LSI package) to be constant regardless of the dimensions of the transistors that make up the memory. Therefore, it is not desirable to lower the externally applied voltage. Therefore, with the above-mentioned conventional technology, it is not possible to realize a highly integrated memory that can use a high external voltage. This applies not only to memory but also to other integrated circuits. SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a highly integrated circuit that can use a high external voltage, has small dimensions, and has internal circuit elements that operate at a low operating voltage. [Means for Solving the Problems] In order to achieve the above object, the present invention provides that the power supply voltage applied to these circuit elements or the signal voltage generated by these circuits can be reduced by reducing the dimensions of the circuit elements. Therefore, we decided to make it smaller. That is, the present invention focuses on the following features of integrated circuits. (1) In general, circuit elements connected to external input terminals in an integrated circuit must have a high withstand voltage. This is to prevent this element from being destroyed even if a high voltage is supplied to this terminal from the outside or electrostatic force is generated.
Therefore, it is practically necessary to increase the dimensions of the circuit elements connected to this external input terminal. (2) As mentioned above, the internal circuits of integrated circuits are made smaller in size, and in order to prevent damage even if the withstand voltage is reduced, the power supply voltage supplied to them or the signal generated by them is It is desirable to reduce the voltage value. Considering these points, in the present invention, the circuit elements in the first circuit that respond to large amplitude signals are:
The circuit element of the second circuit, which responds to the output signal of this circuit, is formed with small dimensions to achieve high integration. Further, a power supply circuit including a circuit element having a large size is provided for inputting a high first power supply voltage and supplying a second power supply voltage lower than the first power supply voltage to a second circuit,
The first circuit is configured to receive a first power supply voltage and generate an internal signal having a voltage corresponding to the second power supply voltage. The second circuit is configured to receive the second power supply voltage, be activated by this internal signal, and output a signal having a voltage corresponding to the second power supply voltage. [Function] As a result of the above-described configuration, the problem regarding withstand voltage can be solved in the first and second circuits, and furthermore, since the second circuit is formed of circuit elements with small dimensions, Since the second circuit occupies a large area in the entire integrated circuit, high integration can be achieved when looking at the integrated circuit as a whole. [Examples] The present invention will be explained below based on Examples. FIG. 1 is a cross-sectional view of a memory chip for dynamic memory comprising a P-type substrate 10 to illustrate the concept of this method. The gate oxide film toxz of the N-type MOS transistor (MOST) Qp is MOST, Q. gate oxide film t
Thicker than OXi. A high drain voltage, for example, external voltage Vcc (eg, 5V) is supplied to the drain Dp of MOST, Qp, and drain D.
, an internal power supply voltage generating circuit 30 (actually formed within the substrate 10) to which this voltage VCC is input generates a voltage Vop lower than Vcc (for example, 3
．． 5V) is supplied.

The external voltage Vcc is input to the substrate voltage generation circuit 20,
Here, a bias voltage of, for example, -3V is generated for the substrate 10. Although the circuit 20 is shown outside the substrate 10, it is actually provided inside the substrate 10. Normally, the density of memory is determined by the memory array and peripheral circuits (direct peripheral circuits) that are directly connected to the memory array, such as sense amplifiers (not shown) that drive it or amplify the minute signals output from it. It is determined by the degree of integration of the first circuit section 40 consisting of Therefore, the MOS of this part
T,Q. I want to reduce the size of . This dimension is MOST,
Q. In general, it is possible to reduce the size by lowering the operating voltage, depending on the withstand voltage, hot electrons, substrate current, etc. Here, MOST,Q.
gate? Membrane t. x1 is made thinner, and the drain voltage V c
Set the voltage Vop lower than c and make the channel length short <LM
It has been realized to reduce the dimensions of OST and Q-Y.

Of course, Gate G. Generally, the maximum value of the voltage must also be set to Vop. On the other hand, the second control circuit consists of other control circuits, that is, circuits that directly control peripheral circuits (indirect peripheral circuits).
The area of the circuit section 50 in the entire chip is approximately 10
%, there is no need to use a particularly small MOST. Rather, since this indirect peripheral circuit is connected to an external input terminal, it must have a sufficiently high electrostatic breakdown voltage. For this purpose, it is generally necessary to thicken the gate oxide film tox of the MOST Qp and use a MOST Qp with a correspondingly large dimension (for example, channel length). Here, this gate oxide film 70.

By making Qp thicker than the gate oxide film tax and increasing the channel length, the drain voltage of Qp is increased to Qp. Vcc is higher than the drain voltage Vop of . Of course Gate GP
The maximum value of the voltage is generally Vcc. In addition, Qp
,Q-'s source S,,S. Both are held at ground potential. As shown in FIG. 1, the MOS of the first circuit section 40 consists of a memory array and direct peripheral circuits that affect high integration.
T Q. The dimensions of MOST Qp of the second circuit section 50 consisting of the spaced peripheral circuit are made larger. Further, by doing so, the M O S T and Qp can be operated by using the power supply voltage (Vcc: 5V, for example) from outside the chip as the operating voltage. Also Q. converts Vcc in-chip to lower operating voltage (Vop: for example 3.5
V). Generally, as the operating voltage is lowered by 1, it is desirable to lower V th accordingly in terms of speed. In this regard, from the general characteristics of MOST, as the gate oxide film tox becomes smaller, Vth also becomes lower, so that the operating speed of the first circuit section, which accounts for a large portion of the operating speed of the memory, can be increased. Therefore, this method is advantageous in terms of speeding up. Note that it is clear that vt, can be adjusted as appropriate using ion implantation technology depending on the application. This method uses a one-transistor type memory cell, right? When applied to an actual dynamic N-MOS memory, it can be used more effectively if some considerations are taken.
An example of this is shown in Figure 2. This is a memory with folded data lines. This memory has external power supply voltage V
cc (5 V) is applied to the substrate bias generation circuit 2o of approximately -3V, and external power supply voltage Vcc is applied to generate an internal power supply voltage VDP of 3.5V and a DC voltage V' of approximately 3B. internal power supply generation circuit 3o, external power supply voltage VCC, and external addresses Ai-Aj, Ai' to A
j/external control signal is input, and internal address signal a. ~
aa, al to a4, internal control pulse φ. ,φ■
, φ1, φX, φy and the voltage V
DP+V't address signal a t ” a J , a
t' to a, control pulse φ. , φ■, φ, the memory array MA and the direct peripheral circuit 40 are separated. Direct peripheral circuits include an X decoder XD, a Y decoder YD, a precharge circuit PC, and a sense amplifier SA. In FIG. 2, the circuit 50A is a separate portion of the indirect peripheral circuit 5o that generates word line drive pulses. This circuit 5
In 0A, pulses φ″, φ′X are generated in the indirect peripheral circuit 50. Here, both the external address signal and the external control signal input to the indirect peripheral circuit 50 are as follows. This is a signal that changes between the external power supply voltage Vcc and the ground potential.Among the pulses output from this circuit 50, φlt at~aa, at'
~a, / are both pulses that change between the internal power supply voltage Vop and the ground potential, and the pulse φ. is the precharging transistor Qpt Qp* Qopp Qyo
If p Qxog L/threshold is Vth, then Vop+
This is a pulse that takes a level higher than Vth, and the pulse φ
, is a pulse that takes a level lower than Vop by the threshold value of transistor Q^tQA. In addition, pulse φ8,
φy is approximately 1. This is a pulse that takes the level of 5 Vop.

The operation of this circuit is as follows. The read signal voltage appearing on the data line D from the selected memory cell MC in the memory array MA according to the stored information is read by the sense amplifier SA using the reference voltage appearing on the data line D from the dummy cell DC.
1I O $1 is determined, but ;a8
is as below. That is, each data line pair D, D receives a precharge signal φ. After being precharged to Vop (<Vcc) by φ. is off, D and D are Vop
is maintained. This precharge signal φ. The amplitude of M O S T Q in the data line precharge circuit pc
p= Qp(7) Under the influence of Vth variation,
In order to prevent the precharge levels of D and D from becoming unbalanced (this becomes equivalent noise during reading), 'i' is sufficiently thicker than Vop (> Vop + V th).
Any amplitude is sufficient. Next, the memory cell MC on the selected word line W cleared to Ov during precharging by QCL
In order to read out the word activation pulse φ8' (amplitude is
The external power supply voltage V c c ) is the word voltage generation circuit WG.
is applied to At this time, decoder XD has already received address a.
Since the word driver MOSTQxs is selected by 5~aa, the gate of the word driver MOSTQxs is held at a high level.
In other words, Qxs is turned on. The word voltage generating circuit WG receives a pulse φ8' and outputs a pulse φ8 having an amplitude Vop, and its output φ is directly transmitted from W' to W. In this case, depending on the purpose, for example, MC
In order to increase the voltage applied to W in order to increase the read voltage from D to D, φ, (oscillation Vop) is also applied via the bootstrap capacitor CB. The booster circuit VU receives a pulse φ, (amplitude V c c ) and outputs a pulse φ. The boosted voltage in this case is determined by the parasitic capacitance of the sum of Ca, W', and W and the amplitude of φ1, but approximately 0.5Vop is possible. Therefore W
1. A pulse with an amplitude of about 5 Vop is generated.
At the same time, although not shown in FIG. 2, a pulse voltage of 1.5Vop is generated in the dummy word AtDW by a circuit of almost the same type. As a result, the storage voltage corresponding to the information held in the storage capacitor Cs appears at D as a minute voltage determined by the relationship between Cs and the data line capacitance. On the other hand, the intermediate level (reference voltage) of the signal voltage appearing at D corresponding to the stored information always appears at D, and these
It is amplified by Sense Ambu SA. Furthermore, the amplification is
Vop Vrh (here, Vth is Vt of Q^, Q^) is precharged from data lines D and D.
This is done by changing φ, which becomes h), to Ov. The D, D differential signal amplified in this way is generated when a predetermined Y decoder VD is selected by the addresses a, I~at' (therefore (the gate voltage of hs is at a high level), and the amplitude is ~ 1.5Vop) is applied to the signal lines I/O and I/O common to each data pair line.
It is output as data output. Now, in normal memory, as mentioned above. If you increase the integration while maintaining Vcc at 5V, that is, if you reduce the MC, the withstand voltage will naturally be affected, but as in the present invention, it is directly related to the degree of integration. Memory cell MC, dummy cell DC
and direct peripheral circuits and MOST (for example, SA, P C @
X D g Y D @ Qxs+ Qysy Qo*
Qo* D C *Qct. ) If the operating voltage of these devices is lowered, the problem of withstand voltage will be eliminated, and the layout 1 can be realized in a small area using small-sized elements (MOST, capacitor, resistor). On the other hand, since the area of the indirect peripheral circuit occupies a small proportion of the total chip area, larger sized elements can be used to ensure stable operation even at high operating voltages. In other words, it becomes possible to create a highly integrated memory that operates at a high voltage when viewed from the outside.

Next, specific examples for reducing dimensions are listed below.

(2) Selectively thinning the oxide film; Generally, the smaller the gate oxide film thickness of a MOST, the normal transistor characteristics are exhibited even with a smaller channel length.

Therefore, in order to reduce the channel length and layout in a small area, it is necessary to reduce the size of the gate oxide film. However, as described above, the withstand voltage (drain-source) decreases. Therefore, as in the present invention, it is important to use different operating voltages depending on the respective channel lengths L. Furthermore, in MOSLSI, this thin oxide film is often used as a capacitor (Ca, C in Figure 2).
s etc.). In this case as well, if a thin gate oxide film is used, a capacitor with a large value can be made in a small area, so such a capacitor can be used in a place that operates at a low voltage. Therefore, the use of thin oxide films in memory arrays and direct peripheral circuits is essential for greater integration.

(2) Making the L and Vth of a MOST with a small gate oxide film smaller; By selectively using a thin oxide film, L and Vth can be made smaller, as is clear from the general characteristics of a MOST. Therefore, by actively utilizing this possibility, high integration is possible without reducing speed. This is because the operating voltage is low in the thin oxide film region, and if left as is, the device will only operate at low speed, but fortunately, L and Vvh can be made small in this region. Konoshiya Vt
This is because aggressively reducing h leads to high-speed operation.

■ Element isolation is easier in areas where devices operate at low voltages. Therefore, the element isolation width can be reduced by this amount. In other words, high integration is possible.

Yes. can affect the interlayer film thickness that contributes to device isolation characteristics. Therefore, the surface area is flattened by this amount, and the number of wire breaks (for example, AQ) is reduced, resulting in a high yield.

That is, as shown in FIG.
．． ．． , 0.2, for example, an AQ wiring WA runs, and a high voltage is applied to it. Also, one M
OST Drain D. Assume that a high voltage is applied to the source Sm2 of the other MOST, and a low voltage is applied to the source Sm2 of the other MOST. Q. Element isolation @Lp that can electrically separate D and Q m2 is. W
The voltage VDP applied to A depends on the interlayer thickness top,
In general, the smaller the Vop, the larger the top, the Lp
can be made small.

Therefore, if the present invention is adopted with top constant, vo
Since p is small, Lp can be made small and highly integrated.

Furthermore, since the top can be made small under a constant LP, a cross section with fewer steps can be obtained. Therefore, AQ disconnections can be reduced, resulting in a high yield.

(2) In order to further emphasize the advantages of the above method, the depth X- of the diffusion layer in the main parts of the memory array and the direct peripheral circuit is made smaller than that in the indirect peripheral circuit part. That is, XJ
This is because the smaller the value, the smaller the size of the MOST can be used.

As is obvious, depending on the case, it is possible to selectively increase the dimensions of elements in the direct peripheral circuit by considering the operating state. For example, in a QCL, a high voltage of 1.5V is applied between its drain and source, so it is necessary to take measures such as using a large-sized MOST.

In addition, in the sense amplifier SA, if Q^ and Q^ are made too small, these threshold values may not match due to manufacturing variations, resulting in memory cell continuous noise, so the dimensions of Q^ and Q^ needs to be selectively increased.

Incidentally, a specific example of the dimensions of the memory shown in FIG. 2 is as shown in FIG. 7. Combinations of these various dimensions can be selected depending on the application. For example, XJ and top
Although the advantages of the present invention can be maximized by using two types as shown in this figure, it is also possible to use only one type depending on the manufacturing process. In addition, Figure 3 shows the word voltage generation circuit WG in Figure 2.
and shows the circuit configuration of voltage booster circuit VU. Both WG and VU are depression type N-channel MOST (V
ih=3.5'V) QDN and a conventional pulse generation circuit PG which uses the source voltage of this MOST as a power supply voltage. The vibration of input pulse voltage φ8,φ,′ is Vc
c, but the voltage at point a is maintained at -3.5V by the depletion MOST and QDN. The pulse generating circuit PG in the word voltage generating circuit WG outputs a pulse φ of voltage Vop (=3.5V) in response to the rise of the input pulse φX. Furthermore, after that, the pulse generation circuit PG in the voltage booster circuit VU generates an input pulse φ, (amplitude V
'cc) In response to the rise of voltage Vop, a pulse φ. Outputs . As a result, the line W' has a capacitance C
The voltage is increased by the action of B to ~1.5Vop. (FIG. 4) The output voltage of the circuit PG remains almost constant even if Vcc changes (for example, from 5 to 8 V) because it is uniquely determined by the Vth of the MOST QDN (FIG. 5).

This means that even if Vcc is set too high, the memory array MA
This means protecting microscopic MOSTs, which are often used in the surrounding areas, from being destroyed. In addition, as shown in the circuits WG and VU shown in FIG.
The method of generating an amplitude equal to a smaller voltage vop in response to an input pulse having an amplitude equal to the external voltage Vcc using a MOS and a pulse generation circuit is not limited to these circuits WG and VU, but also includes the indirect peripheral circuit 60. Also used for

Since the transistor QDN shown in FIG. 3 receives the Vcc power supply and outputs the Vop voltage, the internal power supply voltage generation circuit 30 can also be configured using this transistor. In other words, if a Vtb" 3.5V depletion type transistor is used in the part that generates Vop, as shown in Figure 3, and the drain and gate are applied with Vcc and ground potential, respectively, the power supply voltage Vop can be generated from the source. Furthermore, if the drain and gate of an enhanced transistor are connected to the source of a transistor with the same configuration as the part that generates V', and the threshold of this transistor is set to 0.5V, this transistor The power supply voltage V' can be obtained from the source.Next, a specific example of the applied force formula of the power supply voltage converted to a low voltage will be described.

Figure 8 shows all of the indirect peripheral circuits (PGI,
P02, etc.) is supplied with voltage VDP from a common voltage converter 30. The output pulses from these PGs are φ. φ purchase 1 φ ko, ai ~ a scoop a quantity 1,,, a. 1 etc. In this case, as long as 30 has sufficient current supply capacity, there will be no particular problem with Vop power fluctuations even if each pulse generating circuit that makes up the indirect peripheral circuit rotates its respective load capacitance C, , C, , C3. ．． However, if the current supply capacity of 3o is small, Vop will fluctuate each time each pulse generating circuit PG operates, and this fluctuation will last for a long time if the power line capacitance COP is large. In other words, multiple PGs interfere with each other in the form of Vop fluctuations,
An ideal pulse waveform cannot be obtained from each PG. Figure 9 shows a solution to this drawback. Since a voltage converter is attached to each PG, the above disadvantages are eliminated. Actually, the third
The figure is a concrete example of this. Figure 10 shows an application method when PGs that require low-voltage output pulses and PGs that do not are used together. For example, the output pulses of PGI or PG4 can be applied directly to peripheral circuits or memory arrays that require low voltage pulses, as described above. FIG. 11 shows another embodiment that reduces mutual interference via Vop, which is a drawback of FIG. 8. Classifying each PG that makes up the indirect peripheral circuit, we can see that certain PGs operate only during certain time periods, while other PGs operate only during different time periods. Accordingly, it can be classified into multiple PG groups. For example, in address multiplex type dynamic memory, two ? There are two PG groups inside the chip that operate in response to each applied clock (φ1, φ2). In this case, if the voltage converter is used for each φ, , φ2, , φ■ and φ2 are eliminated. a. Or, as shown in FIG. 12, the PGs (PGI, PG2, P
PG (PGI') that operates when G3, -) and OFF
, PG2', PG3', . . . ), that is, two types of PG groups that operate according to the logic state of φ, and a method of connecting the voltage converter 30 to each group is also conceivable. Taking the example of dynamic memory, φ
is ON, during the time when memory operation is to be performed, and
In the case of FF, this corresponds to the time period in which the precharge operation is performed.

Next, we will describe an example of the circuit system of the voltage converter itself other than that shown in Figure 3. To simplify the explanation, we will use a commonly used dynamic pulse generation circuit. The details of the operation of this pulse circuit PG are described in the 1981 IEICE Semiconductor/Materials Division National Conference Nα69. The outline will be explained with reference to FIG. That is, the input φ
When fear is applied, the gate voltage of Qo is discharged from a high potential to a low potential, turning Qo off, and at the same time, the gate voltage of QL is discharged from a low potential to a high potential (higher than Vcc using bootstrap capacitance). The result is that the voltage is charged to a potential.
QL turns ON and output φ. goes from a low potential (Ov) to a high potential (Vcc). In this kind of circuit format,
In order to obtain a low voltage output pulse, an embodiment as shown in FIG. 3 can be used. However, in some cases, as shown in FIG. 14, a pulse φ. is input, the amplitude of the outputs φ0e to φo4 of each PG is also Vcc, but when a certain output (for example φ0
d, φo4') is additionally lower voltage amplitude (Vo
There may also be cases where it is desired to output the pulse p) and directly apply this low voltage pulse to peripheral circuits or memory arrays. An example of the voltage converter in this case is shown in Section 15.16.

FIG. 15 shows φ in the output stage of FIG. This is an example in which inverters QL' and Qo' are added in parallel. QDN
is the same depression MOST as in FIG. Also 1
Figure 6 is. This is an example in which the same depression MOST QDN as in Figure 3 is added in series to Qo and QL, and the output is taken from both ends. Obviously φ. The amplitude is obtained up to Vcc, and it is regulated by the threshold voltage of the depletion MOST and becomes the amplitude of VDP. ′ is φ. obtained at the same time as

Moreover, FIG. 17 shows φ in FIG. 16. ′ is boosted as shown in Figure 3. As described above, a pulse generating circuit that takes a low level has been described, but if this continues, a highly reliable integrated circuit cannot be obtained. In other words, in a typical integrated circuit, after the final manufacturing process,
In an aging test, a voltage that is sufficiently higher than the power supply voltage used in normal operation is intentionally applied to each transistor in the chip to early detect transistors that are likely to fail due to defects in the gate oxide film, etc. This guarantees reliability. However, as described in this example, if the voltage is made constant, even if the external power supply voltage is increased, a sufficiently high voltage will not be applied to each transistor, making it impossible to conduct a sufficient aging test. Therefore, it is conceivable to make the gate voltage of the depletion MOST higher than the ground potential only in the case of an aging test. By doing so, as is clear from the well-known properties of the depletion MOST, the output voltage increases by the amount of the gate voltage increased. As shown in FIG. 18, as a means for applying the voltage during aging, the depression MOST is applied by the switch SW.
The gate voltage of the QDN may be set to ground potential during normal operation and to an appropriate voltage VE during aging. FIG. 19 shows a specific example thereof. That is, the gates of the plurality of QDNs within the chip are connected to ground within the chip by the resistor R within the chip. On the other hand, the gate is connected to the package pin PN via the bonding pad PD.
connected to. During normal operation, if this pin is left open, the gate of each QDN is at ground potential. Also, if a potential is applied to this bin during aging, the QDN
The higher the voltage applied to the source, the higher the voltage obtained.

FIG. 20 shows an embodiment in which the same effect is obtained by adjusting the phase relationship of the external clock applied to the chip only during aging, without bothering to provide an aging pin as described above. For example, in dynamic RAM, as is well known, two types of external clocks RAS (Ro
w Address Strobe) and C A S (
Colua+n Address Strobe). Normally, a combination of "high level RAS and low level CAS" is not used, so this combination may be used instead during aging. That is, by using the logic shown in FIG. 20, the gate of the QDN can take a potential higher than the ground potential only in the above combination. Note that, for convenience of explanation, the above embodiment is an example of a depression MOST, but an enhancement MOST is obviously also possible. However, to achieve the same effect as the Depression MOST example,
It is necessary to apply a constant voltage to the gate. For example, in order to obtain a constant voltage Vop at the source of an enhanced MOST, a constant voltage Vop is applied to the gate of this enhanced MOST.
It is necessary to apply p+ Vih (Vth: threshold voltage of 1-channel XMO ST). Since it is generally possible to keep Vop+Vth constant on a chip regardless of fluctuations in the external power supply voltage, the above enhanced MOST
This means that you can use . From the above, highly integrated and highly reliable memory becomes possible. It is clear that the present method can be applied not only to dynamic MOS memories but also to static MOS memories, piboramome memory and other memories, and integrated logic circuits to which the above concept can be applied.

〔Effect of the invention〕

According to the present invention, a highly integrated semiconductor integrated circuit can be obtained. Further, according to the present invention, it is possible to obtain a semiconductor integrated circuit that can operate at high speed. Furthermore, according to the present invention, it is also possible to solve the problem of aging tests when the external power supply voltage is lowered.

[Brief explanation of drawings]

1 to 20 are diagrams showing embodiments of the present invention. Description of symbols 10...Substrate, 20...Substrate voltage generation circuit, 30...Internal power supply voltage generation circuit, 40...First circuit section, 50...Second circuit section.茅φ Zuji Z Mekiyo ( ノσ fig. 茅 zu 1? 茅竿DE m 13 茅 4 ふ 9 fig. zu zu / l, fig. Yno 7 fig.

Claims (1)

[Claims] 1. A plurality of word lines, a plurality of data lines provided to intersect with the plurality of word lines, and a plurality of memory elements provided at the intersections of the word lines and the data lines. and a peripheral circuit for selecting the memory element, the lower of the voltages applied to the memory element is lower than the voltage applied to the peripheral circuit, The semiconductor integrated circuit is characterized in that the voltage applied to the word line is higher than the lower one of the voltages applied to the memory element. 2. In a semiconductor integrated circuit in which a plurality of semiconductor devices are provided on a single chip, a single power supply voltage is applied to the power supply pins of the package, and a single power supply voltage is applied to the group of semiconductor devices provided on the single chip. A semiconductor integrated circuit comprising voltage supply means for supplying a voltage lower than a power supply voltage supplied from an external source. 3. It has a plurality of word lines, a plurality of data lines provided to intersect with the plurality of word lines, and a plurality of memory elements provided at the intersections of the word lines and the data lines, and In a semiconductor integrated circuit, the memory element is composed of a field effect transistor for reading or writing information and a capacitive element for storing information, and has a peripheral circuit for selecting the memory element. A semiconductor integrated circuit characterized in that a lower voltage among the voltages is lower than a voltage applied to the peripheral circuit.