JPH02228887A - Video signal processing circuit - Google Patents

Abstract

PURPOSE:To execute the insertion of a still picture and the wipe fade processing of the inserted picture by providing a signal generating means, subtracting means, multiplying means, adding means and control means to control a signal generated by the signal generating means and the multiplier of the multiplying means. CONSTITUTION:A video signal processing circuit is equipped with a memory 18 having storage capacity for one field or for one frame, multiplying circuits 22 and 24, subtracting circuits 26 and 28, adder circuits 30 and 32, data generating circuit 36 to generate prescribed luminance data, data generating circuit 38 to generate prescribed color data, comparator circuit 44 and control circuit 46 to control the operation of the respective parts and the timing of the operation. Thus, since the signal generated by the signal generating means can be superimposed or mixed to an input video signal by the subtracting means, multiplying means and adding means and the multiplier to be hourly changed is multiplied in the multiplying means, the intensity of the signal generated by the signal generating means can be changed and the wipe fade processing can be realized.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a video signal processing circuit.

[Prior Art] Conventionally, a video signal processing circuit is known in which a video signal such as a character video or a graphic video is binarized and stored in a memory, and this is taken out as appropriate and superimposed on another video signal. ing.

That is, if a high-contrast video signal, such as a video signal of characters written on paper, is used as a memory storage signal, the memory storage signal will be only characters, which can be used to insert a simple title into the output video.

Video signal processing techniques using memory include special effect processing such as a wipe effect and a fade effect, which combine a video signal stored in a memory and a normal video signal at a predetermined ratio.

[Problem to be Solved by the Invention] Even in the simple title insertion process described above, if the wipe/fade process is utilized, more effective video display becomes possible.

Therefore, an object of the present invention is to provide a video signal processing circuit with a simple structure that realizes such processing.

[Means for Solving the Problems] A video signal processing circuit according to the present invention includes a signal generating means for generating a specified signal, a subtracting means for calculating a difference between an input video signal and the specified signal, and a subtracting means for calculating the difference between an input video signal and the specified signal. a multiplication means for multiplying the output by a controllable multiplier; an addition means for adding the output of the multiplication means to an input video signal; and a control means for controlling the signal generated by the signal generation means and the multiplier of the multiplication means. Consisting of

[Operation] The subtraction means, the multiplication means, and the addition means:
The signal generated by the signal generating means can be superimposed or mixed on the input video signal. Further, by performing multiplication by a multiplier that changes over time in the multiplication means, the strength of the signal generated by the signal generation means can be changed, and wipe/fade processing can be realized.

[Example] Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1 shows a block diagram of an embodiment of the present invention. 1
0 is luminance signal data sampled, quantized, and encoded by an A/D converter (not shown) (hereinafter referred to as luminance data).

), 12 is an input terminal for similarly sampled, quantized, and encoded color difference signals or carrier color signal data (hereinafter referred to as color data), and 14 is an input terminal for luminance data processed by the illustrated circuit. 16 is an output terminal for color data processed by the illustrated circuit; 18 is a memory with a storage capacity for one field or one frame; 22; 24 is a multiplication circuit; 26.
28 is a subtraction circuit, 30.32 is an addition circuit, 36 is a data generation circuit that generates predetermined luminance data, 38 is a data generation circuit that generates predetermined color data, 40.42 is a changeover switch, 44 is a comparison circuit, 46 is a control circuit that controls the operation and timing of each part.

The output 46A of the control circuit 46 is connected to the data generation circuit 36.3.
8, output 46B is an operation control signal for memory 18, output 46C is multiplier circuit 2.
The data is multiplied by 2.24.

Next, the operation of superimposing the title image on the input video signals of the input terminals 1°0 and 12 will be explained. The memory 18 has input terminal 1
Luminance data of 0 is temporarily stored, and this stored data is read out in synchronization with the input video data at the input terminals 10 and 12, and is applied to the comparison circuit 44. In synchronization with the reading of data stored in the memory 18, the data generation circuits 36 and 38 output designated or predetermined luminance one-color data from the control circuit 46.

Subtraction circuits 26 and 28 are title data generation circuits 36 and 38.
The luminance data and color data of input terminals 10 and 12 are subtracted from the output of . A comparison circuit 44 compares the output data of the memory 18 with a predetermined constant value, and switches the switch 4 according to the comparison result.
0.42 is controlled by switching.

That is, switch 40.42 selects either zero data or difference data output from subtraction circuit 26.28. The data selected by switches 40 and 42 is sent to multiplier circuit 2.
2.24 to the adder circuit 30.32.

Multiplier K of multiplier circuit 22.24 (output 46 of control circuit 46
C) is zero, or when switch 40.42 is connected to ground and outputs zero data, the output data at output terminal 14.16 is exactly the input data at input terminal 10.12. On the other hand, when the switch 40.42 selects the output side of the subtraction circuit 26.28 and the multiplier K of the multiplication circuit 2224 is 1, the output terminal 14.1
The output data of No. 6 is the output data itself of the data generation circuits 36 and 38. Furthermore, when 0<K<1, the output data of the output terminal 14.16 is transferred to the input terminal 10.12.
It becomes mixed data of the input data of and the data generated by the data generation circuits 36 and 38.

By gradually monotonically increasing or decreasing the multiplier K, so-called fade processing can be performed on this mixed data. Also,
By switching K between 0 and 1 with a delay time consisting of horizontal and vertical synchronizing signals and increasing or decreasing the delay time, a so-called wipe effect can be provided.

Note that the comparison value in the comparison circuit 44 may be a fixed value or may be changed externally. Furthermore, the simple title insertion process in this embodiment includes not only so-called character display but also insertion of certain still image data.

[Effects of the Invention] As can be easily understood from the above explanation, according to the present invention, a predetermined still image can be inserted, and wipe/fade processing can be selectively performed on the inserted image. .

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention. 10.12: Input terminal 14, 16: Output terminal 18: Memory 22, 24: Multiplication circuit 26.28: Subtraction circuit
30, 32: Adder circuit 36, 38 = Data generator circuit
40, 42: Switch 44: Comparison circuit 46: Control circuit

Claims (1)

[Claims] a signal generating means for generating a designated signal; a subtracting means for calculating a difference between an input video signal and the designated signal; a multiplication means for multiplying the output of the subtracting means by a controllable multiplier; A video signal processing circuit comprising an adding means for adding the outputs of the means, and a control means for controlling the signal generated by the signal generating means and the multiplier of the multiplying means.