JP2506205B2 - Black level correction device - Google Patents

Description

The present invention relates to a black level correction device for improving the image quality of a television receiver.

[Conventional technology]

In recent years, the image quality of television receivers has been improved, and digital television receivers have been put into practical use. Further, various black level correction devices have been proposed as means for improving image quality.

Hereinafter, a proposal example of the above-described black level correction device will be described with reference to the drawings.

FIG. 6 shows a block diagram of a proposed example of the black level correction apparatus. Further, FIG. 7 is a circuit diagram showing a specific configuration of the integrating circuit, and FIG. 8 is a circuit diagram showing a specific configuration of the horizontal addition circuit in FIG.

In FIG. 6, reference numeral 1 is a digital delay circuit for delaying the input digital luminance signal. Reference numeral 2 denotes a digital first comparison circuit, which detects a black level signal corresponding to a black level dot on the screen by comparing the input digital luminance signal with the set value A. Reference numeral 3 denotes an integrator circuit that obtains the ratio of the area of the black level area in the minute area by integrating the black level signal obtained from the first comparison circuit for each minute area composed of a plurality of dots on the screen. is there. A digital second comparison circuit 4 compares the output of the integration circuit 3, that is, the ratio of the area of the black level area in the minute area on the screen with the set value B. Reference numeral 5 is a gain control circuit for controlling the level of the digital luminance signal, and is composed of, for example, a read only memory 5A and a changeover switch 5B.

In addition, in the concrete configuration of the integrating circuit 3 in FIG.
Are line memories, 7, 7, ... Are horizontal addition circuits, and 8 are vertical addition circuits.

Further, in the specific configuration of the horizontal adder circuit 7 in FIG. 8, reference numerals 9, 9, ... Are D-flip-flops, and 10 is an adder circuit.

Regarding the black level correction device configured as described above,
The operation will be described below with reference to FIG. 2, FIG. 6, FIG. 7, FIG. 8 and FIG. 9 to FIG.

First, the input digital luminance signal S shown in FIG.
₁ is compared with the set value A in the first comparison circuit 2 and is output as the black level signal S ₂ shown in FIG. 2 (b).

Next, the integrator circuit 3 is specifically shown in FIGS.
As shown in the figure, 2i line memories 6 are connected in cascade, and each black line signal S ₂ is delayed by one line, and 2i lines in total are delayed. The input / output of each line memory 6 is simultaneously connected to (2i + 1) horizontal adder circuits 7. Therefore, the black level signal S _{2 of} the (2i + 1) line is simultaneously input to the (2i + 1) horizontal adder circuits 7.

Inside the horizontal adder circuit 7, 2j D-flip-flops 9 are cascade-connected, and (2j + 1) inputs and outputs thereof enter the adder circuit 10. That is, in the horizontal addition circuit 7, for example, a black level signal of a total of 7 dots in the horizontal direction (where j = 3) with a certain dot in a certain line, for example, the dot S in FIG. 9 as the center, on the screen. Is being added.

Then, the outputs of the (2i + 1) horizontal adder circuits 7 enter the vertical adder circuits 8 respectively (when i = 2) and the vertical direction 5 is applied.
Line addition is performed. As the output, the number of dots in which a black level signal exists in a small area of (2j + 1) dots × (2i + 1) lines as shown in FIG. 9 is represented with respect to the point S.

The above integration operation is performed in dot units for each line on the screen. That is, every time one dot of the input digital luminance signal is transferred, the number of dots in which a black level signal exists in a minute area of (2j + 1) dots × (2i + 1) lines centered on the dot is detected.

Next, in the second comparison circuit 4, the output signal S ₃ of the integration circuit 3 shown in FIG. 11 (a) and the set value B are compared in dot units, and as shown in FIG. 11 (b). A black level correction on / off signal S ₄ is output. That is, the on / off signal S _{4 for} black level correction is such that the dots having a large black level region ratio, that is, the black level region having a large area as shown by the hatched portion in FIG. A high level signal is output to turn off the signal, and a low level signal is output to the other parts to perform black level correction.

Further, the input digital luminance signal is delayed by the delay circuit 1, and after the signal delay amount up to the second comparison circuit 4 and the delay amount are matched, the gain control circuit 5 corrects the input luminance signal according to the input level. (See FIG. 12, the solid line shows the input / output characteristic of the gain control circuit 5 when the black level correction is off, and the broken line shows the input / output characteristic of the gain control circuit 5 when the black level correction is on) . As a result, the floating of black is suppressed at points P to Q in FIG. 12, and the black level is expanded at points Q to R to improve the gradation. In this case, when the output of the second comparison circuit 4 is at a high level, that is, when correction is not required, the switch 5B is switched to the a side, and the gain control circuit 5 has the input / output characteristic shown by the solid line. On the other hand, when the output of the second comparison circuit 4 is at a low level, that is, when correction is required, the switch 5B is switched to the b side, and the gain control circuit 5 has the input / output characteristic shown by the broken line. The input / output characteristics indicated by the broken line are stored in the read-only memory 5A in the relationship between address input and data output.

As described above, according to this proposal example, the integration circuit 3 includes 2i horizontal adder circuits 7 each including 2j D-flip-flops 9 and adder circuits 10 and 2i line memories 6.
And the vertical addition circuit 8 are provided, the ratio of the area of the black level region in the small area of (2j + 1) dots × (2i + 1) lines centered on each dot of each line is detected for each dot of each line. can do.

Then, the ratio of the area of the black level region obtained for each dot of each line is compared with the set value B, and the black level correction is turned on / off for each dot of each line based on the comparison result. Therefore, as shown in FIG. 10, even when both the large area black level area K and the small area black level area L exist on one screen 11, the large area black level area K Does not perform the black level correction, but the black level is corrected in the small area black level region L.

[Problems to be Solved by the Invention]

In the configuration of the black level correction device as described above, the setting value B for comparing the ratio of the black level signal to the area is one, and in the scene near the setting value B, the black level correction is turned on and off. However, this may occur for each field, and the image looks like flicker, so the image quality is degraded.

An object of the present invention is to provide a black level correction device that can prevent deterioration of image quality.

[Means for solving the problem]

A black level correction device of the present invention outputs a black level signal corresponding to a black level dot on a screen by comparing an input digital luminance signal with a first set value.
And the black level signal output from the first comparison circuit are integrated, and for each dot of each line on the screen, the black in a minute area consisting of a plurality of dots centered on that dot An integrator circuit for detecting the ratio of the area of the level region, and n (n
Is an integer greater than or equal to 2) and decodes the output of the n second comparison circuits for performing the comparison with the second set value of each of the lines on the screen and the output of the n second comparison circuits. And a decoder for converting it into 1-bit binary data, and a delay circuit for delaying the input digital luminance signal by the same delay time as the delay time by the first comparison circuit, the integration circuit, the n second comparison circuits and the decoder. And a basic black level correction amount pattern indicating the relationship between the level of the input digital luminance signal and the basic black level correction amount corresponding to the level of the input digital luminance signal, and stores a basic black level correction amount pattern corresponding to the output level of the delay circuit. The basic black level correction amount pattern storage unit that outputs the black level correction amount for each dot of each line on the screen, the basic black level correction amount output from the basic black level correction amount pattern storage unit, and the data A multiplication circuit for multiplying 1-bit binary data output from the reader and an output digital luminance signal by subtracting the output of the multiplication circuit from the output of the delay circuit for each dot of each line on the screen. And a subtraction circuit.

[Action]

According to the configuration of the present invention, in the first comparison circuit,
The input digital luminance signal is compared with the first set value, and the black level signal is output from the first comparison circuit corresponding to the black level dot on the screen. In the integrating circuit,
The black level signal output from the comparator circuit is integrated, and for each dot on each line on the screen, the ratio of the area of the black level region in the minute area centered on the dot is output.

The second comparison circuit compares the output of the integration circuit with the n number of set values whose levels are sequentially different. This comparison is performed for each dot on each line on the screen.
Then, the decoder converts the outputs of the n second comparison circuits into l-bit binary data. Then, the basic black level correction amount output from the basic black level correction amount pattern storage unit and the 1-bit binary data output from the decoder are multiplied by the multiplication circuit. Further, in the subtraction circuit, the output of the multiplication circuit is reduced and output as an output digital luminance signal. As a result, for each dot on the screen, the black level is not corrected when the area ratio of the black level region is extremely large, and the black level correction amount is increased stepwise as the area ratio of the black level region decreases. Will be done. Therefore, when there are black level regions having different areas on one screen, the black level is corrected according to the area.

In addition, since the black level correction amount changes stepwise according to the size of the area ratio of the black level area, the black level correction is switched on / off for each frame. A change in black level can be eliminated, a phenomenon that an image looks like a flicker can be suppressed, and the image quality can be improved.

At this time, the digital luminance signal is delayed by the same amount as the delay time in the first comparison circuit, the integration circuit and the second comparison circuit and is supplied to the basic black level correction amount pattern storage unit and the subtraction circuit.

〔Example〕

A black level correction apparatus according to an embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a black level correction device according to an embodiment of the present invention. 2 and 3 are waveform diagrams of the respective parts of FIG. 1, and FIG. 4 is a basic black level correction amount pattern stored in the basic black level correction amount pattern storage unit, that is, a basic black level correction amount. The relationship between the address input and the data output of the pattern storage section is shown, and FIG. 5 shows the input / output characteristics of the gain control circuit.

In FIG. 1, reference numeral 26 is a comparison section, which is composed of n second comparison circuits 24, ... And a decoder 25. 20 is a gain control circuit, which includes a basic black level correction amount pattern storage unit 21 including a read-only memory, a multiplier 22, and
It is composed of a subtractor 23.

The n second comparison circuits 24 compare the output of the integration circuit 3 with the sequentially increased n set values B _{1 to} B _n . decoder
Reference numeral 25 converts the n comparison circuits 24 into 1-bit binary data. For example, when n = 3 and l = 2 and B ₁ <B ₂ <B ₃ , when the output S ₃ of the integrating circuit ₃ is S ₃ ≦ B ₁ , l becomes “11” and B ₁ <S ₃ When ≦ B ₂ , 1 becomes “10”, when B ₂ <S ₃ ≦ B ₃ , 1 becomes “01”, and when S ₃ ≧ B ₃ , 1 becomes “00”.

The basic black level correction amount pattern storage unit 21 stores data at each address so that the address input and the data output have the input / output characteristics shown in FIG. The multiplier 22 multiplies the output of the basic black level correction amount pattern storage unit 21 and the output of the decoder 25. The subtractor 23 is a delay circuit 1
The output of the multiplier 22 is subtracted from the output of. Therefore, the output digital luminance signal output from the gain control circuit 20 is integrated with respect to the input to the gain control circuit 20 when, for example, n = 3 and l = 2 and B ₁ <B ₂ <B _3. When the output S _{3 of the} circuit 3 is S ₃ ≦ B ₁ , the input / output characteristics are as shown by the broken line in FIG. 5, and when B ₁ <S ₃ ≦ B ₂ are the input / output characteristics as by the one-dot chain line in FIG. , B ₂ <S ₃ ≦ B ₃ , the input / output characteristics are as shown by the chain double-dashed line in FIG. 5, and the black level is corrected according to the magnitude of the output of the integrating circuit 3.

When S ₃ ≧ B ₃ , the input / output characteristic is as shown by the chain double-dashed line in FIG. 5, and in this case, the black level is not corrected.

The configuration other than the above is the same as the proposed example shown in FIG.

Regarding the black level correction device configured as described above,
The operation will be described below with reference to FIGS. 1 to 5.

First, the input digital luminance signal S ₁ of FIG.
Is compared with the set value A and output as the black level signal S ₂ shown in FIG. 2B.

Next, in the integrating circuit 3, the black level signal S ₂ is the area of the black level area in a minute area consisting of a plurality of dots centered on each dot of each line on the screen as described above. Is output as a signal S ₃ (see FIG. 3 (a)) indicating the ratio.

Next, in the n second comparison circuits 24, the n set values B _{1 to} B _n (see FIG. 3, where n = 3) are set.
The ratio of the black level region area is divided into four levels by comparing with.

Next, the output of the n second comparing circuits 24 is the 1-bit binary data S _X by the decoder 25 (see FIG. 3 (b), but in the same figure, it is D / A converted for convenience. It is converted to and output.

On the other hand, the input digital luminance signal is delayed by the delay circuit 1 for a predetermined time as described above, and then, as an address in the basic black level correction amount pattern storage unit 21 containing the basic black level correction amount pattern (see FIG. 4). Is entered. Since the basic black level correction amount pattern storage unit 21 contains the basic black level correction amount pattern shown in FIG. 4, the basic black level correction amount pattern storage unit 21 corresponds to the input signal to the basic black level correction amount pattern storage unit 21. The correction amount is output.

Then, the basic black level correction amount is multiplied by the output of the decoder 25 in the multiplication circuit 22. And
In the subtraction circuit 23, the black level correction is performed by subtracting the output of the multiplication circuit 22 from the output of the delay circuit 1 (see FIG. 5). That is, the black level signal S ₂ whose digital brightness signal S ₁ is less than or equal to the set value A is detected, and from this black level signal S ₂ , for each dot of each line on the screen The signal S ₃ indicating the ratio of the area of the black level region in the minute area made up of dots is obtained,
The magnitude of this signal S ₃ is determined in a plurality of steps, and the black level correction amount is changed according to the determination result.

As described above, according to this embodiment, the n second comparison circuits 24 for comparing the output S ₃ of the integrating circuit 3 with the n set values B _{1 to} B _n and the output thereof are 1-bit 2 bits. A basic black level correction amount pattern storage unit 21 that stores a basic black level correction amount pattern while providing a decoder 25 for converting into value data
And the multiplication circuit 22 that multiplies the output of the basic black level correction amount pattern storage unit 21 and the output of the decoder 25, and the subtraction circuit 23 that subtracts the output of the multiplication circuit 22 from the output of the delay circuit 1. The black level correction amount can be changed stepwise. As a result, it is possible to eliminate extreme changes in the black level of the screen, such as switching the black level correction on / off for each frame, and suppress the phenomenon that the image looks like flicker. It is possible to prevent deterioration of image quality.

In addition, the integration circuit 3 integrates the black level signal S ₂ output from the first comparison circuit 2 and, for each dot of each line on the screen, a black level region S The area ratio is calculated, and the n second comparison circuits 24
The output of the integrator circuit 3 is compared with the _n second set values B _{1 to} B _n for each dot on each line on the screen according to The gain control circuit 20 controls the gain of the digital luminance signal for each dot of each line on the screen, and black level correction is performed for dots with a small area ratio of the black level area in the minute area to obtain the black level. Since black level correction is not performed for dots with a large area ratio,
Even when both a large area black level area and a small area black level area exist on one screen, black level correction is not performed in the large area black level area, and in the small area black level area. The black level can be corrected. Therefore, it is possible to suppress black sinking in a black level area that occupies a large area on one screen, and suppress black floating in a black level area that occupies only a small area on the same screen. It is possible to improve gradation.

〔The invention's effect〕

According to the black level correction apparatus of the present invention, n second comparison circuits for comparing the output of the integrator circuit with n set values and a decoder for converting the output into 1-bit binary data are provided, and A basic black level correction amount pattern storage unit that stores a basic black level correction amount pattern, a multiplication circuit that multiplies the output of the basic black level correction amount pattern storage unit and the output of the decoder, and the output circuit of the delay circuit Since the subtraction circuit for subtracting the output of is provided, the black level correction amount can be changed stepwise. As a result, it is possible to eliminate extreme changes in the black level of the screen, such as switching the black level correction on / off for each frame, and suppress the phenomenon that the image looks like flicker. It is possible to prevent deterioration of image quality.

[Brief description of drawings]

FIG. 1 is a block diagram of a black level correction apparatus according to an embodiment of the present invention, FIGS. 2 and 3 are time charts of respective parts of FIG. 1, and FIG. 4 is a diagram showing a basic black level correction amount pattern. Output characteristic diagram, FIG. 5 is an input / output characteristic diagram of the gain control circuit, FIG. 6 is a block diagram of a proposed example of the black level correction device, and FIG. 7 is a circuit diagram showing a concrete configuration of the integrating circuit in FIG. FIG. 8 is a circuit diagram showing a concrete configuration of the horizontal addition circuit in FIG. 7, FIG. 9 is a black level signal integration area diagram, FIG. 10 is a diagram showing an example of an image, and FIG. 11 is each part of FIG. FIG. 12 is an input / output characteristic diagram of the gain control circuit. DESCRIPTION OF SYMBOLS 1 ... Delay circuit, 2 ... 1st comparison circuit, 3 ... Integration circuit, 21
... Basic black level correction amount pattern storage unit, 22 ... Multiplier, 23
… Subtractor, 24… Second comparator, 25… Decoder

Claims (1)

(57) [Claims] 1. A first comparison circuit for outputting a black level signal corresponding to a black level dot on a screen by comparing an input digital luminance signal with a first set value, and the first comparison circuit. The black level signal output from the comparison circuit is integrated to detect, for each dot on each line on the screen, the ratio of the area of the black level area in the minute area composed of a plurality of dots centered on that dot. The integrator circuit compares the output of the integrator circuit with the n second set values (n is an integer of 2 or more) whose values are sequentially increased for each dot on each line on the screen. A second comparison circuit, a decoder for decoding the outputs of the n second comparison circuits and converting it into 1-bit binary data, the input digital luminance signal, the first comparison circuit, the integration circuit, Delay time by n second comparison circuits and decoder The delay circuit for delaying the same amount, the basic black level correction amount pattern indicating the relationship between the level of the input digital luminance signal and the basic black level correction amount corresponding to the level of the input digital luminance signal are stored, and the output of the delay circuit The basic black level correction amount pattern storage unit that outputs the basic black level correction amount corresponding to each level of each line on the screen, and the basic black level correction amount output from the basic black level correction amount pattern storage unit A multiplication circuit that multiplies the amount and 1-bit binary data output from the decoder, and an output digital luminance signal by subtracting the output of the multiplication circuit from the output of the delay circuit for each dot of each line on the screen And a black level correction device having a subtraction circuit.