JPH02224418A - Synchronizing pulse generating device - Google Patents

Abstract

PURPOSE:To speed up pull in and to reduce a noise pulse, and to prevent the deterioration of performance by cutting out the phase difference voltage of a frequency dividing pulse and an input pulse, and oscillating a voltage controlled oscillator by frequency control voltage, and after that, resetting a frequency divider. CONSTITUTION:The input pulse IN whose means frequency is f0 is inputted from an input terminal 1, and supplied to a phase comparator 3 and a noise gate 7. The pulse NO which is the input pulse IN from which the noise pulse is removed is outputted from the noise gate 7. A switching pulse generation circuit 6 supervises phase relation between the input pulse IN and the frequency dividing pulse CO from the input pulse IN and the output pulse 24E of the frequency divider 2, and if phase jump appears in IN, it turns off a switch 4 and turns on the switch 8. Thus, the output pulse NO of the noise gate 7 is supplied as a reset pulse to the frequency divider 2. Consequently, the frequency divider 2 is reset by IN, and CO is forcedly pulled in the prescribed phase relation to IN.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a synchronous pulse generator that generates an output pulse that is synchronized with an input pulse, and particularly relates to a synchronous pulse generator that generates an output pulse that is synchronized with an input pulse. The present invention relates to a synchronization pulse generator capable of preventing deterioration of synchronization performance due to noise pulses and the like.

[Prior Art] Digital processing has come to be widely used for processing information signals. In this digital processing, information signals are written to and read from the memory, but a device for performing such writing and reading is capable of writing and reading data in the memory. A synchronization pulse generator is provided that generates memory drive pulses such as address pulses for selecting memory cells at predetermined locations and address transfer pulses for sequentially selecting memory cells.

Various types of such synchronization pulse generators have been proposed in the past, and one example is a synchronization/sensor drive circuit for a solid-state color camera described in the Proceedings of the 1982 Annual Conference of the Television Society of Japan, p. 9.89-90. .

This is because the sensor (solid-state image sensor) corresponds to a memory, and image signals are read from this sensor, and the memory drive pulse that drives this sensor is a 7.2 MHz pulse that corresponds to an address transfer pulse. A 15.7 kHz pulse corresponding to the address pulse is used. These memory drive pulses are generated from the crystal oscillator.
It is generated by frequency dividing a 3 MHz pulse.

As described above, this conventional example incorporates a reference oscillator and generates memory drive pulses from its output pulses, and is used to read out image signals from a sensor as a memory. When writing and reading an external information signal to a memory, a synchronous pulse generator is required to generate a memory drive pulse synchronized with the external information signal for writing.
Furthermore, when reading the memory in synchronization with other information signals, a synchronization pulse generator is required to generate memory drive pulses in synchronization with the other information signals.

An example of such a synchronous pulse generator is published by Shashin Kogyo Publishing Co., Ltd.
"Video α" Volume 2 No. 3 (Fittest Person No. 5) Summer
1986 pp. 155-160.

This is TBC (time base collector) by memory
It compares the phase of the horizontal synchronizing signal of the input video signal to be written to and read from this memory and the pulse whose frequency is approximately equal to this horizontal synchronizing signal output from the frequency divider. It has a PLL (phase locked loop) configuration in which a VCO (voltage controlled oscillator) is controlled based on the comparison result, and the output signal of this vCO is supplied to the frequency divider. By frequency-dividing the output signal of this vCO at a predetermined frequency division ratio, a memory drive pulse whose phase is synchronized with the horizontal synchronization signal of the input video signal can be obtained.

However, according to this prior art, if the synchronization of the input horizontal synchronization signal changes sharply and significantly.

The phase synchronization state between the instantaneous input horizontal synchronization signal and the memory drive pulse collapses, and furthermore, it takes a long time to restore the phase synchronization state again. For this reason, in the memory, the address at which each sample data of the input video signal is written is shifted, and since there is a shift in this address for a considerable amount of sample data, the video signal output from the TBC is In the reproduced image, a bending phenomenon called skew occurs in this portion.

Here, the operation when the period of the input synchronizing signal in this prior art changes greatly and suddenly will be explained with reference to FIG. 22.

In the figure, it is assumed that the horizontal synchronizing signal IN is input with an average period of TH, and that the period changes greatly from T)I at time t0. Here, the period T1°T3. T4.・
...eTm is approximately equal to the average period TII.

The period T8 is sufficiently smaller than the average period, and near time t0, the following equation is obtained.

T 1- T g I (I T l-T H (however, i
=1,3. 'L ......) Now, assuming that the period of the input horizontal synchronizing signal IN is approximately equal to the average period TI (up to the period T), the input horizontal synchronizing signal IN is obtained by dividing the output signal of vCO. The frequency-divided pulse CO to be compared in phase with
is phase-synchronized with this input horizontal synchronization signal IN.

When the period T2 becomes sufficiently shorter than the average period T8 at time t0, at this time also, vCO is controlled by the frequency control voltage V, which is the level V when the input synchronization signal IN and the divided pulse CO are phase-synchronized. Therefore, the divided pulse C○
The period is approximately equal to the average period T)I. Therefore, the phase of the input horizontal synchronizing signal IN and the frequency-divided pulse CO is largely shifted, and the level of the frequency control voltage (2) output from the phase comparator is V.

rises more than vco is this frequency control voltage V.

The oscillation frequency is controlled by, and as a result, the period of the divided pulse co becomes shorter than the average period TH, but the input horizontal synchronizing signal IN whose period T is approximately equal to the average period T□ is (TeeT2) Since the phase is advanced by some degree, the 1-frequency divided pulse CO cannot catch up with this input horizontal synchronizing signal IN. For this reason, the frequency control voltage V increases.

In this way, the level of the frequency control voltage V gradually increases, the period of the frequency-divided pulse co becomes shorter, and approaches the input horizontal synchronization signal IN. Then, at time t1, the input horizontal synchronization signal When the phase difference between the signal IN and the frequency-divided pulse CO reaches a certain level, the level of the frequency control voltage V becomes too high, and from this point on, the level of the frequency control voltage 2 decreases. However, since the frequency control voltage V, is higher than V, the period of the frequency-divided pulse Co is shorter than the average period T, and even after that, the phase difference between the input horizontal synchronizing signal IN and the frequency-divided pulse C ○ is gradually smaller. It's becoming. Then, at time t2, the frequency control voltage V becomes V.

When the input horizontal synchronizing signal IN and the divided pulse CO match in phase, normal operation is performed from then on.
The human horizontal opening signal IN and the frequency-divided pulse CO are kept in phase synchronization.

As described above, when the phase of the input horizontal synchronization signal changes significantly and suddenly, the phase synchronization between it and the frequency-divided pulse is lost, and it takes time t, This will require a long time of ~t2.

In a VTR, a magnetic tape is alternately scanned for reproduction using a plurality of heads, and by switching these heads in order, the video signals reproduced from these heads are spliced into a continuous video signal. In this case, since the phase of the horizontal synchronization signal changes drastically at the time of head switching, in order to prevent this effect from appearing on the playback screen, the head switching is performed at the leading edge of the vertical blanking period of the video signal. I try to do it in my neighborhood.

However, when such a video signal is supplied to the above TBC to correct the time axis error °-'tt, the horizontal synchronization signal and the frequency-divided pulse become phase synchronized due to a sudden change in phase due to head switching of the horizontal synchronization signal. Period t until return,
When ~t2 is sufficiently longer than the vertical blanking period,
A skew phenomenon appears at the top of the playback screen.

In order to prevent this, the amount of change in the oscillation frequency of vCO relative to the amount of change in the level of frequency control voltage VF is increased. -t2. That is, although it is possible to shorten the phase pull-in time, there is a problem in that the stability against noise and the like drops. For example, phase comparator or vC
When noise is superimposed on the operating power supply voltage of O and a so-called power supply ripple occurs, the level of the frequency control voltage v2 fluctuates, but since the amount of fluctuation in the oscillation frequency of vCO is large relative to the amount of fluctuation in the frequency control voltage v2, the level of the frequency control voltage v2 fluctuates. The phase of the frequency-divided pulse CO fluctuates greatly with respect to the power supply ripple, and the phase synchronization between this pulse and the input horizontal synchronizing signal IN is lost. This causes jitter development in which the reproduced image vibrates in the horizontal direction.

In addition, if a power supply ripple with a repetition frequency higher than the divided pulse CO occurs, the oscillation frequency of c0 changes instantaneously, and the repetition period of the memory drive pulse generated from the output signal of the VCO changes. Disturbed. In this case, a disturbance in the instantaneous period of the address transfer pulse appears in the reproduced image as image distortion such as vertical lines appearing to be twisted or a portion of one image being expanded or contracted. In particular, T.B.C.
In today's world, digital circuits that generate large-amplitude pulse signals are often used, but these digital circuits often become a source of high-frequency noise.

Therefore, in conventional TBCs, sufficient noise countermeasures are taken by devising the layout of the circuit board and board pattern, and inserting a high-capacity ripple filter circuit into the power supply line.
On top of that, as a VCO.

By using an LC oscillator using a coil and a capacitor, it is possible to prevent the occurrence of skew during phase jumps.

However, the above-mentioned noise countermeasures become an impediment to miniaturization of the device. Furthermore, although the LC oscillator has the advantage of shortening the one-phase pull-in time, on the other hand, it has the characteristic that the generated frequency changes sensitively to changes in one circuit constant, and for this reason, one assembly adjustment is required. This is difficult and requires work such as fixing the adjustment part with adhesive to prevent setting deviations after adjustment, and manufacturing costs increase as circuit elements whose circuit constants change little over time are required. There is a problem with doing so.

In the PLL-configured synchronous pulse generator used in conventional TBCs, an oscillator with low frequency stability is used as the vCO in order to prevent the occurrence of skew during phase jumps. , the above-mentioned problems arise.

On the other hand, a synchronous pulse generator was developed in Japanese Patent Application Laid-Open No. 1983-111 that was able to quickly eliminate a large phase shift between input and output pulses.
It is disclosed in Japanese Patent No. 130629.

Although this also has a PLL configuration, the frequency division pulse is forcibly synchronized with the input pulse at startup (PLL operation stop mode), and after that, the mode is shifted to the PLL operation mode. That is, at startup, vC
O operates and its output pulse is divided by a frequency divider to generate a divided pulse CO, but the input pulse IN is not supplied and the pump installed between the phase comparator circuit and vCo The circuit is placed in a deactivated state, the output signal of the phase comparator circuit is blocked, and vCO is supplied with a partial level control voltage. This state is the PLL operation stop mode.

After that, when the input pulse IN is supplied, the frequency divider is reset for each input pulse IN, and the 1-frequency divided pulse CO is forced to be phase-synchronized with the input pulse IN, but when the control signal CNT is input, the frequency divider is reset. Then, the first input pulse IN after inputting the control signal CNT becomes the last reset pulse of the frequency divider, and at the trailing edge of this input pulse IN, the pump circuit is activated and enters the PLL operation mode.

Therefore, in this prior art, when the input pulse IN and the frequency-divided pulse CO are out of phase synchronization, the control signal CNT is input.

The frequency divider is reset by the input pulse IN, and the input pulse IN and the frequency-divided pulse co become rapidly phase-locked.

[Problems to be Solved by the Invention] However, the prior art described in Japanese Unexamined Patent Publication No. 58-130629 has the following problem.

First, there is a problem when a noise pulse is superimposed on the input pulse IN.

As explained earlier, in the PLL operation stop mode, the frequency divider is constantly reset by the input pulse I'N, and the control signal C
When NT is input, the final reset of the frequency divider is performed by the first input pulse IN immediately after the input, and the PLL operation mode is entered. If there is a noise pulse between
This noise pulse performs a final reset of the frequency divider to enter the PLL operating mode. For this reason, in the PLL operation mode, the frequency-divided pulse co is initially phase-locked to this noise pulse, and is largely out of phase with the input pulse IN. The VCO uses these divided pulses CO and input pulses I
The oscillation frequency is controlled according to the phase difference with N, and the frequency-divided pulse CO and the input pulse IN are finally phase-synchronized, but the operation during this time is similar to the operation shown in FIG. Therefore, the high-speed retraction function will be impaired.

Second, there is a problem caused by a level difference in the frequency control voltage of vCO between the PLL operation stop mode and the PLL operation mode.

As explained earlier, vC in PLL operation stop mode
The frequency control voltage of O is constant, and in the PLL operation mode it depends on the phase difference between the input pulse IN and the frequency-divided pulse CO. Therefore, PLL operation mode and PLL
When switching between operation stop mode and operation stop mode, PL
When switching from L operation mode to PLL operation stop mode,
The frequency control voltage of vCO, which had been set according to the phase difference between the input pulse IN and the frequency-divided pulse CO, is released and becomes a constant level.When the PLL operation mode is entered again, the frequency control voltage of vCO is set again according to the phase difference between the input pulse IN and the divided pulse CO. Divided pulse C○
The level is reset according to which phase difference. For this purpose, vC in PLL operation mode and PLL operation stop mode is
If there is a large level difference in the frequency control voltage of O, the time required to pull the frequency-divided pulse C into the input pulse IN becomes long.

This conventional technology is used in a clock generator for a floppy disk drive, but it poses a particular problem when used in a synchronization pulse generator such as a TBC for correcting a time axis error in a reproduced signal of a VTR. . That is, when this prior art is applied to generate a memory drive pulse synchronized with a horizontal synchronizing signal reproduced from a VTR as an input pulse IN, for example, noise pulses are added to the reproduced horizontal synchronizing signal due to dropout, etc. Also, since the period of the reproduced horizontal synchronizing signal changes greatly and suddenly at the time of head switching, it is conceivable to set the PLL operation stop mode for a predetermined period including this head switching time. The period of the reproduced horizontal synchronization signal is random, and therefore, the level difference between the frequency control voltage of vCO between the PLL operation stop mode and the PLL operation mode start time may become large.

For this reason, the above-mentioned problem occurs and the high-speed retracting function is impaired.

An object of the present invention is to solve such problems, and even if an oscillator with high frequency stability is used for the vCO, it is possible to prevent the influence of noise pulses mixed into the input pulse, and to prevent large sudden changes in the phase of the input pulse. It is an object of the present invention to provide a synchronization pulse generator which is capable of high-speed phase pull-in even during phase jumps and can significantly shorten the time required for phase pull-in during normal operation.

[Means for Solving the Problem] In order to achieve the above object, (1) the present invention provides a voltage controlled oscillator, a frequency divider that divides the output pulse of the voltage controlled oscillator, and a frequency divider that divides the output pulse of the voltage controlled oscillator. In a PLL configuration consisting of a phase comparator that compares the phase of a frequency-divided pulse output by a frequency-divided pulse and an input pulse, and a low-pass filter to which a phase difference voltage detected by the phase comparator is supplied, a first means for performing an operation of resetting the frequency generator; a second means for performing an operation of cutting off the supply of the phase difference voltage to the low-pass filter prior to the operation of the first means; 1. A third means for switching between an operating state and a non-operating state of the second means is provided.

The third means includes means for determining whether or not there is an input pulse within a first period having a predetermined time relationship with the frequency-divided pulse; 1. Second
and means for setting the means to an operating state.

(2) Further, in the above PLL configuration, the present invention is such that the input pulse has a phase jump at a predetermined period, and the period of the phase jump is used as a unit to separate the first period including the phase jump of the input pulse. a first means for setting a second period following the first period and a remaining third period; and the low pass of the phase difference voltage during the first and second periods controlled by the first means. There are second means for cutting off the supply to the filter, and third means controlled by the first means for extracting the input pulse during the second period and providing a reset pulse for the frequency divider.

When the input pulse is a reproduction horizontal synchronization signal of the magnetic recording and reproducing device, the first means is set to a period of time equal to the first period during which the trailing edge coincides with the trailing edge of the reproduction vertical synchronization signal of the magnetic recording and reproducing device. means for generating a second signal having a leading edge coincident with a trailing edge of the reproduced vertical synchronization signal and equal to a second period; and means for generating a second signal having a width equal to a second period; and means for generating a third signal for a period equal to the sum of the periods.

(3) Furthermore, in the above PLL configuration, the present invention provides that the input pulse is a horizontal synchronization signal that is reproduced from a magnetic recording and reproducing device and jumps in phase every time the head is switched, and that the input pulse is set in a predetermined time relationship with the frequency-divided pulse. a first means for extracting and outputting an input pulse when it is outside the period; and generating a first signal including at least a time point at which a phase jump occurs and an equalization pulse period of a reproduction synchronization signal of the magnetic recording and reproduction apparatus. a second means; a third means for extracting an output pulse of the first means after a signal period of the first signal and using it as a reset pulse of a frequency divider having a PLL configuration; and a first output pulse of the first means; fourth means for generating a second signal having a time width from to the trailing edge of the first signal, and a phase difference voltage of a phase comparator having a PLL configuration for the signal period of the second signal to a low pass filter having a PLL configuration. and fifth means for cutting off the supply of.

[Operation] (1) According to the present invention, when the first and second means are set to a non-operating state by the third means, the voltage is PLL that controls the oscillation frequency of the controlled oscillator
A configuration feedback loop is formed. 1st, 2nd
When the means is set to the operating state, the second means cuts off the phase difference voltage output from the phase comparator and causes the voltage controlled oscillator to oscillate with the frequency control voltage held in the low-pass filter. , the first means causes the frequency divider to be reset by an input pulse.

This reset forces the frequency-divided pulse to be phase-locked to the input pulse.

When the input pulse is within the first period, the input pulse and the frequency-divided pulse are placed in a phase relationship such that the phase 1 phase comparator generates a phase difference voltage according to the phase difference between the input pulse and the frequency-divided pulse. The third means determines this phase relationship and switches the states of the first and second means.

(2) Also, according to the present invention, when the first means estimates a phase jump point and there is a phase jump in the input pulse, the second means estimates the first period including the phase jump point and the first period including the phase jump point. During the second period, the phase difference voltage output from the phase comparator is cut off, and the voltage controlled oscillator oscillates with the frequency control voltage held in the low-pass filter. Reset by input pulse. Due to this reset, the frequency-divided pulse is phase-locked to the input pulse in the third period.

When the input pulse is a reproduction horizontal synchronization signal of a magnetic recording/reproduction device, a phase jump due to head switching occurs a certain time before the vertical synchronization signal.

For this purpose, the timing of the phase jump can be estimated from the timing of the vertical synchronization signal. Therefore, the period for resetting the frequency divider is determined from the vertical synchronization signal. As a result, in the portion that appears on the screen, the frequency-divided pulse and the input pulse can be synchronized in phase.

(3) Furthermore, according to the present invention, since the phase jump point of the reproduced horizontal synchronization signal due to head switching can be estimated by the vertical synchronization signal as described above, the vertical synchronization signal can be used to estimate the period after the phase jump until the equalization pulse period elapses. is set, and the frequency divider is reset with the first horizontal synchronization signal after this equalization pulse period has elapsed, so that the frequency division pulse is phase-locked with the horizontal synchronization signal. In this case, the first signal and the first
The supply of the phase difference voltage to the low-pass filter of the PLL configuration is cut off by the second signal formed with the phase-jumped horizontal synchronization signal extracted by If the synchronization signal is before the head switching point at which the phase jump starts, the cutoff of the phase difference voltage supply to the low-pass filter always starts from this head switching point, regardless of when the first signal starts. However, the frequency-divided pulse is phase-locked to the horizontal synchronizing signal over the entire portion appearing on the screen.6 [Embodiment] An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a synchronous pulse generator according to the present invention, and 1 is a VCO.

2 is a frequency divider, 3 is a phase comparator, 4 is a switch, 5 is an LP
F (low-pass filter), 6 is a switching pulse generation circuit,
7 is a noise gate, 8 is a switch, 9 is an input terminal, 10
is the output terminal.

In the figure, the average frequency f is input from the input terminal 1.

The input pulse IN is inputted and supplied to the phase comparator 3 and the noise gate 7. The noise gate 7 outputs a pulse NO obtained by removing the noise pulse from the input pulse IN.

VCOl is an oscillator with high frequency stability, and
It oscillates at the oscillation frequency of fo, and its output pulse OU
T is output from the output terminal 10.

This output pulse OtJ T is also frequency-divided by n by a frequency divider 2, and its phase is compared with the input pulse IN by a phase comparator 3 as a frequency-divided pulse CO. The phase detection voltage V from the phase comparator 3 corresponding to these phase differences passes through the switch 4 which is normally on, and is converted into a DC frequency control voltage Vp by the LPF 5.
becomes. The oscillation frequency of VCOl is controlled by this frequency control voltage V.

As described above, a PLL is formed, and the input pulse IN and the frequency-divided pulse CO are phase-synchronized so that they have a predetermined phase relationship. VCOL has high frequency stability, so
It does not respond to sudden changes in the frequency control voltage (2), so the oscillation frequency is not affected by noise pulses mixed into the input pulse IN supplied to the phase comparator 3, and power supply ripples are not affected. The oscillation frequency is also stable.

For this reason, even if there is a phase jump in the input pulse IN, the frequency control voltage (2) changes suddenly.

VCO1 does not respond to this.

Therefore, in this embodiment, the switching pulse generation circuit 6 monitors the phase relationship between the input pulse IN and the divided pulse C○ from the input pulse IN and the output pulse 24E of the frequency divider 2, and detects a phase jump in the input pulse IN. If so, switch 4 is turned off and switch 8 is turned on. When this switch 8 is turned on, the output pulse No. of the noise gate 7 is supplied to the frequency divider 2 as a reset pulse. As a result, the frequency divider 2 is reset by the manual pulse IN, and the 1-frequency division pulse CO is forcibly drawn into a predetermined phase relationship with the input pulse IN.

This operating mode is hereinafter referred to as the frequency divider reset mode. In this frequency divider reset mode, the switch 4 is turned off, and the frequency control voltage V in this mode is held by the LPF 5 at the level immediately before this mode. When the input signal IN and the output pulse 24E of the frequency divider 2 have a predetermined phase relationship by resetting the frequency divider 2, the switching pulse generation circuit 6 turns on the switch 4 and turns off the switch 8 to perform PLL operation. reset to mode.

In this case, the level of the frequency control voltage V held by the LPF 5 during the frequency divider reset mode and the level of the frequency control voltage VF when the PLL operation mode is restarted are both the same as the frequency division pulse CO and the input pulse IN. These differences are small since they are obtained when PLL is in a predetermined phase relationship.
When switching to the operating mode, the oscillation frequency of the VCO1 hardly changes. Therefore, even if the switch 4 is turned on and the PLL operation mode is restarted, the input pulse IN and the frequency-divided pulse CO are kept in phase synchronization.

Next, a specific example of each block in FIG. 1 and its operation will be explained.

FIG. 2 is a circuit diagram showing a specific example of the phase comparator 3 and LPF 5 in FIG. 1, in which 11 is a constant voltage source, 12 to
14 is a resistor, 15 is an NPN transistor, 16 is a capacitor, 17 is a Zener diode, 18 is a switch, 19
is a voltage follower type amplifier, 20 is a switch, 21 is a resistor, and 22 is a capacitor.

In the figure, the phase comparator 3 includes a constant voltage source 11 and a resistor 12.
~14, a constant current power supply circuit consisting of an NPN transistor 15, a capacitor 16, a Zener diode 17,
It is composed of a switch 18, a voltage follower type amplifier 19, and a switch 20.

The output voltage v8 of the constant voltage source 11 is divided by a resistor 12.13 and applied to the base of the NPN transistor 15, and the emitter of this NPN transistor 15 is applied to the resistor 14.
is grounded through.

The collector of this NPN transistor 15 and one terminal of the capacitor 16 are connected to the constant voltage source 1 through a switch 18.
1, and the other terminal of the capacitor 16 is grounded. Further, the collector of the NPN transistor 15 is connected to the anode of a Zener diode 17, and the cathode of the Zener diode 17 is connected to the constant voltage source 11.

Switch 18 receives the divided pulse C from frequency divider 2 (FIG. 1).
The capacitor 16 is turned on during the pulse period of O, and during this period the capacitor 16 is charged to the output voltage v of the constant voltage source 11 via the switch 18. When switch 18 is turned off, capacitor 16 is N
A portion of the current i is passed through the PN transistor 15 and the resistor 14.
is discharged. Therefore, as shown in FIG. 3(a), the charging voltage v0 of the capacitor 16 is the pulse period V! of the frequency division pulse CO! Then, after the 1-frequency division pulse CO has passed, it falls linearly. When the charging voltage Vc drops transiently, the current stabilization characteristics of the constant current source circuit made up of the resistors 12 to 14 and the NPN transistor 15 deteriorate, but the Zener diode 17 prevents this. Due to this Zener diode 17, the charging voltage v0 is stabilized by dropping to <vz-vz>, where v2 is the conduction voltage of the Zener diode 17.

The charging voltage vc of the capacitor 16 is supplied to the switch 20 via the voltage follower type amplifier 19, but as is already known, the voltage follower type amplifier 19 has an extremely large input impedance and a voltage gain of 1. Since there is a circuit connected to the output side, the charging voltage V on the input side
C, thereby reducing the charging voltage v0
is faithfully output from the voltage follower type amplifier 19.

The switch 2o is turned on during the pulse period of the input pulse IN.

Thereby, the charging voltage Vc is sampled by this input pulse IN. That is, as shown in FIG. 3(, ), the switch 20 outputs a voltage pulse having a voltage value V- of the charging voltage v0 at the timing of the input pulse IN. The voltage value V- of this voltage pulse corresponds to the phase difference between the frequency-divided pulse CO and the input pulse IN. This voltage pulse is LP as the phase detection voltage Vp of the phase comparator 3.
Supplied to F5.

Although the switch 4 in FIG. 1 is omitted, the switch 20 can also serve as the switch.

The LPF 5 consists of a resistor 21 and a capacitor 22. The capacitor 22 is charged by a voltage difference V between the charging voltage immediately before the input pulse IN is supplied and the phase detection voltage vP, or is discharged by this voltage difference via the resistor 21 and the switch 20. be done.

For this reason, the charging voltage of the capacitor 22 is as shown in FIG. 3(b).
This changes as shown by the broken line, and this becomes the frequency control voltage v2 of the VCOI (Fig. 1).

Generally, in a vCO used in a PLL-configured synchronous pulse generator, a variable capacitance diode whose capacitance value changes depending on the applied voltage is used as an oscillation diode. This variable capacitance diode has a characteristic that the higher the applied voltage, the lower the capacitance, and the lower the capacitance, the higher the oscillation frequency of vCO. Therefore, when the phase difference T between the 1-frequency division pulse CO and the input pulse IN becomes smaller in the figure 3), the charging voltage of the capacitor 16 (Figure 2) decreases. Since the voltage value V at the timing of the input pulse IN increases, the one-frequency control voltage V increases, and the oscillation frequency of the VCOI (FIG. 1) increases. For this reason, the cycle of the one-frequency pulse CO becomes shorter and its phase advances, and the phase difference T between this and the input pulse IN increases. When the phase difference T between the frequency division pulse CO and the input pulse IN becomes longer, the frequency control voltage VF decreases and the VCO
The oscillation frequency of 1 decreases, the period of the 1-frequency divided pulse CO increases, and the phase difference T between this and the input pulse IN decreases.

As described above, when the phase difference T between the frequency division pulse co and the input pulse IN changes, the frequency control voltage V changes.

changes, the oscillation frequency of the VCOl changes, and this phase difference T returns to the original specified value, but if the pulse width Tw of the input pulse IN changes, the second T.

may fluctuate and malfunction.

That is, the capacitor 22 of the LPF 5 is charged during the pulse period Tw of the input pulse IN when the switch 20 is turned on, and since the charging voltage vc of the capacitor 16 is sloped, when this pulse ll'rw fluctuates, the capacitor 22
The charging voltage, that is, the frequency control voltage vF, also fluctuates and V
The oscillation frequency of CO1 also varies. In order to prevent this, a switch that turns off the pulse period TW of the input pulse IN may be provided in the discharge circuit consisting of the NPN transistor 15 and the resistor 14. When this switch is turned off, the capacitor 16 stops discharging. Pulse period Tw charging voltage of input pulse IN. is the leading edge of the input pulse IN (Fig. 2(b)
) is held at the voltage value at time t). Therefore, the voltage value of the charging voltage Vc when the switch 20 is turned on is held constant, and the charging voltage of the capacitor 22 is changed by the input pulse IN.
It becomes unaffected by the pulse @TW.

By the way, when performing a PLL operation using a phase comparator, the value that stably converges the phase difference T between the frequency-divided pulse CO and the input pulse IN (that is, the convergence value of one phase difference T) is theoretically When the frequency of the input pulse IN increases or decreases around a certain value (center frequency), when the frequency is high, the convergence value of the phase difference T, is higher than when the frequency is at the center frequency. On the contrary, when the frequency is low, this convergence value becomes large. A phase difference T occurs due to the difference in frequency of the input pulse IN.

In order to reduce the fluctuation range of the convergence value of , the slope of the gradual decrease characteristic of the charging voltage Vc of the capacitor 16 shown in FIG. 3 must be made steep.

Also, even if the phase of the input pulse IN jumps,
In order to rapidly bring the phase difference T to a convergent value in the PLL operation mode, conventionally, the waveform of the charging voltage Vc of the capacitor 16 must be made into a sawtooth waveform, as shown by the broken line in FIG. did not become.

In consideration of the above points, it is necessary to increase the operating power supply voltage of the phase comparator, and the steeper the charging voltage slope, the higher the operating power supply voltage must be. However, with modern electronic devices.

From the perspective of power saving, the operating power supply voltage of circuits is being lowered, and for this reason, if you try to increase the operating power supply voltage of the phase comparator, you will need a dedicated power supply separate from the main power supply. A circuit is required, which increases manufacturing costs.

On the other hand, in the conventional VC○ made of an LC oscillator, since the amount of change in the oscillation frequency with respect to the change in the frequency control voltage is large, the characteristics of the charging voltage Vc are set as shown by the broken line in Fig. 3(a). Also, the operating power supply voltage can be set to a relatively low voltage of about IOV. On the other hand, in recent years, a VC○ has been developed that has higher frequency stability than LC oscillators using ceramic resonators or tantalate resonators, and when this is adopted in a synchronous pulse generator with a PLL configuration, the Charging voltage Vc with the characteristic shown by the broken line in (8)
In order to obtain good performance, the operating power supply voltage of the phase comparator must be very high, on the order of several tens of volts, and a dedicated power supply circuit is required as described above.

In the embodiment shown in FIG. 1, the characteristics of the charging voltage vc are
By setting as shown by the solid line in Figure (a), the operating power supply voltage of the phase comparator 3 is lowered to ensure phase synchronization performance by PLL operation near the convergence value of the phase difference T, and the input pulse IN is For phase jumps, a frequency divider reset mode is used to prevent deterioration of the pull-in performance. As a result, an oscillator with high frequency stability can be used as the VCOl, and the effects of power supply ripples and noise pulses can be prevented.

Next, a specific example of the switching pulse generation circuit 6, frequency divider 2, and noise gate 7 for setting each mode shown in FIG. 1 will be explained with reference to FIG. 4. In addition, in the same figure, 23
is a counter, 24 is a decoder, 25 is a DFF (D-type flip-flop circuit), 26 is an OR circuit, 27 is a TFF
(T-type flip-flop circuit), 28 is a DFF, 29 is an AND gate, 30 is an OR circuit, 31.32 is an AND gate, 33.34 is a DFF, 35 is an inverter, and 36 is an AND gate. Parts corresponding to those in FIG. 2 are given the same reference numerals.

First, the frequency divider 2 will be explained with reference to FIG. 5, which shows signal waveforms at various parts when the counter value of the counter 23 is near zero.

As explained earlier, the output pulse OUT of vCol is 1
The frequency is approximately n times the average frequency f0 of the input pulse IN, and is supplied to the counter 2 and counted at its rising edge. The counter 23 is reset to zero every time a reset pulse R8T is supplied from the OR circuit 26.

The count value of the counter 23 is decoded by the decoder 24, and when this count value approaches n, a pulse 24C is first generated at a predetermined value, and then a frequency division pulse CO is generated at a predetermined value. Then, the count value is (n-
1), pulse 24B is generated and provided as a data input to DFF 25. In the DFF 25, the data input is taken on the falling edge of the output pulse OUT of the VCOL, and for this purpose, when the pulse 24B is supplied,
At the falling edge of the first output pulse OUT after the generation of this pulse 24B, the pulse 2 is output from the Q output terminal of the DFF 25.
Pulse 25Q having the same level as 4B is output. This pulse 25Q passes through the OR circuit 26, and the reset pulse R8
The counter 23 is reset as T.

Therefore, the next time the output pulse OUT is supplied,
The count value of the counter 23 is zero.

The pulse 24B is no longer output from the decoder 24.

At the falling edge of this output pulse OUT, the DFF 25 no longer outputs the pulse 25Q, and therefore the counter 2
3 is 1 from the next output pulse OUT after the reset is released.
．． 2,3. ...and counting. In this way, the counter 23 repeatedly counts from zero to (n-1).

Decoder 24 also outputs pulse 24E from the trailing edge of frequency-divided pulse CO. This pulse 24E is
VCOI output pulse OU when the count value of 3 is zero
The periods before and after the rising edge of T have the same pulse width. At the predetermined count value of the counter 23 that has elapsed for a predetermined time from the trailing edge of this pulse 24H, the decoder 2
4 outputs pulse 24D.

As will be described later, the counter 23 is controlled so that the rising edge of the output pulse OUT of the VCO1 when the count value is zero coincides with the rising edge (previous #) of the input pulse IN. The time difference between the edge and the falling edge (trailing edge) of the divided pulse CO is shown in Figure 3 (
This is the convergence value of the phase difference T shown in b). therefore,
The pulse width of the pulse 24E output from the decoder 24 is set to twice this convergence value.

Next, the noise gate 7 will be explained using FIG.

When the frequency divider 24 outputs the pulse 24C, the pulse period TFF 27 is reset, the output signal 27Q from the Q terminal becomes "L" (low level), and the output signal 27ζ from the ζ terminal becomes l#H+1 (high level). level). Here, the timing of the input pulse IN from the input terminal 1 is between the rising edge of the pulse 24C and the falling edge of the pulse 24D, and this output signal 27 is 14 HTj
, this input pulse IN passes through the AND gate 31. The input pulse IN passing through the AND gate 31 becomes the output pulse No of the noise gate 7. This output pulse NO further passes through an OR circuit 30, and the TFF 27 is triggered at its falling edge. As a result, the output signal 27ζ of the TFF 27 becomes "H'" and the output signal 27ζ becomes "L'", and even if a pulse is input from the input terminal 1 thereafter, it does not pass through the AND gate 31.

After that, the decoder 24 outputs the pulse 24D, but at this time, the output signal 28Q of the Q terminal of the DFF 28 is
Assuming L 11 , pulse 24D is blocked by AND gate 29 . Here, the DFF 28 uses the output signal 27Q of the TFF 27 as a data input, and takes this in at the falling edge of the pulse 24D (later I#4).As mentioned earlier, before the pulse 24D is supplied, the output signal of the AND gate 31 At the falling edge of No (this is the input pulse IN), the output signal 27ζ of the TFF 27 is "L", and the output signal 2
Since 7Q is at "H", the DFF 28 takes in the output signal 27Q of 44 Hlj at the falling edge of pulse 24D, and its output signal 28Q becomes "H".

Hereinafter, when the input pulse IN is between the rising edge of the pulse 24C and the falling edge of the pulse 24D, the output signal 270 of the TFF 27 is "H11" when the input pulse IN is supplied, and this input pulse IN
passes through the AND gate 31. At this time, DFF28
The output signal 28Q of is held at ``H'', but the signal 270 of ``L'' is also supplied to the AND gate 29 as a gate signal, and therefore, the pulse 24D is output from the decoder 24 after the input pulse IN. However, this pulse 2
4D is blocked by AND gate 29, and this pulse 24D
TFF 27 is never triggered by this. Therefore, the output signal 27'iQ of TFF27 is changed from the rising edge of input pulse IN to TFF2 at pulse 24C.
Its output signal 27Q is “L I
It is held in I.

In addition, the output signal 28Q of DFF28 is also 14H”
is maintained.

Therefore, the noise pulse inputted from the input terminal 1 after the input pulse IN is blocked by the AND gate 31.

If the input pulse IN is not between the rising edge of the pulse 24C and the falling edge of the pulse 24D from the decoder 24, the TFF 27 is reset by the pulse 24C, and its output signal 27Q becomes #L #l, and the output signal 27
After ζ reaches re H#, the decoder 24 provides a pulse 24D.

At this time, when the output signal 28Q of the DFF 28 is 1'I)'', this pulse 24D is supplied to the TFF 27 through the AND gate 29° OR circuit 30, and the TFF 2
7 is triggered by the falling edge of this pulse 24D, and its output signal 27Q becomes "H"'.

Output signal 27? :5 is shown by the broken line in Figure 6.
However, the output signal 27Q just before that becomes “L It”.
D, the DFF 28 takes in the #L ## output signal 27Q at the falling edge of the pulse 24D, and the output signal 28Q becomes 'L' as shown by the broken line in FIG. 6. For this reason, Even if an input pulse IN is supplied from input terminal 1 after pulse 24D, it does not pass through AND gate 31.

In this way, the output signal 28Q of the DFF 28 is “L II
In this case, or when the above output signal 28Q is not "H" but II L #+, even if the pulse 24D is supplied after the TFF 27 is reset by the pulse 24C, this pulse 24D is blocked by the AND gate 29. , TFF27 is not triggered and its output signal 2
7Q is (l L 19).

27Q remains at "H".

Then, when an input pulse IN is supplied after this pulse 24D, this passes through the AND gate 31.

The TFF 27 is triggered by the falling edge, the output signal 27Q becomes "H71", and the output signal 27Ω becomes "L F
It becomes F. In addition, if there is no input pulse IN, the output signal 27Q becomes L'', and the output signal 27ζ becomes EI H7.
7 respectively.

As described above, when the input pulse IN is between the rising edge of the pulse 24C and the falling edge of the pulse 24D, the output signal 28Q of the DFF 28 becomes jj Hlj
However, the input pulse IN is held at these pulses 24C.
, , 24D, the output signal 28Q of the DFF 28 is held at II L 12 and pulse 2
4D is blocked and the output signal 27iQ of TFF 27 is set to “H”.
'', the AND gate 31 is opened, and an operation is performed to search for the input pulse IN.

Here, as shown in FIG. 6, the period from the rising edge of the pulse 24C to the falling edge of the pulse 24D is set as the phase synchronization operation execution mode, and the period other than this is set as the phase synchronization operation inhibition mode. Also.

During the phase synchronized operation execution mode, pulse 24E
The pulse period is set as the PLL operation mode, and the other period is set as the frequency divider reset mode.

Here, the pulse period of the pulse 24E which becomes the PLL operation mode is set equal to the slope period of the voltage v0 in FIG. When there is an input pulse IN during this period, as explained in FIG.
is pulled into the phase of the input pulse IN by the action of . In addition, during the period of the 1-phase synchronized operation execution mode, the time when the count value of the counter 23 becomes zero is the center point.
The length is set to be larger than the maximum phase jump amount that the input pulse IN takes before and after that. Input pulse IN to V
Assuming that it is the reproduction horizontal synchronization signal of TR, this human pulse IN
The repetition period is about 63.6 μsec, and a phase jump occurs when switching heads, but the amount of this phase jump is set to be about 5 μSeQ at the maximum. In this case, the period of the phase synchronized operation execution mode is, for example, six times before and after the time when the count value of the counter 23 becomes zero.
The length is set to about μsec, that is, about 12 μsec.

If there is a phase jump in the input pulse IN while in the PLL operation mode, the 1 divider reset mode is set, the counter 23 is reset with the input pulse IN, and the divided pulse co is forced to phase synchronize with the input pulse IN. I'll do what I do. Furthermore, at startup or in the event of an abnormality such as a lack of input pulse IN, the phase synchronization operation prohibition mode is set, and the output signal 27? of the TFF 27 is set as described above. :5 JIH”
The period is extended and the search for the input pulse IN is performed.

As described above, the noise gate 7 removes the noise mixed in the input pulse IN in the phase synchronization operation execution mode, and searches for the input pulse IN in the phase synchronization operation prohibition mode.

The switching pulse generation circuit 6 receives the pulse 2 from the decoder 24.
4E and the output pulse NO of the AND gate 31, the AND gate 32 which is the switch 8 is activated according to each mode described above.
It also generates a switching pulse for the switch 20 in the phase comparator 3. The switching pulse generation circuit 6 will be explained below using FIG. 7.

Pulse 24E is provided as a data input to F F 33 and is captured on the rising edge of output pulse NO of AND gate 31. Also, pulse 24
D is inverted by an inverter 35.

Its output pulse 24E is provided to DFF 34 as a data input. In this DFF 34, the data input is the rising edge of the output pulse No. of the AND gate 31.

It is also reset during the it H11 period of the output signal 33Q of the Q terminal of the DFF 33.

This output signal 33Q becomes the gate signal of the AND gate 36, and the output signal 34Q of the Q terminal of the DFF 34 becomes the gate signal of the AND gate 32.

Now, assuming that the input pulse IN is within the pulse period of the pulse 24E, as shown in FIG. 7(a), the DFF 33
Then, the "H" pulse 24E is taken in at the rising edge of the output pulse NO of the AND gate 31, and the output signal 33
Q becomes "H'". Therefore, the output pulse No of the AND gate 31 passes through the AND gate 36 and turns on the switch 20 of the phase comparator 3 as a sampling pulse SP.

Here, since the pulse period of the pulse 24E coincides with the ramp period of the voltage v0 in FIG. 3, the voltage V is increased by turning on the switch 20, as explained in FIG. By sampling the 1-frequency pulse CO and the input pulse IN, a phase comparison is performed. Also, DFF3
3 output signal 33Q becomes 11H", DF
F34 is reset and its output signal 34Q becomes "L". For this reason, the AND gate 32 is turned off, and the AND gate 3 of the output pulse No. of the AND gate 31 is turned off.
Passage of 2 is prohibited.

The above operation is the setting of the PLL operation mode.

When the input pulse IN is outside the pulse period of the pulse 24E, as shown in FIG. 7(b), the input pulse IN,
Therefore, at the rising edge of the output pulse No of the AND gate 31, the data input to the DFF 33 is "L", so its output signal 33Q becomes "L". For this,
AND gate 36 is held in an off state to block the output pulse NO of AND gate 31. As a result, the switch 20 of the phase comparator 3 is turned off.

Furthermore, since the output signal 33Q of the DFF 33 is L'', the reset of the DFF 34 is released, and the DFF 34 is reset at the rising edge of the output pulse NO of the AND gate 31.
Since the data input 24F of 34 is "11H", its output signal 34Q is "H".
2 becomes on state, and the output pulse N of the AND gate 31
O passes through this AND gate 32 and resets the counter 23 via the OR circuit 26 as an external reset pulse 32R.

The above operation is the setting of a mode other than the PLL operation mode.

Each block in Fig. 4 has been explained above, but next,
In the specific example shown in FIG.
This section explains the operation when abnormalities occur due to missing pulses, noise pulses, phase jumps, etc.

First, the transient period will be explained using FIG. 8, where 1 time txt txt . . . indicates each timing of the input pulse IN.

During a transient period, the phase relationship between each output pulse of the 1 frequency divider 2 and the input pulse IN is random.

Here, the human power pulse IN at time t1 is input to the decoder 24.
It is assumed that the input is after the pulse 24D from .

Therefore, the phase synchronization operation prohibition mode is set.

Therefore, before time t1, TF is
F27 is reset and its output signal 270 is “H”
Tonaruka, Konotoki, DFF2B output signal 28Q is 4
1 H17, the next pulse 24D passes through the AND gate 29 and the OR circuit 30, triggers the TFF 27, and outputs its output signal 27? : Set l to It L II. Further, at the falling edge of the pulse 24D just before that, the output signal 28Q of the DFF 28 becomes II L II. therefore,
Even if there is an input pulse IN at time t□, it is blocked by the DFF 31.

From time tU to t3, the TFF 27 is reset by the pulse 24C and its output signal 27ζ becomes "H", but even if there is a primary pulse 24D, this means that the output signal 28Q of the DFF 28 is "17L". by andgate 2
9, and the output signal 270 of the TFF 27 is held at 'H' as it is.

After that, when there is an input pulse IN, it passes through the AND gate 31 and becomes a pulse No. This pulse NO triggers the TFF 27 via the OR circuit 30, causing its output signal 270 to become L'''.

Furthermore, at the rising edge of this pulse No., the data input of 0FF33 is "L II", so its output signal 33
If Q is originally '1 Hl#, it becomes "L".

As a result, the DFF 34 that was in the reset state is released from reset. In the DFF 34, the output pulse NO of the AND gate 31 is supplied immediately before the reset is released, so the output signal 34Q is kept at "L 7+". Therefore, both the AND gates 36 and 32 block the pulse NO. Therefore, the counter 23 is not reset, and the output pulse of the frequency divider 2 and the input pulse I
The phase relationship with N remains almost unchanged.

From time t2 to t□, TFF 27 is reset by pulse 24C in the same way as above, and its output signal 270 becomes '
The input pulse IN passes through the AND gate 31 and triggers the T I'' F 27 at time t3. At this time as well, in the DFF 33, the data input is #L 11 at the rising edge of the output pulse No of the AND gate 31, so the output signal 33Q is held at It L II, and the DFF 34 is held in the reset release state. In this DFF 34, the output pulse No. of the AND gate 31
Since the data input 24E is at "H71" at the rising edge of , its output signal 34Q becomes LIH.

Therefore, the AND gate 36 blocks the output pulse NO of the AND gate 31, but the AND gate 32 allows this output pulse NO to pass. This pulse NO is applied to the counter 2 via the OR circuit 26 as an external reset pulse 32R.
Reset 3. As a result, the phase of each output pulse of the frequency divider 2 is changed so that the input pulse IN enters within the period from the rising edge of the pulse 24C to the falling edge of the pulse 24D.

This causes a transition from the phase synchronized operation prohibition mode to the phase synchronized operation execution mode shown in FIG. 6, where the input pulse IN at time t4 is It is assumed that the period from the rising edge of pulse 24C to the rising edge of pulse 24E has entered.

Therefore, the frequency divider reset mode shown in FIG. 6 is set.

In this case, when the TFF 27 is reset by the pulse 24C and its output signal 270 becomes "H", the input pulse IN is supplied at time t4, and the AND gate 3
1 to trigger TFF27. As a result, the output signal 27ζ of this TFF 27 becomes "itL", and at the same time, the output signal 27Q of the TFF 27 becomes "IJH", so at the falling edge of the next supplied pulse 24D, the DFF2
The output signal 28Q of No. 8 becomes "H".

In the DFF 33, the data input at the rising edge of the output pulse NO of the AND gate 31 is "L", so its output signal 33Q is held at "L", and the DFF
34 is held in a reset release state. For this reason, the output signal 34Q of this DFF 34 is also held at "H".

Then, the output pulse NO of the AND gate 31 passes through the AND gate 32, thereby resetting the counter 23 again. At this time, the AND gate 36 blocks this output pulse No.

In this way, the phase of the output pulse of frequency divider 2 is further changed, so that the input pulse IN is changed to pulse 24E.
It will fall within the pulse period of .

The PLL operation mode shown in FIG. 6 will be entered.

It has been explained that the input pulse IN at time t enters within the period from the rising edge of pulse 24C to the rising edge of pulse 24E and is transferred from the frequency divider reset mode to the PLL operation mode. input pulse I of
The same is true if N falls within the period from the falling edge of pulse 24E to the falling edge of pulse 24D.

When entering PLL operation mode, TF is activated by pulse 24C.
When F27 is reset, a pulse 24E is supplied next, and an input pulse IN is supplied at time t within the pulse period of this pulse 24E, and passes through an AND gate 31 to T.
Trigger FF27. Thereafter, pulse 24D is supplied.

Since the output signal 270 of the TFF 28 is "L pv", this pulse 24D is blocked by the AND gate 29, so that the TFF 27 is not triggered, its output signal 27Q is "Hpt", and the output signal 27ζ is "L pv". ” will be retained as is.

In the DFF 33, the data input is an H'' pulse 24E at the rising edge of the output pulse NO of the AND gate 31.
Therefore, the output signal 33Q is inverted from "L" to "H". In the DFF34, this output signal 33Q
By inverting to "HIt", the Ij upper set state is entered.By the way, the rising edge of the output pulse NO of the AND gate 31 as the clock of the DFF34 is
4 is about to enter the reset state, ]) FF34
Now, the output signal 24E of the inverter 35 is taken in as a data input, but at this time, this data input is "L"'
Therefore, the output signal 34Q is inverted to 11 L II.

Therefore, the AND gate 32 blocks the output signal No of the AND gate 31, and the counter 23 is no longer reset. Further, the AND gate 36 is turned on by the "H" output signal 33Q of the DFF 33. and gate 31
The output pulse NO passes through the AND gate 36 and turns on the switch 20 of the phase comparator 3 as a sampling pulse SP.

In this way, the VCOI, frequency divider 21 phase comparator 3.
The PLL configuration consisting of LPF5 operates and the divided pulse co
The oscillation frequency of the VCOl is controlled so that the phase difference T between the input pulse IN and the input pulse IN is stabilized at a converged value.

Next, the operation when there is a drop in the input signal IN or a noise pulse will be explained with reference to FIG.

However, in the same figure, t, ta + t
4... indicates each timing of the input pulse IN.

It is now assumed that the PLL operation mode is in effect until the input pulse IN at time 11/. Therefore, at this time, D
Output signal 28Q of FF28 and output signal 33 of DFF33
Q is “H” and the output signal 34Q of DFF34 is “L”.
” is.

Next, if the input pulse IN that should be input at time t2' within the pulse period of pulse 24E is missing, then T
After the FF27 is triggered by the pulse 24C and its output signal 27ζ becomes it Hpp, since there is no input pulse IN and the output signal 28Q of the DFF28 is "H17", the TFF27 is triggered by the falling edge of the next pulse 24D. The output signal 27Q becomes "L".At the same time, at the falling edge of the pulse 24D, the output signal 27Q becomes "L".
The output signal 28Q becomes "Ln".

At this time, the output pulse N of the AND gate 31.

Therefore, the output signal 33Q of DFF33 remains “
The DFF 34 is held in the reset state and the output signal 34Q is held in the "L" state.For this reason, the AND gate 36 is in the on state, but the switch 20 of the phase comparator 3 remains in the "L" state. held in the off state, V
CO1 is controlled by the frequency control voltage VF at the level (FIG. 2) held by the LPF5. Therefore, the oscillation frequency of VCO1 hardly changes.

So, when an input pulse IN is next supplied at time t,', which is within the pulse period of pulse 24E, this input pulse IN passes through AND gate 31 and triggers TFF 27.

Therefore, at the timing of pulse 24D, TFF27
The output signal 27Q of the DFF 28 becomes "HII" at the falling edge of the pulse 24D.

This means that the system has returned to the PLL operation mode again.

If the input pulse IN is missing at time 1, /, since the output signal 28Q of the DFF 28 is "L", the pulse 24D is blocked by the AND gate 29, and the pulse 24D from time t to t3 in FIG. The state is the same as before, and the output signal 27Q of the DFF 27 is held at "HII" as it is, and the search for the input pulse IN is performed.During this time,
VCOl is controlled by the frequency control voltage V at the level maintained by the LPF 5, and its oscillation frequency hardly changes. For this reason, when the input pulse IN is supplied after the omission, this input pulse IN is within the pulse phase feed of pulse 24E, and when the input pulse IN is supplied at time 1, / in FIG. Similarly, the PLL operation mode is reset.

As described above, when the input pulse IN is missing only once, the AND gate 31 is turned off in synchronization with the pulse 24D, and malfunctions due to noise pulses are prevented by assuming that the input pulse IN is simply missing. There is. If the input pulse IN is missing two or more times in a row, it is not regarded as a mere omission of the input pulse IN, but the AND gate 31 is kept on to search for the input pulse IN. This is particularly effective when the input pulse IN is the reproduced horizontal synchronizing signal of the VTR. This reproduced horizontal synchronization signal is often lost due to dropouts. If the search for the input pulse IN is performed immediately every time this omission occurs, malfunctions may occur due to noise pulses, but in this specific example,
This can be prevented.

Furthermore, at the joints of programs on magnetic tape, the phase of the horizontal synchronization signal may become largely discontinuous, but in such cases, the input pulse IN will be dropped more than once (
In reality, the input pulse IN is in a period other than between pulses 24C and 24D), and the search for the input pulse IN is performed at the second omission. This search operation is similar to that shown in FIG.

In this way, even if there is a dropout in the reproduced horizontal synchronization signal due to dropout, or even if there is a discontinuous portion such as a seam between one program, the PLL operating mode can be quickly restored.

In addition, a further DFF is connected in cascade after the DFF28,
By using the output signal of the final stage DFF as the gate signal of the AND gate 29, it is possible to search for the input pulse IN only when the input pulse IN is missed a desired number of times, ie, three or more.

By the way, when in the PLL operation mode, the noise pulse mixed into the input pulse IN has an effect on when the AND gate 31 is in the ON state from the rising edge of the pulse 24G to the falling edge of the input pulse IN. When it is within the period. At other times, the noise pulse is blocked by the AND gate 31.

Therefore, in FIG. 9, during the PLL operation mode, time t
, ' and the rising edge of pulse 24C immediately before pulse 24
Assuming that there is a noise pulse N at time 1° between the rising edge of H, this noise pulse N is generated by the AND gate 31.
, and triggers TFF27. For this reason, the output signal 27Q becomes "L'", and the immediately following time t4
' input pulse IN is blocked by the AND gate 31.

However, even if the pulse 24D is supplied, the output signal 28Q of the DFF 28 is maintained at tiH'', and
The state of TFF 27 is not reversed.

On the other hand, when noise pulse N is output from AND gate 31 as pulse NO, this pulse N.

At the rising edge of , the data input of DFF33 is "L'"
Therefore, the output signal 33Q is inverted to 11 L 11. However, the output signal 34Q of the DFF 34 is held at "L" as it is.

As a result, the output pulse No of the AND gate 31, which is the noise pulse N, is blocked by the AND gate 36, the phase comparator 3 and the LPF' 5 are cut off, and the frequency control voltage V is maintained at the level maintained by the LPF5.

VCOl is controlled by . Therefore, VCOl is not affected by the noise pulse N, and its oscillation frequency hardly changes.

Then, when the next input pulse IN is supplied at time ts', this input pulse IN is within the pulse period of pulse 24E and passes through AND gate 31.

The output pulse number of this AND gate 31 is the TFF 27
Since the rising edge of this pulse NO is in the pulse period of the pulse 24E, the output signal 33Q of the DFF 33 becomes "H" again.

In this way, the PLL operating mode is set again.

When the noise pulse N is immediately before the input pulse IN within the pulse period of the pulse 24E, this noise pulse N passes through the AND gate 36 as the pulse NO, so that the frequency control voltage ■? corresponds to the phase of this noise pulse N, and the oscillation frequency of VCOl changes slightly, but when the next input pulse IN is still within the pulse period of pulse 24E, the input pulse IN and the divided pulse CO immediately change. VC so that the phase difference T, becomes the original convergence value.
OI is controlled.

If there is a time axis fluctuation in the input pulse IN, the noise pulse N
When the oscillation frequency of the VCO1 fluctuates as described above, the input pulse IN, which was previously within the pulse period of the pulse 24E, may deviate from this pulse period. Furthermore, due to a phase jump in the input pulse IN, the input pulse IN may deviate from the pulse period of the pulse 24E.

The operation in this case will be explained with reference to FIG.

Now, the PLL operation mode is in effect until the time point t when the input pulse IN is generated, and immediately after that, due to the above-mentioned reasons, the next input pulse IN is delayed from the time indicated by the broken line at time t, II.
Assume that the current is supplied between pulses 24E and 24D.

At this time as well, the input pulse IN passes through the AND gate 31, but since the rising edge of the output pulse No. is outside the pulse period of the pulse 24E, the output signal 33Q of the DFF 33
becomes “L 11,” and the AND gate 36 reads this pulse “N”.
Prevent O. Further, at this time, since the DFF 34 has not yet been reset by the rising edge of the pulse No, its output signal 34Q is held at "it L", thereby causing the AND gate 32 to block the pulse NO.

Therefore, VCOl is controlled by the frequency control voltage V at the level held in the LPF 5, the counter 23 is not reset by the external reset pulse 32R, and the phase relationship between the input pulse IN and each output pulse of the frequency divider 2 is It doesn't change.

When the next input pulse IN is supplied at time t,' which is one cycle later than time t2'', this input pulse IN also passes through the AND gate 31, but it is shifted from the pulse period of pulse 24E. , the output signal 33Q of the DFF 33 is held at "L II" as it is, and since the DFF 34 is in the reset release state and the data input is "H) I" at the rising edge of the output pulse No of the AND gate 31, the output signal 34Q becomes “H” and AND gate 3
2 becomes on state, and the output pulse N of the AND gate 31
O passes through AND gate 32 and causes counter 23 to be reset.

As a result, the phase of the output pulse of the frequency divider 2 changes by the amount of phase variation of the input pulse IN, and the next input pulse IN at time t4' enters the pulse period of the pulse 24E.

Therefore, at the rising edge of pulse No caused by input pulse IN passing through AND gate 31, in DFF 33, since the data input is "H", its output signal 33Q is inverted from "L II to xi Hn," DFF
At 34, since the data input is "L", the output signal 34Q is inverted from "H" to "L" 71. As a result, the PLL operation mode is set again. From this point on, the output signal of the DFF 33 33Q is held at “HTj, and 0FF34 is the output signal 33Q of this tt Hpp.
Since it enters the reset state, its output signal 34Q
is held as “L Hl. Therefore, PL
The L operating mode continues.

Note that during the operation of 1 or more, the output signal 28Q of the DFF 28 is 1.
It is held at 'H'.

The operation of the specific example shown in FIG. 4 can be summarized as follows.

(i) In the PLL operation mode, the noise gate 7 removes the noise pulse mixed into the input pulse IN with the AND gate 31, and the pulse period of this input pulse IN is passed through the phase comparator 3.
The divided pulse CO is turned on so that the switch 20 of
The phase difference T between the input pulse IN and the input pulse IN is set to a predetermined convergence value.

(it) When the input pulse IN is missing, the noise gate 7 limits the ON period of the AND gate 31 at the first loss and provides a grace period in which the counter 23 is not reset. If this dropout occurs only once, the PLL operation mode is reset from the first input pulse IN after this dropout, and if the dropout occurs multiple times in succession, the noise gate 7 starts from the second dropout. sets the AND gate 31 to a phase synchronization operation prohibition mode in which it continues its on period and searches for an input pulse IN.

In this phase synchronization operation prohibition mode, the AND gate 36 of the switching pulse generation circuit 6 is turned off, and the phase comparator 3 and LPF
When the input pulse IN is detected by the noise gate 7, the counter 23 is reset. This causes a transition to phase synchronization operation execution mode.

(■) Even if there is a noise pulse N before the pulse 24E during the ON period of the AND gate 31 in the noise gate 7,
The switching pulse generating circuit 6 simply separates the phase comparator 3 and the LPF 5, so that the counter 23 is not reset and enters the PLL operation mode with the next input pulse IN.

(iv) The input pulse IN undergoes a phase jump, and the pulse 24
When it enters between E and pulse 24D, the switching pulse generating circuit 6 also turns off the AND gate 36 to disconnect the phase comparator 3 and the LPF 5, but the first pulse after the phase jump At input pulse IN, AND gate 32 is turned off to prevent counter 23 from being reset. This is to prevent the counter 23 from being reset by a noise pulse that is mixed into the input pulse IN at the time of a phase jump and cannot be removed by the AND gate 31. When using the reproduced horizontal synchronizing signal from a VTR as the input pulse IN, noise pulses are often mixed into the input pulse IN during the phase jump of the input pulse IN when the head is switched. By providing such a grace period in which the counter 23 is not reset, it is possible to prevent the counter 23 from being erroneously reset due to mixed noise pulses.

Note that, as explained earlier, D in the noise gate 7
By cascade-connecting a predetermined number of DFFs to the Q terminal of the FF 28, it is possible to increase the grace period for the search operation for the input pulse IN due to the omission of the input pulse IN in the noise gate 7. By continuously connecting a predetermined number of DFFs to the Q terminal of the DFF 34 in 6, if a noise pulse is mixed in for a long time after the phase jump of the input pulse IN, a grace period is created in which resetting the counter 23 is prohibited during this period. can be increased.

Here, the reset operation of the frequency divider 2 in FIG. 4 by the external reset pulse 32R will be explained in detail with reference to FIG. 11.

The frequency divider reset mode is set, the input pulse IN passes through the AND gates 31 and 32, and the external reset pulse 32
When supplied as R to the counter 23, the count value of the pulse period counter 23 of this input pulse IN is held at zero. Here, the pulse width of the input pulse IN is VCOL
Assuming that it is sufficiently long compared to the period of the output pulse OUT,
The pulse period counter 23 of this input pulse IN does not count these output pulses OUT even if a plurality of them are supplied, and its count value is held at zero.

On the other hand, in the PLL operation mode, the DFF in the 1 frequency divider 2
The counter 23 is reset by a pulse 25Q having a pulse width equal to one period of the output pulse OUT of VCOl from 25, and after this counter 23 is released from reset, the VCO
Every time a predetermined number of L output pulses OUT are counted, the decoder 24 outputs each pulse. That is, in this case, by resetting the counter 23 by one period of the output signal OUT of the VCO1, the phase difference T between the input pulse IN and the frequency-divided pulse co is set to a predetermined convergence value. .

On the other hand, as described above, the pulse width of the input pulse IN is sufficiently longer than the period of the output signal OUT of the VCO1, and as shown in FIG.
When the counter 23 starts to be reset by this input pulse IN, since the reset period of the counter 23 is long, each pulse such as the frequency-divided pulse CO output from the decoder 24 after this reset is canceled is input at the next time t2. The phase with respect to the rising edge of the pulse deviates from the normal phase (phase in PLL operation mode) by approximately the pulse period of the input pulse IN, and the difference between the divided pulse CO set in the circumference set mode and the input pulse IN by this amount The phase difference T, will deviate greatly from the convergence value. For this reason, when transitioning from the frequency divider reset mode to the PLL operation mode, this phase difference T.

A transient control operation of the VCO1 is performed to bring the value close to the convergence value.

To prevent this, input pulse IN in divider reset mode.
In order to set the phase difference T between the frequency-divided pulse CO and the frequency-divided pulse CO to almost a convergent value, a differentiating circuit or a monostable multivibrator circuit is provided at the next stage of the AND gate 32, and the AND gate 3
A narrow pulse width pulse may be formed from the output pulse 32R of the AND gate 32 as an external reset pulse for the counter 23, or alternatively, it may be set at the rising edge of the output pulse 32R of the AND gate 32.

Falling edge of output pulse OUT of VCOl (after ta>
The S-R type flip-flop circuit that is reset by
If a DFF whose clock is T is used, a pulse with a pulse width equal to one period of the output pulse OUT is obtained from this DFF, and this may be used as an external reset pulse for the counter 23, or other known means can be used. The pulse width of the external reset pulse of the counter 23 may be narrowed by using the .

As described above, in this embodiment, the phase synchronization operation execution area is broadly divided into a phase synchronization operation execution area and a phase synchronization operation inhibition area according to the phase relationship between the input pulse IN and the frequency-divided pulse co. It is divided into a PLL operating region and a frequency divider reset region, and in the PLL operating region, VCOL is controlled according to the phase difference T# between the input pulse IN and the divided pulse CO so that this becomes a converged value. , input pulse I
If there is a phase jump in N, the mode in the divider reset region
mode and resets the frequency divider to enter the PLL operating region. For this, the phase difference T.

Even if the PLL operating region is a narrow range centered on the convergence value of The slope of the voltage VC (FIG. 3) generated by the phase comparator 3 can be made steep without using a power supply circuit.

Therefore, the VCOL is not affected by power supply ripples, etc., and has high responsiveness to phase fluctuations of the input pulse IN.

FIG. 12 is a block diagram showing another specific example of the phase comparator 3 in FIG.
9 is an AND gate, and parts corresponding to those in FIG. 1 are given the same reference numerals.

A specific example of this will be explained with reference to FIG. 13 showing the waveforms of each signal. The one-phase comparator 3 consists of a monomulti 37 and a sampling switch 38. The monomulti 37 is triggered by the rising edge of the output pulse No of the AND gate 31 in the noise gate 7 shown in FIG.
A signal MO with a period equal to is generated. If the "L" period of this signal MO is Tb, (T, +Tb) is the period of this signal MO, and therefore the period of pulse No. It goes without saying that pulse NO is equal to input pulse IN.

On the other hand, in FIG. 4, in the switching pulse generation circuit 6,
The AND gate 36 is controlled by the output signal 33Q of the DFF 33 and controls the switch 20 of the phase comparator 3 by passing the output signal No of the noise gate 7 in the PLL operation mode. Instead, switch 39 is controlled by output signal 33Q of DFF 33 to pass pulse 24E output from divider@2 (FIG. 4) during the PLL operating mode. The pulse 24E that has passed through the AND gate 39 is used as the sampling pulse SP, which is the output signal MO of the monomulti 37.
is supplied to the switch 38.

Here, in the PLL operation mode, as is clear from the previous explanation, the rising edge of the pulse NO supplied to the monomulti 37 is within the pulse period of the pulse 24E, and therefore the sampling pulse SP, so the output of the monomulti 37 is The rising edge of signal MO also lies within the pulse period of sampling pulse SP. Input pulse IN and frequency divided pulse CO
When the phase difference T, (FIG. 3(b)) is at a predetermined convergence value, the rising edge of the output signal MO of the monomulti 37 is at the center of the pulse period of the sampling pulse SP. Pulse width is 2Ta
Then, from the switch 38, the pulse T0 II HI
A pulse of I is output.

Now, the phase of the pulse MO when the rising edge coincides with the center point of the sampling pulse SP is defined as a reference phase O, and when the pulse MO is ahead of this reference phase O, the time difference between the sampling pulse SP and the pulse MO ( The following is simply pulse SP.

Pulse SP when the pulse MO is sent further than the reference phase 0, with the time difference between MOs being negative.

Let the time difference of the MO time be positive, and furthermore, the II of the pulse MO
When the T1 period of HPI is T, > 2 To, as the pulse MO advances from the reference phase O, the pulse width of the output pulse of the switch 38 increases sequentially from T, and the pulse SP
, M, and O becomes -T, the pulse width of the output pulse of the switch 38 becomes 2'I'0\. Also,
As pulse MO lags from reference phase 0, switch 3
The pulse width of the output pulse 8 is T. When the time difference between pulses SP and MO reaches +TO, switch 3
The pulse width of the output pulse No. 8 is O.

The output pulse of this switch 38 is supplied to the LPF 5, and since the pulse width of this output pulse changes as described above according to the time difference between the pulses SP and MO, the characteristics of the frequency control voltage VF output from the LPF 5 As shown in FIG. 14, -To to + of the time difference between pulses SP and MO
The characteristics become sloped in the range of T.

That is, this frequency control voltage v2 is a pulse SP.

The sampling pulses sp, t, and therefore the output pulse 24E of the frequency divider 2 (FIG. 4) have a predetermined phase relationship with the frequency-divided pulse Co, although they vary depending on the time difference between MOs.
The frequency control voltage Vr changes according to the phase difference between the frequency-divided pulse CO and the input pulse IN, thereby making it possible to control the oscillation frequency of the VCO1.

By the way, in the embodiment described above, each pulse such as the divided pulse CO output from the frequency divider 2 is
It is generated when the count value of the counter 23 (FIG. 4) within each reaches a specific value.

Therefore, the frequency of these pulses will differ depending on the oscillation frequency of the VCO1. Therefore.

In order to stabilize the phase difference Tφ between the input pulse IN and the frequency-divided pulse CO to a predetermined convergence value and bring them into a phase-synchronized state, it is necessary to make each output pulse of the frequency divider 2 have the same frequency as the input pulse IN. In addition, it is necessary to adjust the oscillation frequency of the VCO 1 in advance.

One way to initialize the oscillation frequency of this VCOl is to set the average frequency f of the input pulses used.

A standard signal source that generates a standard signal with a stable frequency equal to There is a method of adjusting the oscillation frequency of the VCOl so that In order to make such adjustment possible, it is necessary to take out the necessary pulses of the pulses formed by the frequency divider 2 to the outside and to make it possible to observe the phase relationship between these pulses and the manual pulse IN from the outside. desirable.

On the other hand, in order to downsize the device, it is desirable to integrate the frequency divider 2, noise gate 7, switching pulse generation circuit 6, etc., which are made up of logic circuits, into one digital LSI. case.

This digital LSI may be provided with terminals capable of outputting the pulse 24E in FIG. 4, the output pulse 25Q of the DFF 25, the reset pulse R8T, etc. to the outside.

Next, the procedure of the above method for initializing the oscillation frequency of the VCO1 will be explained in detail.

In FIG. 4, first, frequency divider 2, phase comparator 3, LP
The feedback loop of the PLL configuration consisting of F5 is opened, and a fixed voltage source is used to generate the charging voltage shown in Fig. 3 when the phase difference T# between the input pulse IN and the frequency-divided pulse co to be used is at a predetermined convergence value. A reference voltage at the level of Vc (this is referred to as V) is applied to VCOl as a frequency control voltage VF.

Here, the average frequency of the input pulse IN used is fo, and the oscillation frequency of the VCOl that should be taken when this human pulse IN and the divided pulse CO are phase-synchronized is nfo.
Then, the oscillation frequency of the VCOl to which the reference voltage is applied is II! Celebrate this, so that it becomes nf, VCO
Adjust 1.

A VCO is generally provided with a variable capacitance diode and an auxiliary capacitor as an oscillation capacitor, and by changing the capacitance of the auxiliary capacitor, the oscillation frequency of the VCO can be adjusted.

When the above adjustment is completed, the feedback loop is closed, the standard signal is supplied from the standard signal source as the input pulse IN, and the phase difference T between this and the frequency-divided pulse CO is observed. When this phase difference T deviates from the predetermined convergence value, the capacitance of the auxiliary capacitor of the VCO 1 is finely adjusted again. This absorbs the characteristic errors of the phase comparator 3 and LPF 56. By the way, in the above initial setting of VCO 1, in addition to using the standard signal source, you can open and close the feedback loop of the PLL configuration, and install a fixed voltage source. This requires work such as , removal, etc., making the procedure complicated. An embodiment of the synchronization pulse generator according to the present invention, which makes it possible to initialize the vcoi without such a complicated procedure, will be described with reference to FIG. In the same figure, 40 is a changeover switch, and parts corresponding to those in FIG. 2 are given the same reference numerals and redundant explanations will be omitted.

When initializing the VCOl, first close the switch 40 to the
Let F be the sampling pulse of the phase comparator 3. This pulse 24F is generated such that when the phase difference T between the input pulse IN and the frequency-divided pulse CO is at a predetermined convergence value, the phase difference between the input pulse IN and the frequency-divided pulse CO becomes approximately the predetermined convergence value. However, as is clear from FIG. 5, this pulse 24F includes the pulse 24B output from the decoder 24 (FIG. 4) and the output pulse 25Q of the DFF 25 (FIG. 5).
may also be used, or may be generated separately by the decoder 24.

Even if the oscillation frequency of VCOl deviates from nfo, the phase difference between the input pulse IN and the divided pulse CO is determined by the sampling time point of pulse 24F at the slope part of voltage Vc shown in FIG. 3 in the phase comparator 3. The voltage V when T is at the predetermined convergence value. When the phase difference between the divided pulse CO and the pulse 24F is set to be equal to the sampling time by the input pulse IN at the slope of V
The oscillation frequency of COL is stabilized. Therefore, the oscillation frequency of the VCOl is observed, and the oscillation frequency of the VCOl is adjusted as described above so that the oscillation frequency of the VCOL is stabilized at nf.

In this way, the oscillation frequency of the VCOl can be adjusted without using a fixed voltage source, and once this adjustment is completed,
The switch 40 is switched to the Y side to make the output signal SP of the switching pulse generation circuit 6 the sampling pulse of the phase comparator 3, and the standard signal from the standard signal source is supplied from the input terminal 1 as the input pulse IN, as described above. Then, finely adjust the oscillation frequency of the VCOL by nf.

In this embodiment, the voltage VC generated by the phase comparator 3 may have the waveform shown by the solid line in FIG. 3(a), but may also have the waveform shown by the broken line.

In addition, specific examples of Figures 2, 4, and 12 and Figure 15 are also provided.
In the illustrated embodiment, the switch 20 of the phase comparator 3 is also used as the switch 4, which is turned on only in the PLL operation mode of FIG. 1, but as shown in FIG. When a switch 4 is provided in the switch 4, the switch 4 may be controlled by the output pulse 33Q of the DFF 33 in FIG. 4, and the switch 20 of the 1-phase comparator 3 may be controlled by the output pulse NO of the noise gate 7. Alternatively, the output signal 33Q of this DFF33
The switch 4 may be controlled by the output pulse 24E of the frequency divider 2 when 41 H11, and the switch 20 may be controlled by the input pulse IN.

FIG. 16 is a block diagram showing still another embodiment of the synchronous pulse generator according to the present invention, in which 41 is an input terminal;
42 is a sync separation circuit, 43 is a horizontal sync signal separation circuit, 4
4 is a switching pulse generation circuit, 45 is a vertical synchronizing signal separation circuit, 46, 47 is a mono-multi, and 48 is a NOR circuit. Portions corresponding to those in FIG. 1 are given the same reference numerals and redundant explanations will be omitted.

This embodiment is particularly suitable for generating pulses that are phase synchronized with the horizontal synchronization signal of a video signal reproduced from a VTR.
The operation will be explained using diagrams.

A reproduced video signal of a VTR is supplied from an input terminal 41, and a synchronization signal SY is separated by a synchronization separation circuit 42. This synchronizing signal SY is, on the one hand, supplied to the horizontal synchronizing signal separation circuit 43 to separate the horizontal synchronizing signal and supplied as an input pulse IN to the phase comparator 3 and the switch 8, and on the other hand,
It is supplied to the switching pulse generation circuit 44. The horizontal synchronizing signal separation circuit 43 also has the function of removing noise pulses, as will be described later, and also serves as the noise gate 7 in FIG. 1.

In the switching pulse generation circuit 44, a vertical synchronization signal separation circuit 45 separates the vertical synchronization signal vS from the synchronization signal SY. The monomulti 46 is triggered by the falling edge (trailing edge) of the vertical synchronizing signal ■S, and outputs a signal 46ζ for a predetermined period 11 L II from the falling edge of the vertical synchronizing signal vS to its ζ terminal. In addition, the monomulti 47 is also triggered by the falling edge of the vertical synchronization signal vS, and its ζ
A signal 47Q that remains "H" for a predetermined period from the falling edge of the vertical synchronizing signal vS is output to the terminal.

In a VTR, a phase jump occurs in the horizontal synchronization signal reproduced by head switching, but this head switching is specified to occur at point a when a certain amount of time has elapsed from the vertical synchronization signal. , when the average period of the reproduced horizontal synchronization signal is TH, in FIG. Assume that a jump has occurred.

In this way, in the input pulse IN which is the reproduced horizontal synchronizing signal, a phase jump occurs due to head switching at a certain point in time with respect to the vertical synchronizing signal vS.
The time point at which the phase jump occurs can be estimated from

The switching pulse generation circuit 44 performs this estimation, and based on this estimation, sets the frequency divider reset mode to draw into the PLL operation mode.

For this reason, the output signal 46Q of the monomulti 46 is
31 period is the region where the next phase jump occurs from the falling edge of the vertical synchronization signal vS (region d in FIG. 17).
, and the equalization pulse period immediately after the falling edge of the direct synchronization signal vS is at least one period T of the horizontal synchronization signal. up to the point in time. In this embodiment, the output signal 46iQ of the monomulti 46
so that it is in the phase synchronization operation execution mode during the period P'''.

Also, the phase synchronization operation prohibition mode is set during the it H11 period. In addition, in phase synchronization operation execution mode,
The It HI+ period of the output signal 47Q of the monomulti 47 is set to the frequency divider reset mode, and its uL” period P
Set it to LL operation mode.

According to this, the period from the trailing edge of the single-ply serial synchronization signal vS to just before the next phase jump becomes the phase synchronization operation execution mode, and the other region becomes the phase synchronization operation prohibition mode. Also,
In the phase synchronization operation execution mode, a region slightly past the end of the equalization pulse period from the trailing edge of the vertical synchronization signal vS becomes the frequency divider reset mode, and the other region becomes the PLL operation mode.

The switch 8 is set so that the output signal 47Q of the monomulti 47 is tiH.
Therefore, the switch 8 is turned on only in the frequency divider reset mode, and the frequency divider 2 is reset by the input pulse IN.

In addition, the output signal 460 of the mono multi 46 and the mono multi 4
7 output signal 47Q is supplied to the NOR circuit 48, and the PLL
The switch signal SW becomes “H11” only in the operation mode.
is generated. Switch 4 is “H” of switch signal SW
The switch 4 is turned on only during the PLL operation mode, so that the PLL operation is performed.

Note that in the 1-phase synchronization operation prohibition mode, the switch 4.8 is held in the off state.

As described above, in this embodiment, a phase jump occurs in the input pulse IN immediately before the vertical synchronizing signal vS, but within the equalization pulse period that does not appear on the screen immediately after the vertical synchronizing signal vS, the frequency divider is reset by the input pulse IN, and the phase of the frequency-divided pulse CO from the frequency divider 2 is pulled into the input pulse IN.

Figure 18 shows the horizontal synchronizing signal separation circuit 43 in Figure 16.
It is a block diagram showing a specific example of 49.50 is a monomulti, and 51 is a Nantes gate.

In the same figure, in the monomulti 49, the synchronization separation circuit 42
ItH is triggered by the falling edge (leading edge) of the synchronizing signal SY from (Fig. 16), and some pulses @ (approximately the pulse width of the horizontal synchronizing signal) whose phase coincides with this falling edge.
A pulse 49Q of ``'' is formed. The monomulti 50 is triggered by the falling edge (trailing edge) of this pulse 49Q, and now changes the average period of the horizontal synchronization signal to TI4, as shown in FIG. 19(a). The pulse width of this horizontal synchronization signal is T.

Then, from the falling edge of pulse 49Q ('rtt
-Ta) A signal 50ζ having a slightly shorter period II L If is output from the ζ terminal. Therefore, this signal 50ζ includes a pulse 49Q when the average period is TH, and has a pulse width of "H" slightly longer than this pulse period.
This is the pulse of

Pulses 49Q, 500 are supplied to the Nant gate 51,
Pulse 49Q existing within the pulse period of pulse 50iQ
is level-inverted and output. This is the input pulse IN
This is the horizontal synchronization signal.

Next, each area a in FIG. 17 of this specific example.

b. , d will be explained with reference to FIG.

FIG. 19(a) shows the operation in area a of FIG. 17. In this case, when the period of the synchronization signal SY is close to the average period T, the pulse 49Q is included within the pulse period of the pulse 50Q, and these pulses 49Q are inverted and the Nant gate 51
is output from. Also.

Due to the phase jump, the period of the synchronization signal SY becomes the average period T.
Even if the pulse width is longer than 8, the pulse width of the pulse 50'cl is expanded to include the pulse 4.9Q, and the pulse 49Q is inverted and output from the Nant gate 51.

In the region of FIG. 17 that includes the equalization pulse, the region of FIG. 19 (b
), since the period of the equalization pulse is as short as T/2, the pulse 4.9Q generated from every other equalization pulse is included in this pulse period, and therefore , these pulses 49Q are inverted and output from the Nant gate 51.

This is a horizontal synchronization signal with an average period of TH, and the equalization pulse is removed.

Note that if the equalization pulse indicated by 1, which should be detected as a horizontal synchronization signal, is lost due to dropout or the like, the pulse width of pulse 500 at the time of this equalization pulse will change to the following value indicated by i, as shown by the broken line. This is extended to the equalization pulse, which passes through the Nant gate 51, and from then on, every other equalization pulse is detected as a horizontal synchronization signal. For this reason, the phase of the input pulse IN output from the Nant gate 51 is shifted by TH/2 until the equalization pulse ends. If the frequency divider 2 is reset by this input pulse IN and shifts to the PLL operation mode, the switch 8 will remain off and the frequency divider 2 will not be reset, so what is the phase difference between the input pulse IN and the divided pulse C? The PLL operation is started when T is T8/2.

To prevent this, as previously explained and shown in Figure 17, the 1 divider reset mode is extended to a period slightly past the equalization pulse period, and this mode is applied to the horizontal At least one synchronization signal is included. As a result, the frequency divider 2 is always reset by the horizontal synchronizing signal after the equalization pulse period has elapsed, and in the PLL operation mode, the phase difference T# between the input pulse IN and the divided pulse CO is close to a predetermined convergence value from the beginning. will be set to .

In region C of FIG. 17 within the vertical synchronization signal period, as shown in FIG. 19(c), it is similar to the equalization pulse period shown in FIG. 19(b), and the horizontal synchronization signal 5
1 is extracted.

In region d of FIG. 17, where the period T' of the horizontal synchronizing signal is shorter than the average period TH due to head switching, this causes the monomulti 4
The output pulse 490 of 9 is the output pulse ζ of monomulti 50
If it deviates from the current, this pulse 49Q is blocked by the Nant gate 51 and the input pulse IN is lost. However, from the next horizontal synchronization signal, pulse 49Q is within the pulse period of pulse 50Q, and input pulse IN is again obtained from Nant gate 51.

In this way, even if there is a phase jump in the reproduced synchronization signal SY and the input pulse IN is missing, this is during the phase synchronization operation prohibition mode and both switches 4 and 8 are off, so there is no particular problem. It won't happen.

Furthermore, as is clear from the operation during the equalization pulse periods shown in FIGS. It is not triggered by the output pulse of the multi 49, so this noise pulse is filtered out by the Nandt gate 51.

FIG. 20 is a block diagram showing still another embodiment of the synchronous pulse generator according to the present invention, in which 52 is an inverter, 53 is a DFF, and 54 is an AND gate;
Components corresponding to FIGS. 4 and 16 are given the same reference numerals and redundant explanations will be omitted.

This embodiment combines the embodiment shown in FIG. 1 and the embodiment shown in FIG. 16 to generate pulses that are phase-synchronized with the reproduced horizontal synchronizing signal of a VTR. The operation of this embodiment will be described below with reference to FIG. 21 showing signal waveforms at each part.

In FIGS. 20 and 21, as explained in FIG. 16, when a reproduced video signal of a VTR is input from the input terminal 41, a horizontal synchronization signal is outputted from the horizontal synchronization signal separation circuit 43 as an input pulse IN. , are supplied to the noise gate 7. When there is a phase jump in the input pulse IN due to head switching of the VTR, a pulse 32R is output from the AND gate 32 for each input pulse IN that has undergone a phase jump due to the action of the noise gate 7 and the switching pulse generation circuit 6.

In addition, in the switching pulse generation circuit 44, the Nant gate 48
As shown in FIG. 17, It H
A signal SW of '1' is output.

This signal SW is supplied to the DFF 53 as a reset signal, and is inverted by the inverter 52 and supplied as a data input. Further, the DFF 53 is supplied with a pulse 32R output from the AND gate 32 as a clock.

The output signal 53ζ obtained at the ζ terminal of the DFF 53 becomes a switching control signal for the switch 4. Further, the output pulse 32R of the AND gate 32 and the output signal SW of the switching pulse generation circuit 44 are supplied to an AND gate 54, and the pulse 32R that has passed through the AND gate 54 becomes an external reset pulse for the frequency divider 2.

Therefore, the output signal SW of the switching pulse generation circuit 44 is "
During this period, the AND gate 54 is in an off state and the 5 frequency divider 2 is in a reset prohibited state.

On the other hand, after this signal SW becomes "L", there is a phase jump in the input pulse IN due to head switching, but during the "L" period of the output signal SW of the switching pulse generation circuit 44, the AND gate 54 is in the off state. Since the frequency divider 2 is prohibited from being reset, even if the AND gate 32 outputs the pulse 32R due to the phase jump of the input pulse IN, the frequency divider 2 is not reset. For this reason, the signal SW is 11 L l after head switching.
During the period #, the input pulse IN is in a phase jump state shifted from the pulse period of the pulse 24E from the frequency divider 2, and the AND gate 32 continues to output the pulse 32R for each input pulse IN.

In addition, the output signal SW of the switching pulse generation circuit 44 is “L”
During this period, the DFF 53 is released from reset, its data input is “H”, and the AND gate 3
When the pulse 32R is output from the DFF 53, the DFF 53 takes in the "H" data input and outputs the output signal 53? :5 becomes 11 L 71. As a result, the switch 4 is turned off. That is, during the "L" period of the output signal SW of the switching pulse generation circuit 44 after there is a phase jump in the input pulse IN due to head switching, the switch 4 is held in the off state and the phase comparator 3 and the LPF 5 are disconnected. The VCOl is controlled by the frequency control voltage V at the level maintained by the LPF5. In this way, "L#" of the output signal SW of the switching pulse generation circuit 44
In the period, there is a phase jump in the input pulse IN due to head switching, and then the feedback loop of the PLL configuration is interrupted and VCOl is generated at a nearly constant frequency.
In addition, since the frequency divider 2 is prohibited from being reset, the input pulse IN is maintained in a phase jump state with respect to the frequency division pulse CO, and the pulse 32R continues to be output from the AND gate 32.

At the end of the equalization pulse period, the output signal SW of the switching pulse generation circuit 44! When it becomes R'', the DFF 53 enters a reset state, and its output signal 53ζ becomes II HII, and the switch 4 is turned on to form a PLL configuration.

The first pulse 32R output from the AND gate 32 after the signal SW becomes "HII" passes through the AND gate 54 and resets the frequency divider 2 as an external reset pulse 54R. Peripheral pulse C
O is in phase synchronization with the switching pulse generation circuit 6.
The output signal 34Q becomes "L" and the AND gate 32 is turned off.

Further, for each input pulse IN supplied thereafter, a sampling pulse SP is sent from the switching pulse generation circuit 6 to the phase comparator 3.
is supplied.

In the embodiment shown in FIG. 16, the timing at which the switch 4 starts to turn off is set to
8 and must be set before the head switching timing. However, if this rise timing is made too early, the feedback loop of the PLL configuration will be interrupted in the portion that appears on the screen. For this reason, the phase synchronization between the input pulse IN and the frequency-divided pulse CO may not be achieved, and there is a possibility that disturbances such as image distortion may occur at the lower part of the screen.

For this purpose, the signal SW output from the Nant gate 48
The rising timing of the signal must be as close as possible to the head switching timing before the head switching timing, and it is necessary to make the characteristic accuracy of the monomulti 46 relatively strict for setting this timing.

On the other hand, in the embodiment shown in FIG. 20, it is controlled by the output signal 53ζ of the DFF 53, which falls due to the phase jump caused by Herad switching, and the switch 4 starts to turn off at this falling edge. It is turned off from the time of switching, and PLL operation is performed over the entire portion appearing on the screen.

Therefore, the falling edge of the output signal SW of the switching pulse generation circuit 44, that is, the output signal 46 of the monomulti 46
This rising edge simply needs to occur before the head switching point, and the characteristics of the monomulti 46 can be given some leeway.

[Effects of the Invention] As explained above, according to the present invention, by using a vCO with high frequency stability, it is possible to perform high-speed phase pull-in in response to phase jumps of input pulses, and to prevent missing or mixed input pulses. Malfunctions due to noise pulses and performance deterioration due to changes over time can be prevented.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the synchronous pulse generator according to the present invention, FIG. 2 is a circuit diagram showing a specific example of the phase comparator and low-pass filter shown in FIG. 4 is a diagram showing a specific example of the frequency divider, switching pulse generation circuit, noise gate, and switch in FIG. 1. FIG. 5 is a diagram showing the operation of the frequency divider in FIG. 4. 6 is a diagram showing the operation of the noise gate in FIG. 4, FIG. 7 is a diagram showing the operation of the switching pulse generation circuit in FIG. 4, and FIG. 8 is a diagram showing the operation of the switching pulse generation circuit in FIG. 4. An explanatory diagram of the operation at startup, FIG. 9 is an explanatory diagram of the operation in response to missing input pulses and noise pulses, and FIG. 10 is an explanatory diagram of the operation when the input pulse has a phase jump.
FIG. 11 is an explanatory diagram of the operation when the reset pulse of the frequency divider is a wide pulse, FIG. 12 is a block diagram showing another specific example of the phase comparator in FIG. 1, and FIG. 13 is the diagram shown in FIG. 14 is an explanatory diagram of the operation of the phase comparator shown in FIG.
16 and 16 are block diagrams showing other embodiments of the synchronous pulse generator according to the present invention, and FIG.
FIG. 18 is a block diagram showing a concrete example of the horizontal synchronizing signal separation circuit in FIG. 16, FIG. 19 is a diagram explaining the operation of this concrete example, and FIG. FIG. 21 is a block diagram showing still another embodiment of the synchronizing pulse generator according to the invention, FIG. 21 is an explanatory diagram of the operation of this embodiment, and FIG. 22 is an explanatory diagram of the operation of the conventional synchronizing pulse generator. 1... Voltage controlled oscillator, 2... Frequency divider, 3... Phase comparator, 4... Switch, 5... Low pass Filter, 6...Switching pulse generation circuit, 7...Noise gate, 8.
...Switch, 9...Input terminal, 10.
...Output terminal, 23...Counter, 24
...Decoder, 40...Selector switch, 41...Video signal input terminal, 42...
- Synchronization separation circuit, 43...Horizontal synchronization signal separation circuit, 44...Switching pulse generation circuit, 45...
...Vertical synchronization signal separation circuit. Figure 4 Figure 3 (O) Figure 5 Figure 6 Figure 7 (O) (b) 32/? ]]1--Figure 9 P Mi v: +sg foot W3? Taa ~ ~ ~ ~ ~ ~ 1 nth figure 1O figure P figure 11 figure 12 figure N. Fig. 76 Fig. 13 - 42Tol- Fig. 14 Fig. 15 Fig. 17 Fig. 18 Fig. 19 B! 1 1~ Engineering---"-m-l- NF" N m-"--1F (d) 490 几-JL-Gohi 50Q1--]-11 SIIN ■-1111] F $20 figure

Claims (1)

[Claims] 1. A voltage controlled oscillator, a frequency divider that divides the output pulse of the voltage controlled oscillator, and a phase comparator that compares the phase of the divided pulse output by the frequency divider and the input pulse. and a low-pass filter to which the phase difference voltage detected by the phase comparator is supplied, and the output voltage of the low-pass filter is used as the frequency control voltage of the voltage-controlled oscillator. a first means for performing an operation of resetting the frequency divider; a second means for performing an operation of cutting off the supply of the phase difference voltage to the low-pass filter prior to the operation of the first means; and a third means for switching between an operating state and a non-operating state of the first and second means, and interrupting the phase difference voltage and operating the voltage controlled oscillator with the frequency control voltage held in the low-pass filter. A synchronous pulse generator characterized in that it is configured to cause oscillation and then reset the frequency divider. 2. In claim 1, the first means includes means for extracting the input pulse and using it as a reset pulse for the frequency divider together with the setting of the operating state by the third means. Pulse generator. 3. In claim 1, the third means includes means for determining whether or not the input pulse is present within a first period having a predetermined time relationship with the frequency-divided pulse; and means for setting the first and second means to the operating state when the period is outside the first period. 4. In claim 3, means for determining whether or not the input pulse is present within a second period including the first period;
means for setting a pulse extraction period according to a determination result of the means, extracting the input pulse and supplying it to the first and third means; The extraction period is set to a period up to the time when the input pulse is supplied within the second period, and when the input pulse is outside the second period, the pulse extraction period is set for a predetermined number of cycles of the frequency-divided pulse. and means for setting the pulse extraction period to be equal to the second period and then setting the pulse extraction period to a period from the start of the second period to the time when the input pulse is supplied. Device. 5. A voltage controlled oscillator, a frequency divider that divides the output pulse of the voltage controlled oscillator, a phase comparator that compares the phase of the divided pulse output by the frequency divider and the input pulse, and the phase comparator. and a low-pass filter to which a phase difference voltage detected by is supplied, the output voltage of the low-pass filter is used as the frequency control voltage of the voltage controlled oscillator, and the frequency-divided pulse is applied to the input pulse that causes a phase jump at a predetermined period. In a synchronizing pulse generator, the period of the phase jump is a unit of a first period including the phase jump of the input pulse, a second period following the first period, and the remaining third period. a second means controlled by the first means to cut off the supply of the phase difference voltage to the low-pass filter during the first and second periods; third means controlled by the first means to extract the input pulse during the second period and use it as a reset pulse for the frequency divider; oscillates the voltage controlled oscillator with the frequency control voltage held at A synchronous pulse generator characterized in that it is synchronized. 6. In claim 5, the input pulse is a reproducing horizontal synchronizing signal of a magnetic recording/reproducing device whose phase jumps occur due to head switching, and the first means is a reproducing vertical synchronizing signal of the magnetic recording/reproducing device. The trailing edge coincides with the first
means for generating a first signal having a time width equal to the period of;
means for generating a second signal whose leading edge coincides with the trailing edge of the reproduced vertical synchronization signal and which is equal to the second period;
means for generating a third signal having a period equal to the sum of the periods of the signals, the third signal controlling the second means, and the second signal controlling the third means. A synchronous pulse generator characterized by: 7. The synchronization pulse according to claim 6, wherein the second signal is set to have a time width including at least one horizontal synchronization signal after the equalization pulse period in the reproduction synchronization signal of the magnetic recording and reproducing device. Generator. 8. A voltage controlled oscillator, a frequency divider that divides the output pulse of the voltage controlled oscillator, a phase comparator that compares the phase of the divided pulse output by the frequency divider and the input pulse, and the phase comparator. and a low-pass filter to which a phase difference voltage detected is supplied, and the output voltage of the low-pass filter is used as the frequency control voltage of the voltage-controlled oscillator, and the horizontal In a synchronizing pulse generator that uses a synchronizing signal as the input pulse and synchronizes the phase of the frequency-divided pulse with the input pulse, the input pulse is output when the input pulse is outside a set period that has a predetermined time relationship with the frequency-divided pulse. a first means for extracting and outputting a first signal; a second means for generating a first signal including at least a time point at which the phase jump occurs and an equalization pulse period of a reproduction synchronization signal of the magnetic recording and reproducing apparatus; third means for extracting the output pulse of the first means after the signal period of the first signal and using it as a reset pulse of the frequency divider; a fourth means for generating a second signal having a time width up to the trailing edge; and a fifth means for cutting off the supply of the phase difference voltage of the phase comparator to the low-pass filter during the signal period of the second signal. means for interrupting the phase difference voltage during the signal period of the second signal, causing the voltage controlled oscillator to oscillate with the frequency control voltage held in the low-pass filter, and controlling the signal period of the first signal to elapse. resetting the frequency divider by at least a first output pulse of the first means afterward, and adjusting the phase of the divided pulse to the phase of the input pulse such that the input pulse falls within the set period; A synchronous pulse generator characterized by being retractable.