JPH0132589B2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a control circuit for a disc motor in a disc playback device such as a video disc or a compact disc, and a method for detecting a stable state of disc rotation and switching the control mode. This is what I did.

[Conventional technology]

Rotation control of the disk motor in a disk playback device is generally controlled by AFC (Auto Frequency).
control) and PLL (Phase locked loop) control.

AFC control is an FG directly connected to the disk motor.
(Frequency Generator: A device that generates pulses at a period proportional to the rotation speed) This is a coarse control that controls the rotation of the disk motor by comparing the frequency of the pulses generated by the device with a reference clock, and can be controlled even when no reproduction is made from the disk. It is.

PLL control is a relatively highly accurate control that controls the rotation of a disk motor by comparing the phase of a synchronization signal (for example, a horizontal synchronization signal) extracted from a disk reproduction signal with a reference clock.

AFC
When the control is executed and the disk rotation speed approaches the specified speed, the synchronization signal can be extracted from the disk playback signal and pulled into PLL control.
I am trying to switch to PLL control.

However, the range that can be retracted into PLL control is
There is a certain degree of spread relative to the target speed,
Just because the disc motor is engaged in PLL control, it does not necessarily mean that the disk motor will rotate stably at the target speed immediately.

Furthermore, even after stable rotation at the target speed is achieved using PLL control, due to some reason (such as an impact or scratches on the disk surface), the PLL control may become out of lock and the disk rotation may become unstable. be. Therefore, simply because the PLL control is engaged, it is immediately determined that the rotation is in a stable rotation state, and control that should be executed only in a stable rotation state (for example, jitter removal control or horizontal synchronization signal extraction window for PLL control) is determined. (switching control, etc.), accurate control cannot be expected.

[Problem that the invention seeks to solve]

The present invention aims to solve the problems in the conventional technology and provide a disk motor control device that is capable of detecting a stable state of disk rotation in a PLL control mode and executing various controls. be.

[Means for solving problems]

The present invention includes a first control circuit that controls the rotation of the disk motor by comparing a rotation detection signal of the disk motor with a reference clock, and a first control circuit that controls the rotation of the disk motor by comparing a synchronization signal in a disk reproduction signal with the reference clock. A second control circuit, a circuit that applies a window to the timing of the next expected synchronization signal based on the synchronization signal in the disc playback signal, and a circuit that detects the synchronization signal entering the window are provided. If the window is wide, the first control circuit performs control, and at that time, the window is set wide to detect a synchronization signal, and if the synchronization signal is often obtained within this wide window, the second control circuit is performed. Switching to control by the circuit, in the control by this second control circuit, the window is set narrow to detect synchronization signals, and when the synchronization signals often enter this narrow window, it is determined that the state is stable, and the state is stable. In this stable state, the window is set a little wider than the narrow window to detect synchronization signals, and when the number of synchronization signals entering this window decreases, it is determined that the state is unstable. The control that should be performed in the stable state is stopped based on this judgment.

[Effect]

According to this invention, in the control by the second control circuit (PLL control), after confirming that the disk rotation is in a stable state, the control that should be performed in the stable state is executed, so that the reliability of these controls is guaranteed. After confirming the stable state in PLL control, the window is widened a little to detect the disk rotation state, which prevents the control that should be performed in the stable state from being stopped unnecessarily. .

〔Example〕

An embodiment of this invention is shown in FIG.

In FIG. 1, a video disk 10 is rotationally driven by a disk motor 12. As shown in FIG. An FG (Frequency Generator) 14 is directly connected to the disk motor 12, and the FG 14 outputs pulses at a period proportional to its rotational speed.

The recorded information on the disk 10 detected by the head 16 consists of a pulse frequency modulated signal,
The signal is input to the FM detection circuit 20 via the amplifier 18, where it is FM detected and a composite video signal is output.

In addition, the output of the HF amplifier 18 is separately connected to TBC.
(Time Base Correct) is input to the circuit 21.
The TBC circuit 21 removes jitter (fluctuation in the time axis direction) contained in the disc playback signal, and is a continuously variable delay circuit (for example,
160784). The TBC control circuit 23 continuously variably controls the delay time of the TBC circuit 21, and is generated at the regular horizontal synchronization signal period based on the horizontal synchronization signal present in the output of the TBC circuit 21 and the crystal oscillation output. Compare the phase with the clock φh and adjust TBC according to the phase difference.
By controlling the delay time of the circuit 21,
A signal from which jitter has been removed is output from the TBC circuit 21.

Furthermore, the composite video signal obtained from the FM detection circuit 20 is processed into a synchronous component signal by a synchronous separation circuit 22.
CSYNC is separated.

The edge detection circuit 24 uses a synchronous component signal CSYNC.
It detects falling edges of the synchronization component signal CSYNC, excluding falling edges that are clearly determined to be caused by noise, and outputs a synchronization detection signal SYNDW.
Note that noise removal here is achieved by ensuring that the width of the "L" level after the fall is sufficient, and that the "H" level always rises within a predetermined period of time before the fall. ``This is done by detecting only falling edges that are in a level state.

Synchronization detection signal obtained in this way
SYNDW includes not only the horizontal synchronization signal HSYO, but also the horizontal synchronization signal HSYO.
To identify the vertical synchronization signal, an equalization pulse is included that is inserted at an intermediate position in the timing of the horizontal synchronization signal HSYO only during the vertical blanking period. Furthermore, unexpected noise components may still remain. Therefore, window setting circuit 2
8, the window WD is set at the timing when the horizontal synchronization signal HSYO is expected, and the AND circuit 26
The signal that comes within the window WD of the synchronization detection signal SYNDW is converted into the true horizontal synchronization signal.
Extract as HSYO. As a result, the equalization pulse and residual noise are removed from the window WD.

The width of the window WD is changed depending on the stable state of disk rotation, as will be described later.

The window control counter 30 measures the timing within one horizontal scanning period H (=regular generation interval of the horizontal synchronizing signal HSYO), is stepped by a clock based on the crystal oscillation output, and is incremented by 1 at the regular rotation speed.
It counts 455 during the horizontal scanning period H (count value is 0 to 454) and is cleared by the horizontal synchronizing signal HSYO.

The protection circuit 32 outputs the signal HSYI at the 454th count of the window control counter 30 as a substitute signal when the horizontal synchronization signal HSYO cannot be obtained within the window WD due to dropout or the like. If the alternative signal HSYI is used, the window control counter 30 is cleared by this alternative signal HSYI.

Note that the window WD has a spread around the 454th count of the window control counter 30, so at the timing of the 454th count, the horizontal synchronization signal is not activated during the window WD.
I don't know yet whether HSYO is included (it may be in the latter half of Wind WD after 454 counts). Therefore, the protection circuit 32 uses the horizontal synchronizing signal HSYO and its alternative signal.
Delay HSYI for a predetermined time and wait for the end of window WD to generate horizontal synchronization signal HSYO (horizontal synchronization signal HSYO).
(when horizontal synchronization signal HSYO is not obtained) or alternative signal HSYI (when horizontal synchronization signal HSYO is not obtained).

The switching circuit 34 switches the disk rotation control mode between the horizontal synchronizing signal HSYNC and the reference clock RFHSYNC.
This switches to PLL control based on phase comparison between the output pulse EXFG of the FG14 and AFC control based on frequency comparison between the output pulse EXFG of the FG14 and the reference clock IFG. The comparator 36 performs these phase comparisons or frequency comparisons to control the rotation of the disk motor 12.

The window register control circuit 40 looks at the count value of the window control counter 30 and outputs signals instructing the start and end timings of various windows. Here, in addition to the window WD for extracting the horizontal synchronization signal HSYO mentioned above, an intermediate window corresponding to the equalization pulse position is used.
It instructs the timing of H2WD and window WS to detect the stable state of disk rotation.

An example of the window is shown in FIG. Horizontal sync signal
The window WD for extracting HSYO includes a wide window WD1 and a narrow window WD2. Wide window WD1 has window control counter 30
The count value is set to a period from 318 to 592 (±30% of the expected timing of the horizontal synchronization signal HSYO, with the 1H period being 100%). Narrow window WD2 has a count value of 448 to 476 (-1.5%)
+4.8%). Intermediate window H2WD has a count value of 158 to 318 (same 65%)
-30%) period.

Window WS for detecting stable state of disk rotation is WS1, WS3, WS in order from widest to widest.
There are 2. Wind WS1 has a count value of 318
to 592 (±30% of the expected timing of the horizontal synchronization signal HSYO). Wind WS3
, the count value is from 448 to 476 (from -1.5% to +
4.8%) period. Wind WS2 is
The count value is set for the period from 448 to 461 (±1.5%).

The window register 38 has individual registers for each of the various windows, is set and reset at corresponding timings from the window register control circuit 40, and outputs a signal indicating the area of the window.

The mode control section 51 detects a stable state of disk rotation and switches the control mode.
Here, the control modes include AFC mode, PLL1 mode, and PLL2 mode. AFC mode is used in the most unstable state, and disk rotation control is executed by AFC control. PLL1
Although this mode is more stable than AFC mode, it is used when the final stable state has not yet been reached, and disk rotation control is executed by PLL control. PLL2 mode is used in the final stable state, and like PLL1 mode, disk rotation control is executed by PLL control. this
It is not until the PLL2 mode is reached that the TBC circuit 21 performs jitter removal control, the window setting circuit 28 performs window switching control, etc. Strict conditions are imposed on switching to a higher-order mode, but once the higher-order mode is entered, it is prevented from switching to a lower-order mode unnecessarily, thereby preventing frequent mode switching.

The stable state of the disk rotation is detected by using the disk rotation state detection window WS output from the window register 38, etc., using the horizontal synchronization signal.
Synchronization detection signal at the timing when HSYO is expected
This is done depending on whether SYNDW can be obtained.
In other words, there is a synchronization detection signal within the window WS.
If the number of times SYNDW is obtained is large, it is determined that the state is stable, and if it is small, it is determined that the state is unstable.
When driven by AFC control, check the synchronization detection signal SYNDW in a wide window WS1 (within ±30% of the expected timing of the horizontal synchronization signal HSYO), and if the number of times it enters the window WS1 increases, the PLL1 The control mode is switched to control. Narrow window WS2 under PLL1 control
(within a range of ±1.5%), and if the number of times that this window WS2 is entered increases, it is determined that a stable state has definitely been reached, and the mode is switched to PLL2 mode.

It is confirmed that the final stable state has been reached by entering the PLL2 mode, and the above-mentioned TBC circuit 21 performs jitter removal control and changes the window WD to extract the horizontal synchronization signal HSYO (wide window WD).
Switch from 1 to narrow window WD2. ) etc. are executed. By switching the window WD, noise in the synchronization detection signal SYNDW is reliably removed, and only the normal horizontal synchronization signal HSYO is extracted. Even after entering PLL2 mode, the rotation may become unstable for some reason, so check the horizontal synchronization signal HSYO in window WS3 and return to PLL1 mode if it often does not enter that window. There is. In this case, to prevent frequent mode switching, the window WS3 used in PLL2 mode is -1.5 to +4.8%.
Window WS2 used in PLL1 mode (±1.5%)
It's wider than that.

The configuration of the mode control section 51 will be explained.

The window selection circuit 64 selects a window WS for detecting a stable state of disk rotation.
Here, mode signals MD and LMT, which will be described later, are
According to the signal LMT from the counter 72, the windows WS are set as WS1, WS2, and WS3 (Fig. 2).
One of them is selected.

The up control circuit 62 outputs a synchronization detection signal.
Horizontal synchronization signal at normal speed of SYNDW
Pass what is within the window WS (hereinafter also referred to as window WSUP) at the timing of HSYO. The down control circuit 66 passes the synchronization detection signal SYNDW that is outside the window WS and outside the intermediate window H2WD (hereinafter collectively referred to as window WSDW).
Note that the reason for excluding those within the intermediate window H2WD is to prevent a down signal from being generated by the equalization pulse during normal rotation.

When the rotation is stable, the number of times the synchronization detection signal SYNDW appears within the window WSUP increases, and when the rotation is unstable, the number of times the synchronization detection signal SYNDW appears within the window WSDW increases.

In addition, when the signal does not appear in either window WSUP or WSDW for 1H, the down control circuit 66 determines that the rotation is unstable and generates one pulse every 1H specified by an internal reference counter. Output.

The mode control counter 58 is connected to the up control circuit 6.
2 (however, when double speed is detected, the AND circuit 60 is turned off as described later, so the up-count is not performed), and the output of the down control circuit 66 is used to down-count. Therefore, in the current mode, if the rotation becomes stable and the number of times the synchronization detection signal SYNDW enters the window WSUP increases,
The count value N of the mode control counter 58 increases, and if the rotation is still unstable and the number of times the synchronization detection signal SYNDW enters the window WSDW is large, the count value N of the mode control counter 58 decreases.

The mode control counter 58 goes from 0 to N2 via N1.
(N1 and N2 are limit values described later, for example, N1=
2048, N2=3072. ) count up/down. Once it reaches 0, it will not fall below 0 even if a down pulse is input. Furthermore, once it reaches N2, it will not rise above N2 even if an up pulse is input.

The mode control counter 58 is used to switch control modes, and when it counts up, it is determined that the rotation is heading towards stable rotation.
After confirming that a predetermined limit value has been reached, the control mode is switched to a higher level control mode. Furthermore, if the count is down, it is determined that the control mode is unstable, so it is confirmed that a predetermined limit value has been reached, and the control mode is switched to a lower control mode.

The count value determination circuit 68 detects, as a condition for switching the rotation control mode, that the count value of the mode control counter 58 has reached the limit value N1 or N2.

The mode determination counter 74 instructs the control mode, and the count value itself indicates the control mode. That is, the mode control counter 74 is counted up/down from 0 to 2 by the mode control circuit 70, a count value of 0 commands the AFC mode, a count value of 1 commands the PLL1 mode,
Command PLL2 mode with count value 2. The mode signal MD is input to the switching circuit 34, and when the count value is 0, the rotation control switching circuit 34 is switched to the AFC side, and when the count value is 1 or 2, the switching circuit 34 is switched to the PLL side.

The LMT counter 72 is the mode control counter 5
This counter indicates which of the limit values N1 and N2 is selected as the target value of 8. If the count value N of the mode control counter 58 is smaller than N1,
The LMT counter 72 is set to 1 (N1 selected), and if the count value N is greater than N1, the LMT counter 72 is set to 1 (N1 selected).
2 is set to 2 (N2 selection).

The mode control circuit 70 controls the current mode MD,
The mode determination counter 74 and the LMT counter 72 are incremented/decreased based on the count value of the LMT counter 72 and the count value of the mode control counter 58, thereby switching the mode.

The state of each mode is shown in FIG.

In AFC mode (MD=0), LMT counter 7
When 2 is 1 (N1 selection), the disk rotation state detection window WS is ±30%;
HSYO's extraction window WD is controlled to ±30% and TBC is turned off. This is the initial state.

In PLL1 mode (MD=1), LMT counter 7
When 2 is 1 (N1 selection), the disk rotation state detection window WS is ±30%;
HSYO extraction window WD is controlled to ±30%,
TBC is turned off.

LMT counter 72 in PLL mode (MD=1)
is 2 (N2 selection), the disk rotation state detection window WS is ±1.5%, and at this time HSYO
Extraction window WD is controlled to ±30%, TBC
is turned off.

In PLL2 mode (MD=2), LMT counter 7
When 2 is 2 (N2 selection), the WS for disc rotation state detection is -1.5% to +4.8%;
The HSYO extraction window WD is controlled between -1.5% and +4.8%, and TBC is turned on. This is the final stable state.

Note that due to circuit malfunction, etc., combinations of modes and LMT counter 72 not shown in Fig. 3 (for example, AFC
A combination in which the LMT counter 72 becomes 2 in the mode,
Or LMT counter 72 is 1 in PLL2 mode.
) occurs, the mode control circuit 70 clears the mode determination counter 74 and sets the LMT
When the counter 72 is set to 1, the initial state is AFC.
Return to mode.

Next, the conditions for switching the limit values N1 and N2 are shown in FIG. The LMT counter 72 which selects the limit value is based on its own pre-switching state and the mode control counter 58.
It is switched by the value N of . That is, when the limit value before switching is N1 (LMT counter 72 is 1), when the count value N increases and reaches N=N1, it is switched to N2 (LMT counter 72 is 2).
Also, the limit value before switching is N2 (LMT counter 72
When is 2), the count value N decreases and N=
When it reaches N1, it switches to N1 (LMT counter 72 is 1).

Next, conditions for control mode switching are shown in FIG.
The control mode is switched depending on the control mode before switching and the count value of the mode control counter 58. That is, when the control mode before switching is AFC, the mode is switched to PLL1 mode when the count value N reaches the limit value N1. once the control mode is
Once switched to the PLL1 mode, the PLL1 mode is maintained even if the count value N falls below the limit value N1 unless the switching conditions for the next PLL2 mode are satisfied.

When the control mode before switching is PLL1, the control mode is switched to PLL2 mode when the count value N reaches the limit value N2. When the control mode before switching is PLL2, when the count value N reaches the limit value N1, the mode is switched to PLL1 mode. When the control mode before switching is PLL1, when the count value N reaches 0, the mode is switched to AFC mode.

FIG. 6 generally shows the transition state of the control mode under the above switching conditions. This is an operation when a normal reproduction command is given, and the operation is performed sequentially (that is, there is no jumping over) so as to transition from the initial state A on the left side to the final stable state D on the right side as the target.

Initial state A is AFC mode, and at this time, the rotational state is observed with a wide window WS = ±30%.
When the count value N1 is reached in the initial state A, the mode is switched to the PLL1 mode of the intermediate state B, and the window WS is also narrowed to ±1.5%. When the disk rotation control switches from AFC control to PLL control, the count value N may temporarily fall below N1.
At this time, as intermediate state C, the rotation state is observed with the window WS expanded to ±30% even in the same PLL1 mode. When it moves in the stable direction again in intermediate state C and reaches count value N1, it returns to intermediate state B again.
Observe the rotation status in a narrow window of WS = ±1.5%.
In this intermediate state, it operates in a stable direction and the count value increases.
When N2 is reached, it switches to the final stable state D, PLL2 mode. Wind WS -1.5 in PLL2 mode
~+4.8%, which is slightly wider than intermediate state B, to prevent the mode from dropping unnecessarily. When this final stable state D is reached, the HSYO extraction window WD is switched from ±30% up to now to -1.5 to +4.8%, and noise is removed more reliably. Moreover, the jitter removal operation by the TBC circuit 21 is started, and stable reproduction is realized.

Even when rotating stably in PLL2 mode,
Impact or scratches on the disc may cause focus to drop and rotation to become unstable. At this time, when the count value N decreases to N1, the intermediate state C is
Switches to PLL1 mode and restarts rotation. If the rotation is successfully restarted in the intermediate state C, the intermediate state B returns to the final stable state D. If the restart of the rotation fails in intermediate state C, it will fall to the AFC mode of initial state A, where further restart of the rotation will be attempted, and the state will change to intermediate state B → (intermediate state C → intermediate state B) → final stable state. Switching to D.

FIG. 7 shows the actual mode transition situation. When the operation starts at point a, control is performed in AFC mode until the count value N reaches N1. When it reaches N1 at b, it switches to PLL1 mode (intermediate state B), but the count value N decreases and C
When it returns to N1, it switches to PLL1 mode (intermediate state C). Then count down and d
When the count value N becomes 0, the camera returns to AFC mode. The count value N does not fall below 0.

Reconstruction is attempted in AFC mode, and when it reaches N1 at e, it switches to PLL1 mode (intermediate state B). As the rotation control is switched from AFC control to PLL control, the rotation becomes temporarily unstable, the count value decreases and reaches N1 at f, and the mode is switched to PLL1 mode (intermediate state C). When the count is counted up again and reaches N1 at g, the circuit returns to PLL1 mode (intermediate state B). Further, the count continues to increase and when it reaches N2 at h, it switches to PLL2 mode. Count value N
does not rise above N2.

After that, the rotation became unstable for some reason,
When it reaches N1 at i, it falls to PLL1 (intermediate mode C) and is attempted to be restarted. When the rebuilding is successful and reaches N1 at j, it switches to PLL1 (intermediate mode B), and when it continues to count up and reaches N2 at k, it switches to PLL2.

After that, the rotation becomes unstable again, and when it reaches N1 at 1, it falls to PLL1 (intermediate mode C) and attempts to rebuild it. Once it reaches N1 at m, PLL1
(intermediate mode B), but the unstable state still continues, and when it reaches N1 at n, PLL1 (intermediate mode C)
and when the count value N reaches 0 at o
The camera is switched to AFC mode and restarted from the initial state.

As described above, mode transition is always performed with the aim of reaching the final stable state D.

〔Effect of the invention〕

As explained above, according to this invention,
In PLL control, after confirming the stable state of disk rotation, the control that should be performed in the stable state is executed, so the reliability of these controls can be guaranteed, and after confirming the stable state in PLL control, the window Since the disk rotation state is detected by expanding the distance a little, it is possible to prevent the control that should be performed to achieve the stable state from being stopped unnecessarily.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention. FIG. 2 is a diagram showing the positions of various windows used in the embodiment of FIG. 1. FIG. 3 is a diagram showing the state of the mode control circuit 70 of FIG. 1 in each mode. Figure 4 is the same as Figure 1.
7 is a diagram showing switching conditions for an LMT counter 72. FIG.
FIG. 5 is a diagram showing switching conditions for mode MD in FIG. 1. FIG. 6 is a diagram showing mode transitions according to FIGS. 4 and 5. FIG. FIG. 7 is a diagram showing an example of actual mode transition based on FIG. 7 and FIG. 6; 10... Disc, 12... Disc motor,
14...FG, 16...Head, 51...Mode control circuit.

Claims (1)

[Claims] 1. A first control circuit that controls the rotation of the disk motor by comparing a rotation detection signal of the disk motor with a reference clock; and a first control circuit that controls the rotation of the disk motor by comparing a synchronization signal in a disk reproduction signal with the reference clock. a second control circuit that controls rotation; a circuit that applies a window to the timing of the next expected synchronization signal based on the synchronization signal in the disc playback signal; a circuit that detects the synchronization signal that enters the window; If they are far apart, control is performed by the first control circuit, and at that time, the window is set wide to detect synchronization signals, and if synchronization signals are often obtained within this wide window, the second control circuit Switching to control by the control circuit, in the control by this second control circuit, the window is set narrowly and synchronization signals are detected, and when the number of synchronization signals entering this narrow window increases, it is determined that the state is stable. Execute the control that should be performed in a stable state, and in this stable state, set the window a little wider than the narrow window to detect a synchronization signal, and if the number of synchronization signals entering this window decreases, the state is determined to be unstable. 1. A control circuit for a disk motor, comprising: a control circuit that determines that the control is performed in the stable state and stops the control that should be performed in the stable state.