JPH02223930A - How to form an active matrix liquid crystal display - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to active matrix liquid crystal displays, and more particularly to a method of forming active matrix liquid crystal displays suitable for large area displays. [Prior Art] Conventionally, the structure of the display section of an active matrix liquid crystal display is, for example, JAPAN DISPLAY '83.
digest pp, 356-359. Here, FIG. 2 shows a pattern diagram of the display section used above. In FIG. 2, 10 is a gate electrode, 11
1 is a source electrode, and 12 is an intrinsic amorphous silicon film. 13 is a drain electrode, and 14 is ITO. [Problems to be Solved by the Invention] In the prior art described above, for example, in the structure of the display section as shown in FIG. 2, two masks are required to determine the positions of the gate, drain, and source portions of the TPT. By the way, when a large-area display is assumed, mask positioning is an extremely important issue. Particularly in the formation of TPT, misalignment of the gate, drain, and source portions causes fatal damage to the liquid crystal display. Therefore, when forming a large-area display, it is necessary to determine the positions of the gate, source, and drain portions of the TPT using one mask. An object of the present invention is to position the gate, source, and drain portions of a TPT using one mask in a display section of an active matrix liquid crystal display. [Means for Solving the Problems] The above object is to provide a method for forming a display section of an active matrix liquid crystal display, in which: 1) an intrinsic semiconductor film is deposited on a glass substrate, and an intrinsic semiconductor film is formed by one resist step and one etching step; patterning the semiconductor film; 2) depositing an insulating film after removing the resist; patterning the insulating film by one resist process and one etching process; 3) implanting impurity ions after removing the resist;
4) After removing the insulating film, a gate insulating film and a gate electrode film are sequentially deposited, and the gate electrode film and gate insulating film are sequentially patterned by one resist process and multiple etching processes.5) After removing the resist, remove impurities. Perform ion implantation and then perform silicidation treatment to silicide the extrinsic semiconductor film. 6) After silicidation treatment, deposit a transparent electrode film, and perform one resist process and one etching process to make only the transparent electrode film. This is achieved by patterning. [Operation] With the above process, one mask is required to gate TPT. The positions of the source and drain parts are determined. Therefore, formation of TPT becomes extremely easy. (Example) Hereinafter, an example of the present invention will be explained with reference to Fig. 1. Fig. 1 shows a process procedure of the display part forming method of the present invention. Intrinsic polycrystalline silicon r! Depositing Al and patterning the intrinsic polycrystalline silicon film 1 through one resist process and one etching process; b) After removing the resist, depositing a 5iOz film and performing one resist process and one etching process. The SiOz film is patterned by the following steps. After removing the resist, P (phosphorus) ions are implanted. As a result, a part of the intrinsic polycrystalline silicon film becomes the low resistance layer 2. c)
After removing the Si02 film, Ge1"5io2 film 3, Cr electrode 4
The Cr electrode 4. The gate Sj and the Oz film 3 are sequentially patterned. d) After removing the resist, P (phosphorous) ions are implanted, and then a silicidation process is performed, so that the extrinsic polycrystalline silicon crotch becomes Pt (platinum) silicide, that is, low resistance y! Becomes J2. Thereafter, ITO 5 is deposited, and only the ITO 5 is patterned by one resist I process and one etching process, and then the resist is removed. That is, according to the above procedure, one mask is used to gate the TPT. The positions of the source and drain parts are determined. Therefore, formation of TPT becomes extremely easy. Furthermore, a TFT can be formed by omitting only the P (phosphorous) ion implantation step in the above procedure. That is, a) the intrinsic polycrystalline silicon film 1 is deposited on the glass substrate 6, and the intrinsic polycrystalline silicon film 1 is patterned by one resist step and one etching step. b) After removing the resist, deposit a 5iOz film,
5iOz by nosist process and one etching process
Pattern the film. After removing the resist, a part of the intrinsic polycrystalline silicon film becomes Pt, silicide, that is, a low resistance layer 2 by performing a silicidation process. c) After removing the SiO2 film, Ge hs i
0211ffi3. sequentially depositing Cr'it poles 4;
Cr'jy, pole 4. by 18 resist 1-steps and multiple etching steps. After sequentially patterning the gate 5iOz pancreas 3, d) after removing the resist, a part of the intrinsic polycrystalline silicon film becomes PT silicide, that is, a low resistance layer 2 by performing a silicidation process. After that, ITO5 was deposited, one resist step and one
Only the ITO 5 is patterned by the second etching process, and then the resist is removed. That is, the above procedure is 1. The positions of the gate, source, and drain portions of the TPT are determined using a mask and without an ion implantation process. Therefore, formation of TPT becomes extremely easy. Here, a cross-sectional structure taken along line AA' in FIG. 1(d) is shown in FIG. In FIG. 3, 1 is an intrinsic polycrystalline silicon film, 2 is a low resistance layer (PL silicide), 3 is a gate 5j-02 film, 4 is a Cr electrode, and 5 is an ITO 16 is a glass substrate. In addition, ITO 7 for a storage capacitor is placed on the display section 9, and ITO 7 is placed on the glass substrate 6 for the storage capacitor.
, after depositing 5iO28 for a storage capacitor, the planar pattern will be exactly the same as that shown in FIG. 3 even if the process shown in FIG. 1 is used. The cross-sectional structure taken along line AA' at that time is shown in FIG. In FIG. 4, 1 is an intrinsic polycrystalline silicon film, 2 is a low resistance layer (Pt silicide), 3 is a gate 5iOz film, 4 is a Cr electrode, 5 is an ITO 16 glass substrate, 7 is an IT0. 8 is 1-
It is 5iOz for storage capacitor. By the way, in the structure shown in FIG. 4, since the ITO 7 is present via 5iOz8 directly under the low resistance layer 2 serving as a signal electrode, the load capacitance seen from the low resistance layer 2 becomes relatively large. Therefore, ITO 7 was deposited on the glass substrate 6, and after patterning the ITO 7 through 1-times of resist process and 1-time of etching process, 5i02° film 8 was deposited, and the following process shown in FIG. 1 was used. Figure 5(a) shows the plane pattern of
Shown below. In addition, the cross-sectional structure between B-B' in Fig. 5 (,) is shown in Fig. 5.
Shown in Figure (b). 1 in Figure 5 (,1) and (b)
is an intrinsic polycrystalline silicon film, 2 is a low resistance layer (Pt silicide), 3 is a gate 5iOz film, 4 is a Cr electrode, and 5 is an IT
O16 is a glass substrate, 7 is IT for storage capacitor
O18 is 5iOz for storage capacitor. 6th
In the structure shown in the figure, I
Since there is no TO, the load capacitance seen from the low resistance layer 2 serving as the signal electrode is small. Also, in the structure shown in Figure 6, TP
The gate, source, and drain portions of T are determined by one mask. Therefore, formation of TPT becomes extremely easy. [Effects of the Invention] According to the present invention, the positions of the source, drain, and goo portion of the TPT are determined with one mask, so that effects such as high throughput, low cost, and high yield of the display can be achieved. be.

[Brief explanation of the drawing]

FIG. 1 is a process procedure diagram of an embodiment of the present invention, FIG. 2 is a plan pattern diagram of a conventional display section, FIG. 3 is a cross-sectional view of a display section of an embodiment of the present invention, and FIG. 4 is a diagram of a conventional display section. Cross-sectional view of a display section according to an embodiment of the present invention FIG. 5 is a plan pattern diagram and a cross-sectional view of a display section according to an embodiment of the present invention. 1... Intrinsic polycrystalline silicon, 2... Low resistance layer, 3...
・Geto S i 02 , 4-Cr, 5 ・IT O1
6...Glass substrate, 7...ITO58 for storage capacitor...5iOz for storage capacitor, 10
...Goo 1-electrode, 11...source electrode, 12...
...Intrinsic amorphous silicon, 13...Drain electrode, 14...ITO. Agent Patent attorney Jl + Katsuo, 'ko≧, 11 Kuchiben 2... I Lstf: <#-Le 11 child Urodome (〆) Kayotsu / δ (in)

Claims (1)

[Claims] 1. In a method for forming a display section of an active matrix liquid crystal display, 1) depositing an intrinsic semiconductor film on a glass substrate, and patterning the intrinsic semiconductor film by one resist process and one etching process. 2) After removing the resist, deposit an insulating film and pattern the insulating film by one resist process and one etching process; 3)
) After removing the resist, perform ion implantation of impurities. 4) After removing the insulating film, deposit a gate insulating film and a gate electrode film in sequence, and deposit the gate electrode film and gate insulating film in one resist process and multiple etching processes. sequential patterning,
5) After removing the resist, implanting impurity ions and then performing a silicidation process to silicide the extrinsic semiconductor film; 6) After the silicidation process, depositing a transparent electrode film;
A method for forming a display section of an active matrix liquid crystal display, comprising a process of patterning only a transparent electrode film by performing one resist step and one etching step. 2. A method for forming a display section of an active matrix liquid crystal display, comprising: 1) sequentially depositing a transparent electrode film and an insulating film on a glass substrate; and 2) the following process according to claim 1. How to form a liquid crystal display. 3. In a method for forming a display part of an active matrix liquid crystal display, 1) depositing a transparent electrode film on a glass substrate and patterning the transparent electrode film by performing one resist process and one etching process, 2) removing the resist. 3) A method for forming an active matrix liquid crystal display, comprising the following steps: 3) depositing an insulating film. 4. A method for forming an active matrix liquid crystal display, wherein the intrinsic semiconductor film according to any one of claims 1, 2 and 3 is a polycrystalline silicon film or an amorphous silicon film.