JPH02215180A - Hybrid integrated circuit and manufacture thereof - Google Patents
Hybrid integrated circuit and manufacture thereofInfo
- Publication number
- JPH02215180A JPH02215180A JP3655989A JP3655989A JPH02215180A JP H02215180 A JPH02215180 A JP H02215180A JP 3655989 A JP3655989 A JP 3655989A JP 3655989 A JP3655989 A JP 3655989A JP H02215180 A JPH02215180 A JP H02215180A
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- hybrid integrated
- desired shape
- predetermined
- symbol
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0266—Marks, test patterns or identification means
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0097—Processing two or more printed circuits simultaneously, e.g. made from a common substrate, or temporarily stacked circuit boards
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/303—Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
Landscapes
- Parts Printed On Printed Circuit Boards (AREA)
- Structure Of Printed Boards (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
(イ)産業上の利用分野
本発明は混成集積回路に関し、特に異なった機能を有す
る混成集積回路を連続生産する場合に有効な混成集積回
路とその製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a hybrid integrated circuit, and more particularly to a hybrid integrated circuit and a manufacturing method thereof that are effective in serially producing hybrid integrated circuits having different functions.
(ロ)従来の技術
従来の混成集積回路はセラミックスあるいは絶縁金属等
の基板上に所望形状の導電路を形成し、その導電路上の
所定位置に印刷抵抗、トランジスタ、IC等の複数の回
路素子が付着され所定の機能を有する混成集積回路が提
供されていた。(B) Conventional technology In conventional hybrid integrated circuits, a conductive path of a desired shape is formed on a substrate made of ceramics or insulating metal, and multiple circuit elements such as printed resistors, transistors, and ICs are placed at predetermined positions on the conductive path. Hybrid integrated circuits have been provided with attached and predetermined functions.
斯る混成集積回路を製造する場合、所定の基板を用意し
、その基板上に導電パターンを形成する工程と、導電パ
ターン間に印刷抵抗体を形成する工程と、導電パターン
上にチップ状の回路素子を付着する工程とを複数の組立
工程を有した組立ライン上によって所定の混成集積回路
が形成されている。When manufacturing such a hybrid integrated circuit, there are three steps: preparing a predetermined substrate, forming a conductive pattern on the substrate, forming a printed resistor between the conductive patterns, and forming a chip-shaped circuit on the conductive pattern. A predetermined hybrid integrated circuit is formed on an assembly line having a plurality of assembly steps including the step of attaching elements.
(ハ)発明が解決しようとする課題
上述した従来の混成集積回路では導電パターンのパター
ン形状を用いて混成集積回路の種別あるいは品別が行わ
れていた。上述の様に混成集積回路を製造する場合、通
常組立ラインには同種類の機種、即ち同一導電パターン
を有した基板が搬送されて所定の組立が行われている。(c) Problems to be Solved by the Invention In the conventional hybrid integrated circuit described above, the type or product of the hybrid integrated circuit is determined using the pattern shape of the conductive pattern. When manufacturing a hybrid integrated circuit as described above, substrates of the same type, that is, having the same conductive pattern, are usually transported to an assembly line and subjected to predetermined assembly.
しかしながら、必しも同一組立ライン上に同種類の基板
が搬送されるのではなし、実際製造するに当り、異種の
導電パターンを有する基板が搬送され組立ライン上で組
立きれている。この場合同一の工程区間内で異なる工程
がある場合、例えば印刷抵抗体形成時に抵抗体形成の位
置が異なる場合、あるいは抵抗体形成の数が異なる場合
等では人間が手作業によって振り分は作業を行っている
作業性及び作業能率が著しく低下している問題点があっ
た。However, substrates of the same type are not necessarily transported on the same assembly line; in actual manufacturing, substrates having different types of conductive patterns are transported and assembled on the assembly line. In this case, if there are different processes within the same process section, for example, if the positions of the resistors are different when forming the printed resistor, or if the number of resistors is different, humans will have to manually distribute the work. There was a problem in that the work efficiency and work efficiency were significantly reduced.
(ニ)課題を解決するための手段
本発明は上述した課題に鑑みて為されたものであり、所
望形状に形成された混成集積回路基板と、前記混成集積
回路基板上に金属箔より形成された所望形状の導電路と
、前記導電路上に固着された複数の回路素子とを備えた
混成集積回路において、前記混成集積回路基板上の所定
位置に所望形状の標識記号を設け、その標識記号を用い
て混成集積回路を組立てて解決する。(d) Means for Solving the Problems The present invention has been made in view of the above-mentioned problems, and includes a hybrid integrated circuit board formed into a desired shape, and a metal foil formed on the hybrid integrated circuit board. In a hybrid integrated circuit comprising a conductive path having a desired shape and a plurality of circuit elements fixed on the conductive path, a marker symbol having a desired shape is provided at a predetermined position on the hybrid integrated circuit board, and the marker symbol is to assemble and solve hybrid integrated circuits.
(*)作用
この様に混成集積回路基板上の所定位置に標識記号を設
け、その標識記号を用いて混成集積回路の組立を行うこ
とにより、組立ライン上に異種の組立工程を有する基板
が搬送されたとしても前記標識記号によってあらかじめ
定められたデータに基づいて組立工程が行われるため効
率のよい組立工程を実現することができる特徴を有する
。(*) Effect In this way, by providing a marker symbol at a predetermined position on a hybrid integrated circuit board and assembling a hybrid integrated circuit using the symbol symbol, boards having different assembly processes are transported on the assembly line. Even if the assembly process is performed based on the data predetermined by the marking symbol, the assembly process can be carried out efficiently.
(へ)実施例
以下に図面に示した実施例に基づいて本発明の混成集積
回路及びその製造方法を詳細に説明する。(F) Embodiments The hybrid integrated circuit of the present invention and its manufacturing method will be explained in detail below based on the embodiments shown in the drawings.
第1図に示す如く、本発明の混成集積回路は、セラミッ
クスあるいは絶縁処理された金属等の混成集積回路基板
(5)と、基板(5)上にエポキシ樹脂等の絶縁樹脂層
(図示しない)を介して形成された所望形状の導電路(
2)と、導電路(2)上に付着された複数の回路素子(
7)と、基板(5)上の所定位置に設けられた標識記号
(4)とから構成されている。As shown in FIG. 1, the hybrid integrated circuit of the present invention includes a hybrid integrated circuit board (5) made of ceramics or insulated metal, and an insulating resin layer (not shown) such as epoxy resin on the board (5). A conductive path of desired shape formed through (
2) and a plurality of circuit elements (
7) and a marker symbol (4) provided at a predetermined position on the substrate (5).
以下に第2図A乃至第4130に基づいてその製造方法
を説明する。The manufacturing method will be described below based on FIGS. 2A to 4130.
先ず、第2図Aに示す如く、短冊状の絶縁基板(1)を
用意し、その基板(1)の−主面上の個別基板となる領
域(点線内)(3)・・・(3)に所望形状の導電路(
2)・・・(2)を形成する。絶縁基板(1)としては
0゜5〜1.0■厚の金属、例えばアルミニウムを用い
、そのアルミニウムの基板(1)は周知の陽極酸化によ
ってその表面に酸化アルミニウム被膜(図示せず)が形
成され、更に基板の一生面に第1図に示す如く導電路(
2)・・・(2)が形成される。基板(1)上には導電
金属箔、例えば銅箔が粘着される。金属箔表面はスクリ
ーン印刷によって所望の導電路(2)・・・(2)を露
出してレジストでマスクされ、貴金属(金、銀、白金)
メツキ層が金属箔表面にメツキされる。然る後レジスト
を除去して貴金属メツキ層をマスクとして金属箔のエツ
チングを行い所望の導電路(2)・−(2)が形成され
る。スクリーン印刷による導電路(2)・−(2)の細
さは0.51が限界であるので、極細配線を必要とする
ときは周知の写真蝕刻技術に依り約2μまでの極細導電
路(2)・・・(2)の形成が可能となる。First, as shown in FIG. 2A, a strip-shaped insulating substrate (1) is prepared, and areas (within dotted lines) that will become individual substrates on the main surface of the substrate (1) (3)...(3) ) with the desired shape of the conductive path (
2)...(2) is formed. The insulating substrate (1) is made of a metal such as aluminum with a thickness of 0.5 to 1.0 mm, and an aluminum oxide film (not shown) is formed on the surface of the aluminum substrate (1) by well-known anodic oxidation. Furthermore, conductive paths (
2)...(2) is formed. A conductive metal foil, for example a copper foil, is adhered onto the substrate (1). The surface of the metal foil is screen printed to expose the desired conductive paths (2)...(2) and masked with a resist, and then coated with noble metals (gold, silver, platinum).
A plating layer is plated on the surface of the metal foil. Thereafter, the resist is removed and the metal foil is etched using the noble metal plating layer as a mask to form desired conductive paths (2) and -(2). The thinness of the conductive paths (2) and -(2) by screen printing is limited to 0.51 mm, so when ultra-fine wiring is required, the ultra-fine conductive paths (2 )...(2) can be formed.
本工程で大切な点はスクリーン印刷時に各導電路(2)
・・・(2)に対応する個別の標識記号(4)を印刷す
る。即ち、個別基板領域(3)・・・(3)内のエッチ
部の余白領域にバーコードを印刷し、銅箔のパターン形
成時で標識記号(4)を形成する。標識記号(4)は銅
箔により形成されているため、その表面上には腐蝕を防
止するために所定のメツキ工程によりNiメツキ膜を形
成する。The important point in this process is that each conductive path (2) is
...Print the individual indicator symbol (4) corresponding to (2). That is, a bar code is printed in the margin area of the etched portion in the individual substrate areas (3)...(3), and an indicator symbol (4) is formed when patterning the copper foil. Since the marker symbol (4) is formed of copper foil, a Ni plating film is formed on its surface by a predetermined plating process to prevent corrosion.
第4図は標識記号(4)を示す拡大図であり、銅箔によ
って組立工程に必要な最小限のデータとなるバーコード
記号が示されている。斯る標識記号(4)の場合は、微
細加工を必要であるため写真蝕刻法によって形成する。FIG. 4 is an enlarged view showing the marker symbol (4), in which a bar code symbol, which is the minimum data necessary for the assembly process, is shown using copper foil. In the case of the marker symbol (4), since microfabrication is required, it is formed by photolithography.
また標識記号(4)は第4図に示したバーコード記号の
みによるものでは無く、そのバーコード即ち標識記号(
4)の外形パターンを認識することで対応することがで
きる。Furthermore, the sign symbol (4) is not only based on the barcode symbol shown in Fig. 4, but also the barcode, that is, the sign symbol (
4) can be dealt with by recognizing the external shape pattern.
複数の個別基板領域(3)・・・(3)に形成する標識
記号(4)は組立ライン上の組立工程が異なるものにつ
いてはバーコード即ちデータの異なる標識記号(4)を
形成し、組立工程が同一なものは同じデータを有した標
識記号(4)を形成する。斯る標識記号(4)は後述す
る各組立工程前に所定の認識装置によってそのデータを
認識し各工程を行うものとする。For the marking symbols (4) formed on the plurality of individual board areas (3)...(3), if the assembly process on the assembly line is different, marking symbols (4) with different barcodes or data are formed. If the process is the same, an indicator symbol (4) having the same data is formed. The data of the indicator symbol (4) is recognized by a predetermined recognition device before each assembly process to be described later, and each process is performed.
また、標識記号(4)は上述した如く、デー、夕を有す
るバーコードのみならず、標識記号(4)の外形パター
ン形状で各組立工程を選択することもできる。Further, as described above, the marker symbol (4) is not limited to a bar code having day and night, but each assembly process can also be selected based on the external pattern shape of the marker symbol (4).
以上においては銅箔を用いた標識記号(4)の説明をし
たが、第3図の如く、個別基板領域(3)内に所望形状
の孔(4゛)を形成して、その孔(4′)の外形パター
ン形状を認識し各工程を選択することもできる。標識記
号(4)は前述した様に余白部分となる領域であれば任
意であるが、パターン面積を有効に使用するために個別
基板領域(3)・−(3)の周端部に形成することが好
ましい、その周端部には後にケース材が固着されるため
パターン形成時のパターン面積の低下には何んの問題も
ない。In the above, the marking symbol (4) using copper foil has been explained, but as shown in Fig. 3, a hole (4゛) of a desired shape is formed in the individual board area (3). It is also possible to select each process by recognizing the external pattern shape of '). As mentioned above, the marker symbol (4) can be placed anywhere as long as it is a blank area, but in order to effectively use the pattern area, it is formed at the peripheral edge of the individual substrate areas (3) and -(3). It is preferable that the case material is fixed to the peripheral end portion later, so that there is no problem in reducing the pattern area during pattern formation.
次に第2図Bに示す如く、個別基板領域(3)・・・(
3)の周端部に雄型金型を用いてプレス打抜きを行い複
数の個別集積回路基板(5)・・・(5)に分離する0
分離された複数の個別集積回路基板(5)・・・(5)
は夫々少なくとも異なった組立工程を有する基板であり
、それらは所定の組立工程を有した組立ラインに搬送さ
れ所望の機能を有した混成集積回路が組立される。Next, as shown in FIG. 2B, the individual substrate area (3)...
Press punching is performed on the peripheral edge of 3) using a male mold to separate it into a plurality of individual integrated circuit boards (5)...(5)0
A plurality of separated individual integrated circuit boards (5)...(5)
are boards having at least different assembly processes, and are transported to an assembly line having a predetermined assembly process to assemble a hybrid integrated circuit having a desired function.
組立工程は所定の抵抗値を有する印刷抵抗体り6)を形
成する抵抗体形成工程と、半導体素子(7)やチップ部
品を導電路(2)上に載置するグイボンディング工程と
、半導体素子(7)の電極と対応する導電路(2)とを
金あるいはアルミニウムのボンディングワイヤで接続す
るワイヤボンディング工程と、回路機能検査や特性のm
tを行うファンクショナルトリミング等を行う検査工程
より構成されている。抵抗体形成工程では所定の導電路
(2)間にシルクマスクを用いて抵抗ペーストをスクリ
ーン印刷して焼成して形成する。グイボンディング工程
では、導電路(2)の所望位置に半導体集積回路等の半
導体素子(7)を導電ペーストを用いて固着し、チップ
部品(図示せず)は半田付けする0次にワイヤボンディ
ング工程では、自動デジタルボンダー装置により半導体
素子(7〉の電極と導電路(2)とをパターン認識しな
がら超音波ボンディングあるいはネールへラドボンディ
ングによりボンディングワイヤで自動的に接続する。The assembly process includes a resistor formation process to form a printed resistor body 6) having a predetermined resistance value, a bonding process to place the semiconductor element (7) and chip components on the conductive path (2), and a bonding process to place the semiconductor element (7) and chip components on the conductive path (2). A wire bonding process that connects the electrode (7) and the corresponding conductive path (2) with a gold or aluminum bonding wire, and a circuit function test and characteristic test.
The inspection process includes functional trimming and the like. In the resistor forming step, a resistor paste is screen printed between predetermined conductive paths (2) using a silk mask and then baked. In the wire bonding process, a semiconductor element (7) such as a semiconductor integrated circuit is fixed to a desired position of a conductive path (2) using a conductive paste, and a chip component (not shown) is soldered in a zero-order wire bonding process. Then, an automatic digital bonder device automatically connects the electrodes of the semiconductor element (7) and the conductive paths (2) with bonding wires by ultrasonic bonding or nail-to-nail rad bonding while recognizing patterns.
次に第2図Cに示す如く、搬送レール上に搬送された複
数の集積回路基板(5)・・・(5)上の所定位置に上
述した組立工程の抵抗体形成工程を行う、斯る搬送レー
ル上には異なった組立工程を有した基板(5)・・・(
5)が搬送されているものとし、標識記号(4)によっ
て所定の工程を選択する。Next, as shown in FIG. 2C, the resistor forming step of the above-mentioned assembly process is performed at predetermined positions on the plurality of integrated circuit boards (5)...(5) transported on the transport rail. On the transport rail are boards (5) with different assembly processes...
5) is being transported, and a predetermined process is selected using the indicator symbol (4).
印刷抵抗体形成工程には本実施例では3カ所のスクリー
ン印刷工程が備えられており、スクリーンAでは100
Ω、スクリーンBではIKΩ、スクリーンCではIOK
Ωの抵抗値を有する抵抗体を印刷形成する0例えば夫々
の基板(5)上に100Ω、IKΩとIOKΩ、100
ΩとIKΩと10にΩ、を形成する場合、従来ではA、
B、Cの3工程を必要としないものについては手作業に
よってM9分けを行っていたが、本発明では印刷工程前
に標識記号(4)を認識装置(8)を用いて、光学的あ
るいはXsによって標識記号(4)(バーフード)の数
字コードの所定のデータを認識し、そのデータに基づい
て選択して抵抗体が印刷される。即ち、認識装置(8)
と印刷抵抗体形成装置とが所定の接続手段によって接続
され、認識された標識記号(4)のデータは抵抗体形成
装置のコントロール装置に供給され、そのデータに基づ
いてスクリーン工程A、B、Cあるいはその組合せたス
クリーン工程が選択きれる。In this embodiment, the printed resistor forming process includes three screen printing processes, and screen A has 100 screen printing processes.
Ω, IKΩ on screen B, IOK on screen C
For example, on each substrate (5), print a resistor having a resistance value of 100Ω, IKΩ and IOKΩ, 100Ω.
When forming Ω, IKΩ, and 10Ω, conventionally A,
For products that do not require the three steps of B and C, M9 classification was performed manually, but in the present invention, before the printing process, the marking symbol (4) is divided into optical or Xs using a recognition device (8). The predetermined data of the numerical code of the marker symbol (4) (bar food) is recognized by the operator, and the resistor is selected and printed based on the data. That is, the recognition device (8)
and the printed resistor forming apparatus are connected by a predetermined connecting means, and the data of the recognized sign symbol (4) is supplied to the control device of the resistor forming apparatus, and the screen processes A, B, and C are performed based on the data. Alternatively, a combination of these screening processes can be selected.
例えば基板(5′)に形成された標識記号(4)ではA
、B、Cのスクリーン工程が行われ、基板(5“)では
B、Cのスクリーン工程が行われ、基板(5)ではAの
スクリーン工程が行われている。For example, in the marking symbol (4) formed on the substrate (5'), A
, B, and C are performed on the substrate (5''), and the screen process A is performed on the substrate (5'').
次は第2図りに示す如く、抵抗体形成後、複数の基板(
5)・・・(5)はグイボンディング工程に搬送されチ
ップ部品の回路素子(7)が固着される。この工程にお
いても第2図Cの工程と同様に標識記号(4)が認識装
置(8)によって認識され、そのデータに基づいた大き
さの異なる素子(7)あるいは異なる位置に素子(7)
が選択して固着きれる。Next, as shown in the second diagram, after forming the resistor, multiple substrates (
5)...(5) is transported to a bonding process and the circuit element (7) of the chip component is fixed. In this step as well, the marker symbol (4) is recognized by the recognition device (8) in the same way as the step in FIG.
can be selected and fixed.
斯る標識記号(4)は組立工程前にに認識することによ
り、記号(4)のデータに基づいた工程が選択されて行
え製造工程が円滑に行えるものである。By recognizing the mark symbol (4) before the assembly process, a process based on the data of the symbol (4) can be selected and performed, and the manufacturing process can be carried out smoothly.
本実施例では印刷抵抗体形成工程、グイボンディング工
程を用いて説明したが、同一組立ライン上での工程の各
工程に使用することが可能であり、例えば抵抗体のトリ
ミング工程時にも当然のことながら使用することができ
る。Although this embodiment has been explained using the printed resistor forming process and the bonding process, it can also be used in each process on the same assembly line, and can also be used, for example, in the resistor trimming process. It can be used while
(ト)発明の効果
以上に詳述した如く、本発明に依れば、組立ライン上に
異なる組立工程を有する基板を搬送したとしても、あら
かじめ基板上に設けられた標識記号を認識することで、
そのデータに定められた工程が行え安定した組立工程が
行える。(G) Effects of the Invention As detailed above, according to the present invention, even if boards having different assembly processes are transported on the assembly line, the marking symbols provided on the boards in advance can be recognized. ,
The process determined by that data can be performed and a stable assembly process can be performed.
また、本発明では標識記号の認識によって各工程が選択
されるため製造ラインの完全自動化が行え作業能率が著
しく向上するものである。Furthermore, in the present invention, each process is selected by recognizing the sign symbol, so that the manufacturing line can be completely automated and work efficiency is significantly improved.
第1図は本発明の混成集積回路を示す組立て斜視図、第
2図A乃至第2図り及び第3図は第1130に示した混
成集積回路を製造するための工程図、第4150は本実
施例で用いられる標識記号を示す拡大図である。
(5)・・・混成集積回路基板、(4)・・・標識記号
、(2)・・・導電路。FIG. 1 is an assembled perspective view showing the hybrid integrated circuit of the present invention, FIGS. 2A to 2 and 3 are process diagrams for manufacturing the hybrid integrated circuit shown in FIG. FIG. 3 is an enlarged view showing the indicator symbols used in the example; (5)...Hybrid integrated circuit board, (4)...Label symbol, (2)...Conducting path.
Claims (11)
状の導電路と、 前記導電路上に固着された複数の回路素子とを備えた混
成集積回路において、 前記混成集積回路基板上の所定位置に所定のデータを有
する標識記号が設けられていることを特徴とする混成集
積回路。(1) A hybrid integrated circuit board formed in a desired shape, a conductive path in a desired shape formed of metal foil on the hybrid integrated circuit board, and a plurality of circuit elements fixed on the conductive path. A hybrid integrated circuit, characterized in that an indicator symbol having predetermined data is provided at a predetermined position on the hybrid integrated circuit board.
とを特徴とする請求項1記載の混成集積回路。(2) The hybrid integrated circuit according to claim 1, wherein the sign symbol is formed from the metal foil.
た孔であることを特徴とする請求項1記載の混成集積回
路。(3) The hybrid integrated circuit according to claim 1, wherein the indicator symbol is a hole provided in the hybrid integrated circuit board.
るケース材の固着領域あるいは外部リード端子が固着さ
れる固着領域に形成されていることを特徴とする請求項
2又は3記載の混成集積回路。(4) The hybrid integrated circuit according to claim 2 or 3, wherein the indicator symbol is formed in a fixed area of a case material fixed to the hybrid integrated circuit board or in a fixed area to which an external lead terminal is fixed. circuit.
及び標識記号を形成する工程と、 所定の読取り装置で前記標識記号を読取る工程と、 前記装置で読取られた標識記号のデータに基づいて組立
ラインの所定の組立工程を行う工程とを具備することを
特徴とする混成集積回路の製造方法。(5) preparing a hybrid integrated circuit board with a desired shape; forming conductive paths and marking symbols with a desired shape from metal foil on the hybrid integrated circuit board; and reading the marking symbols with a predetermined reading device. A method for manufacturing a hybrid integrated circuit, comprising the steps of: performing a predetermined assembly process on an assembly line based on the data of the sign read by the device.
集積回路基板が搬送されていることを特徴とする請求項
5記載の混成集積回路の製造方法。(6) The method of manufacturing a hybrid integrated circuit according to claim 5, wherein hybrid integrated circuit boards having different types of assembly processes are transported to the assembly line.
程と、 前記混成集積回路基板上に金属箔により所望形状の導電
路及び標識記号を形成する工程と、所定の読取り装置で
前記標識記号を読取る工程と、 前記装置で読取られた標識記号のデータに基づいて前記
複数の混成集積回路基板の各々の所定の前記導電路間に
印刷抵抗体を形成する工程とを具備することを特徴とす
る混成集積回路の製造方法。(7) a step of preparing a plurality of hybrid integrated circuit boards having a desired shape; a step of forming conductive paths and marking symbols of a desired shape with metal foil on the hybrid integrated circuit board; and a step of using a predetermined reading device to read the marking symbols. and forming a printed resistor between predetermined conductive paths of each of the plurality of hybrid integrated circuit boards based on the data of the symbol read by the device. A method for manufacturing a hybrid integrated circuit.
上形成されていることを特徴とする請求項7記載の混成
集積回路の製造方法。(8) The method for manufacturing a hybrid integrated circuit according to claim 7, wherein the printed resistors are formed at at least one location with different values.
程と、 前記混成集積回路基板上に金属箔により所望形状の導電
路及び標識記号を形成する工程と、前記複数の混成集積
回路基板の各々の所定の前記導電路間に印刷抵抗体を形
成する工程と、所定の読取り装置で前記標識記号を読取
る工程と、 前記装置で読取られた標識記号のデータに基づいて前記
印刷抵抗体のトリミング調整を行う工程とを具備するこ
とを特徴とする混成集積回路の製造方法。(9) a step of preparing a plurality of hybrid integrated circuit boards having a desired shape; a step of forming conductive paths and sign symbols of a desired shape with metal foil on the hybrid integrated circuit board; forming a printed resistor between each predetermined conductive path; reading the marker symbol with a predetermined reading device; and trimming the printed resistor based on the data of the marker symbol read by the device. 1. A method for manufacturing a hybrid integrated circuit, comprising the step of making an adjustment.
工程と、 前記混成集積回路基板上に金属箔により所望形状の導電
路及び標識記号を形成する工程と、所定の読取り装置で
前記標識記号を読取る工程と、 前記装置で読取られた標識記号のデータに基づいて前記
複数の混成集積回路基板の各々の所定の前記導電路上に
複数のチップ部品を載置することを特徴とする混成集積
回路の製造方法。(10) A step of preparing a plurality of hybrid integrated circuit boards having a desired shape, a step of forming conductive paths and marking symbols of a desired shape using metal foil on the hybrid integrated circuit board, and a step of using a predetermined reading device to read the marking symbols. and placing a plurality of chip components on a predetermined conductive path of each of the plurality of hybrid integrated circuit boards based on the data of the sign read by the device. manufacturing method.
とする請求項1,5,7,9又は10記載の混成集積回
路及びその製造方法。(11) The hybrid integrated circuit and its manufacturing method according to claim 1, 5, 7, 9, or 10, wherein the indicator symbol uses a bar code.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3655989A JPH02215180A (en) | 1989-02-16 | 1989-02-16 | Hybrid integrated circuit and manufacture thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3655989A JPH02215180A (en) | 1989-02-16 | 1989-02-16 | Hybrid integrated circuit and manufacture thereof |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH02215180A true JPH02215180A (en) | 1990-08-28 |
Family
ID=12473114
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3655989A Pending JPH02215180A (en) | 1989-02-16 | 1989-02-16 | Hybrid integrated circuit and manufacture thereof |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH02215180A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006134910A (en) * | 2004-11-02 | 2006-05-25 | Hitachi Kokusai Electric Inc | Printed circuit board manufacturing method |
-
1989
- 1989-02-16 JP JP3655989A patent/JPH02215180A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006134910A (en) * | 2004-11-02 | 2006-05-25 | Hitachi Kokusai Electric Inc | Printed circuit board manufacturing method |
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