JPH02210816A - Compound semiconductor lamination body - Google Patents

Abstract

PURPOSE:To form a compound semiconductor layer whose crystal lattice constant is larger than gallium arsenide and the like, on a silicon substrate of large area, with excellent crystallizability, by interposing a specified compound semiconductor layer having almost the same crystal lattice constant as the compound semiconductor layer between the silicon substrate and the compound semiconductor layer. CONSTITUTION:On a silicon substrate 1, a second compound semiconductor layer 2 composed of Ge1-xSnx, mixed crystal of germanium and tin, is formed as a buffer layer, and thereon a compound semiconductor layer 3 is formed. The crystal lattice constant of Ge1-xSnx can be continuously changed by changing the mixed crystal ratio (x). As a result, when the mixed crystal ratio (x) is so selected that the crystal lattice constant of the second compound semiconductor layer 2 coincides with the crystal lattice constant of a compound semiconductor layer 3 to be formed on the layer 2, dislocation is not caused on the interface 5 between the second compound semiconductor layer 2 and the compound semiconductor layer 3. Thereby, a compound semiconductor layer whose crystal lattice constant is larger than gallium arsenide and germanium can be formed on the silicon substrate of large area, with excellent crystallizability.

Description

[Detailed Description of the Invention] [Summary] Regarding a large-area compound semiconductor stack with good crystallinity, a compound semiconductor layer with a larger crystal lattice constant than gallium arsenide or germanium is formed on a large-area silicon substrate with good crystallinity. In a compound semiconductor stack having a compound semiconductor layer on a silicon substrate, a crystal of the compound semiconductor layer is placed between the silicon substrate and the compound semiconductor layer. It is composed of a compound semiconductor layered body in which a mixed crystal layer of germanium and tin having a crystal lattice constant that is approximately the same as the lattice constant is interposed.

[Industrial application field]

The present invention relates to improvements in compound semiconductor stacks, and particularly to improvements in large-area compound semiconductor stacks with good crystallinity.

[Conventional technology]

Electronic devices using compound semiconductors have the characteristic of being able to perform signal processing faster than electronic devices using silicon semiconductors, which are currently widely used. However, since compound semiconductors use rare metals such as gallium and indium, they are expensive and difficult to manufacture large-area substrates such as silicon substrates.

In recent years, as a result of various research efforts to manufacture large-area compound semiconductor substrates, the vapor phase growth method (CVD method) has recently been developed.
, crystal growth of a compound semiconductor layer on a silicon substrate using a crystal growth method such as molecular beam crystal growth method (MBE method),
It has become possible to manufacture large area compound semiconductor substrates. However, the crystal-grown compound semiconductor layer contains many defects such as dislocations, and the surface morphology is poor, resulting in unevenness on one surface. Therefore, it is difficult to form electronic devices with a high degree of integration on this compound semiconductor layer. That is currently impossible. The main reason for the poor surface morphology is that there is a difference of approximately 4% between the crystal lattice constant of silicon and that of compound semiconductors, such as gallium arsenide.
It is thought that this is because there is a large difference in the coefficient of thermal expansion, and the coefficient of thermal expansion is also twice as large. Therefore, in order to solve this problem, a layer of germanium, which has almost the same crystal lattice constant and thermal expansion coefficient as gallium arsenide, is interposed between the silicon substrate and the gallium arsenide layer. A method has been developed to absorb dislocations caused by lattice mismatch between the arsenic layer and the arsenic layer.

[Problem to be solved by the invention]

However, when the compound semiconductor layer is made of indium gallium arsenide, indium phosphorous, indium arsenide, indium antimony, etc., which have a larger crystal lattice constant than gallium arsenide, even if a germanium layer is interposed as a buffer layer, the silicon substrate The lattice mismatch between the semiconductor layer and the compound semiconductor layer cannot be alleviated, and dislocations generated at the interface reach the surface of the compound semiconductor layer, significantly degrading the electrical characteristics when a device is formed.

An object of the present invention is to make it possible to form a compound semiconductor layer having a larger crystal lattice constant than gallium arsenide or germanium on a large area silicon substrate so as to have good crystallinity.

[Means to solve the problem]

The above object is to provide a compound semiconductor laminate having a compound semiconductor layer (3) on a silicon substrate (1), in which the compound semiconductor layer (3) is provided between the silicon substrate (1) and the compound semiconductor layer (3). Crystal lattice constant of semiconductor layer (3)
This is achieved by a compound semiconductor stack formed by interposing a mixed crystal layer (2) of germanium and tin having roughly the same crystal lattice constant. The interposed mixed crystal layer may have a laminated structure (2.21) in which the crystal lattice constant is gradually changed from the crystal lattice constant of silicon to the crystal lattice constant of the compound semiconductor layer (3).

[Effect]

Refer to FIG. 1 In the compound semiconductor stack according to the present invention, a second compound semiconductor layer 2 made of Ge, -113H, which is a mixed crystal of germanium and tin, for example, is formed on the silicon base FiI.
is formed as a buffer layer, and a compound semiconductor layer 3 is formed thereon.
form. By changing the value of the mixed crystal ratio X of Ge and □Snx, the crystal lattice constant can be continuously changed from 5.64613 to 6.48920. G
If the mixed crystal ratio
Second compound semiconductor 1112 made of Ge+-*Sn
No dislocation occurs at the interface 5 between the compound semiconductor layer 3 and the compound semiconductor layer 3.

On the other hand, since the crystal lattice constants of the silicon substrate l and the second compound semiconductor layer 2 made of Ge+□Sn are mismatched, many dislocations occur at the interface 4 due to the mismatch of crystal lattice constants. If the second compound semiconductor layer 2 made of Ge+-xsng is formed sufficiently thick, Ge+-*S
The number of dislocations reaching the surface 5 of the second compound semiconductor layer 2 made of ny can be sufficiently reduced. As a result, dislocations reaching the surface of the compound semiconductor layer 3 are
Only a very small portion of the dislocations occur at the interface 4 between the semiconductor layer 2 and the second compound semiconductor layer 2 made of Ge, -, and Sn.

Table 1 Silicon 5.43095 Germanium 5.64613 Tin
6.48920 gallium arsenide
5.6533 Indium Arsenic 6.0584
6.4794 gallium antimony 5.8686 gallium antimony
6.0959 In this way, the compound semiconductor layer 2 made of Ge, -, Sn, and L can be made of indium arsenide, indium antimony, indium phosphorus, gallium antimony, or a combination of indium arsenide and gallium arsenide shown in Table 1. As a buffer layer when growing a compound semiconductor layer having a lattice constant larger than that of gallium, such as indium gallium arsenide, which has a lattice constant between Since dislocations generated at the interface 4 between the substrate 1 and the second compound semiconductor layer 2 are suppressed from reaching the surface of the compound semiconductor layer 3, the surface morphology of the compound semiconductor layer 3 becomes extremely flat, and dislocations are formed there. The electrical characteristics of the device become better.

Note that if at least two compound semiconductor layers are interposed between the silicon substrate 1 and the compound semiconductor layer 3 and the lattice constant of the compound semiconductor layer is gradually changed from the lattice constant of the silicon substrate 1 to the lattice constant of the compound semiconductor layer 3, The lattice mismatch at each interface is reduced, the number of dislocations generated at each interface is reduced, and the surface morphology of the compound semiconductor layer 3 becomes even more flat.

〔Example〕

Hereinafter, compound semiconductor stacked bodies according to two embodiments of the present invention will be described with reference to the drawings.

Refer to Figure 2. On a silicon substrate 1, a compound semiconductor layer 2 consisting of Gea, taSno, ti and I no, s*Gao, ayAs
A layer 3 and an InP layer 6 are formed, and the manufacturing method thereof will be explained below.

Metal-organic vapor phase epitaxy using, for example, tetramethylgermanium and tetramethyltin on a silicon substrate 1 (
Geo, qaSn・,ih using MOCVD method)
A compound semiconductor layer 2 is formed to a thickness of about ln, and on top of that, a five-layer layer of I n *, ssG a 11.4tA is formed using MOCVD using, for example, trimethyl indium, trimethyl gallium, and arsine. 3 to a thickness of about 1,000 mm, and then MOCVD using, for example, trimethyl indium and phosphine.
The InP layer 6 is formed to have a thickness of approximately 5,000 wafers by using the method.

Geo, yaSno, gi layer 2 and Ino, ssG
ao, 4? A: The crystal lattice constants of the 5-layer 3 and the InP layer 6 are 5.8686 and are the same, so no dislocations occur due to lattice mismatch at the interfaces 5 and 7 of these layers. G ea, yas n
Although dislocations occur due to lattice mismatch at the interface 4 with the o,
, the number of dislocations reaching the surface of the th layer 2 can be reduced. In addition, it has the same crystal lattice constant as the InP layer 6,
Furthermore, I no and ssG a have different compositions.
oltAs layer 3 and InP layer 6, Ge@, raSno,
*Geo, ra by forming between h layer 2
Dislocations that have reached the surface of the Sno, tb layer 2 can be further reduced, and the surface morphology of the InP layer 6 becomes flat.

3. On the silicon substrate 1, a Ge layer 21, Gea, y4Sn*
, zh layer 2 and I no, ssG ae, 4? A
The s-layer 3 and the 1nP layer 6 are formed, and the manufacturing method thereof will be explained below.

A Ge layer 21 is formed on the silicon substrate 1 using the MOCVD method.
is formed to a thickness of about 0.5 μm, and Geo, taSn
o, Ti layer 2 is formed to a thickness of about 0.5n, and then I
ns, 5sGa*, 5yAj 1 layer 3 is formed to a thickness of about 1,000 layers, and an InP layer 6 is further formed to a thickness of about 5,000 layers. From silicon substrate 1 to Ino, ssGa
o, 4? Since the crystal lattice constant changes in two steps up to the AS layer 3, the lattice mismatch at the interface 8 between the silicon substrate 1 and the Ge layer 21 and the lattice mismatch at the interface 9 between the Ge layer 21 and the Geo, taSno, and zi layers 2 occur. Matching is done by silicon substrate 1 and Geo
, vaSno, and xh due to the lattice mismatch at the interface with the layer 2, the number of dislocations generated at each interface 8 and 9 is reduced, and the surface morphology of the InP layer 6 is further flattened. Note that the more steps of changing the crystal lattice constant, the better the crystallinity of the compound semiconductor layer 6 can be obtained.

In addition, in the above examples, G by the MOCVD method is
Growth of the eSn layer is carried out at a temperature of 300 to 550 °C, 3
If it is lower than 00°C, a growth layer cannot be formed, and if it is higher than 550°C, Sn evaporates and good crystals cannot be obtained.

〔Effect of the invention〕

As explained above, in the compound semiconductor laminate according to the present invention, between the silicon substrate and the compound semiconductor layer,
By interposing a second compound semiconductor layer that has a crystal lattice constant that is almost the same as that of the compound semiconductor layer, the lattice mismatch between the silicon substrate and the compound semiconductor layer is alleviated, and the occurrence of dislocations is reduced. Therefore, a compound semiconductor layer having a larger crystal lattice constant than gallium arsenide, germanium, etc. can be formed on a large area silicon substrate with good crystallinity.

[Brief explanation of the drawing]

FIG. 1 is a diagram illustrating the principle of a compound semiconductor stack according to the present invention. FIG. 2 is an explanatory diagram of a compound semiconductor stack according to the first embodiment of the present invention. FIG. 3 is an explanatory diagram of a compound semiconductor stack according to a second embodiment of the present invention. l...Silicon substrate, 2.3.6.21...Compound semiconductor layer, 4.5.7.
8.9...Interface.

Claims (1)

[Claims] In a compound semiconductor laminate having a compound semiconductor layer (3) on a silicon substrate (1), the compound semiconductor layer is provided between the silicon substrate (1) and the compound semiconductor layer (3). A compound semiconductor laminate characterized in that a mixed crystal layer (2) of germanium and tin having a crystal lattice constant substantially the same as that of (3) is interposed.