JPH022095A - Preparation of ic module and base material for ic module - Google Patents
Preparation of ic module and base material for ic moduleInfo
- Publication number
- JPH022095A JPH022095A JP63144448A JP14444888A JPH022095A JP H022095 A JPH022095 A JP H022095A JP 63144448 A JP63144448 A JP 63144448A JP 14444888 A JP14444888 A JP 14444888A JP H022095 A JPH022095 A JP H022095A
- Authority
- JP
- Japan
- Prior art keywords
- circuit board
- module
- semiconductor element
- sealant
- tape
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000463 material Substances 0.000 title claims abstract description 16
- 239000004065 semiconductor Substances 0.000 claims abstract description 47
- 238000004519 manufacturing process Methods 0.000 claims abstract description 28
- 238000007789 sealing Methods 0.000 claims abstract description 17
- 238000007689 inspection Methods 0.000 claims abstract 3
- 238000000465 moulding Methods 0.000 claims description 4
- 239000008393 encapsulating agent Substances 0.000 claims 4
- 238000004220 aggregation Methods 0.000 claims 1
- 230000002776 aggregation Effects 0.000 claims 1
- 238000000034 method Methods 0.000 abstract description 59
- 239000000565 sealant Substances 0.000 abstract description 19
- 229920005989 resin Polymers 0.000 abstract description 16
- 239000011347 resin Substances 0.000 abstract description 16
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical group [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 9
- 239000011889 copper foil Substances 0.000 description 9
- 238000001721 transfer moulding Methods 0.000 description 7
- 238000010586 diagram Methods 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 5
- 230000002950 deficient Effects 0.000 description 3
- 239000004642 Polyimide Substances 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 238000012546 transfer Methods 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000011156 evaluation Methods 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 229920005992 thermoplastic resin Polymers 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
- H01L2224/48228—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad being disposed in a recess of the surface of the item
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Credit Cards Or The Like (AREA)
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野］
本発明は、回路基板部に集積回路素子を載置しＩＣモジ
ュールを製作するＩＣモジュールの製造方法と、前記製
造方法に使用するＩＣモジュール用基材に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an IC module manufacturing method for manufacturing an IC module by mounting an integrated circuit element on a circuit board portion, and an IC module manufacturing method used in the manufacturing method. Regarding the base material.
［従来の技術］
半導体素子の封止方法として従来より帯状の薄いテニプ
上にパターニングされた銅箔パターンに半導体素子をボ
ンディングし樹脂にて前記半導体素子を封止するテープ
オートメイテッド ポンディング（以下ＴＡＢと略す
）方法、基板上に配線接続された半導体素子に液状の樹
脂を滴下し、前記樹脂を加熱硬化させ半導体素子を封止
する、デツプオンボード（以下ＣＯＢと略す）方法、半
導体素子が装填された金型に予熱した樹脂を入れ封入成
形するトランスファ成形方法及び金属、セラミック、ガ
ラスにて半導体素子を気密封止するハーメチックシール
方法等が知られている。尚、半導体素子を樹脂にて封止
する方法には上記以外にも数種類の方法が知られている
。[Prior Art] Tape Automated Bonding (hereinafter referred to as TAB) is a conventional method for sealing semiconductor devices, in which a semiconductor device is bonded to a copper foil pattern patterned on a thin band-shaped tape and the semiconductor device is sealed with resin. Depth-on-board (hereinafter abbreviated as COB) method, in which a liquid resin is dropped onto a semiconductor element wire-connected on a substrate, and the resin is heated and cured to seal the semiconductor element. Known methods include a transfer molding method in which preheated resin is placed in a mold and sealed and molded, and a hermetic sealing method in which a semiconductor element is hermetically sealed with metal, ceramic, or glass. In addition to the above methods, several other methods are known for encapsulating semiconductor elements with resin.
上記方法の一例として、ＴＡ［３方法の概略図を第６図
（ａ）に、第６図（ａ）のＡ−Ａ断面図を第６図（ｂ）
に示し、以下にＴＡＢ方法にて製造される集積回路（以
下ＩＣと略す）モジュールの構成を説明する。尚、ＩＣ
モジュールとは、半導体素子が上述したような方法で封
止された単体を怠味する。As an example of the above method, a schematic diagram of the TA[3 method is shown in FIG. 6(a), and a sectional view taken along line AA in FIG. 6(a) is shown in FIG.
The configuration of an integrated circuit (hereinafter abbreviated as IC) module manufactured by the TAB method will be described below. In addition, I.C.
A module refers to a single unit in which a semiconductor element is sealed using the method described above.
第６図（ａ）及び第６図（ｂ）において、ポリイミド等
にてなる薄い帯状のテープ３０の中央部には方形状の穴
３１が明けられる。テープ３０の片表面上には、穴３１
の長手方向の２辺のそれぞれの辺と直角に複数の銅箔３
２が等間隔にパターニングされる。尚、銅箔３２は穴３
１の空間部にも延在するものであるが、穴３１の前記２
辺から対向して延在する銅箔３２ａと銅箔３２ｂとは接
触していない。次に、テープ３０の穴３１には、半導体
素子３３がバンプ３４を介して穴３１に延在する銅箔３
２ａ及び銅箔３２ｂにまたがって接続される。In FIGS. 6(a) and 6(b), a rectangular hole 31 is made in the center of a thin strip-shaped tape 30 made of polyimide or the like. A hole 31 is formed on one surface of the tape 30.
Plural copper foils 3 perpendicular to each of the two longitudinal sides of
2 are patterned at equal intervals. Note that the copper foil 32 is located in the hole 3.
2 of the hole 31.
Copper foils 32a and 32b extending oppositely from the sides are not in contact with each other. Next, in the hole 31 of the tape 30, the semiconductor element 33 is placed in a copper foil 3 that extends into the hole 31 via the bump 34.
2a and the copper foil 32b.
さらに、半導体素子３３及びテープ３０の穴３１部は、
樹脂にてなる封止剤３５でテープ３０の両面より封止さ
れ、ＩＣモジュールが形成される。Furthermore, the semiconductor element 33 and the hole 31 portion of the tape 30 are
Both sides of the tape 30 are sealed with a sealant 35 made of resin to form an IC module.
［発明が解決しようとする課題］
上述のような方法で製造されるＩＣモジュールを評価す
る項目としては、製造されたＩＣモジュールを回路基板
に実装する際、ＩＣモジュールが占める面積を小さくす
るために、ＩＣモジュールの厚さが薄いこと及びＩＣモ
ジュールの外形寸法が均一なこと、さらに大量生産でき
ること、回路基板に実装したＩＣモジュールが故障して
いる場合、良品と交換できること及び生産コストか安価
なこと等があげられる。[Problems to be Solved by the Invention] Items for evaluating IC modules manufactured by the method described above include: , the thickness of the IC module is thin, the external dimensions of the IC module are uniform, mass production is possible, if the IC module mounted on the circuit board is malfunctioning, it can be replaced with a good product, and the production cost is low. etc. can be mentioned.
ところが上述したＩＣモジュールの製造方法は、それぞ
れの一長一短があり上記のＩＣモジュールの評価項目の
総てについて満足しないという問題点があった。However, the above-mentioned IC module manufacturing methods each have their own advantages and disadvantages, and there is a problem in that they do not satisfy all of the above-mentioned IC module evaluation items.
例えばＴＡＢ方法においては、大量生産は可能であるが
、前記バンプの素材コストが高価なことや、製造された
ＩＣモジュールを回路基板に実装する際、専用工具が必
要であることなどから加工費が高価となり、生産コスト
が高くなる欠点があ又、ＣＯＢ方法においては、ＩＣモ
ジュールの厚さは薄くできるが、ＩＣモジュールの外形
寸法の均一性に欠けたり、回路基盤に実装してしまうと
不良半導体素子の交換ができないという欠点がある。For example, in the TAB method, mass production is possible, but processing costs are high due to the high material cost of the bumps and the need for special tools when mounting the manufactured IC module on a circuit board. In addition, the COB method has the disadvantage of being expensive and increases production costs.Although the thickness of the IC module can be made thinner, the IC module may lack uniformity in external dimensions and may be defective when mounted on a circuit board. The disadvantage is that the elements cannot be replaced.
又、トランスファ成形方法においては、金型で成形され
ることからＩＣモジュールの外形寸法は製品毎に均一で
あり、大量生産を行なうことができる。しかしＩＣモジ
ュールの厚さが厚くなることや生産コストが高いという
欠点がある。Further, in the transfer molding method, since the IC module is molded using a mold, the external dimensions of the IC module are uniform for each product, and mass production can be performed. However, there are drawbacks such as increased thickness of the IC module and high production cost.
又、ハーメチックシール方法においても、前述のトラン
スファ成形方法と同様の長短所がある。Further, the hermetic sealing method also has advantages and disadvantages similar to those of the transfer molding method described above.
本発明は上述した問題点を解決するためになされたもの
で、製造されるＩＣモジュールは、厚さが薄く、外形寸
法が製品毎に均一であり、大量生産が可能で、生産コス
トが低くさらに、実装した際不良品を良品に交換する交
換性のよいＩＣモジュールの製造方法及び前記製造に使
用するＩＣモジュール用基材を提供することを目的とす
る。The present invention has been made to solve the above-mentioned problems, and the manufactured IC module has a thin thickness, uniform external dimensions for each product, can be mass-produced, and has a low production cost. An object of the present invention is to provide a method for manufacturing an IC module with good replaceability in which a defective product is replaced with a non-defective product upon mounting, and a base material for an IC module used in the manufacturing.
［課題を解決するための手段］
本発明のＩＣモジュールの製造方法は、薄い帯状の基材
表面の回路基板部に半導体素子を載置する第１の工程と
、前記半導体素子と回路基板部上の端子とを結線する第
２の工程と、結線された半導体素子を封止剤にて封止し
ながら封止剤を成形する第３の工程と、封止後封止剤表
面に捺印し、半導体素子の検査及び封止された半導体素
子を前記基材からの分離を行なう第４の工程とを備えた
ことを特徴とする。[Means for Solving the Problems] The method for manufacturing an IC module of the present invention includes a first step of placing a semiconductor element on a circuit board portion on the surface of a thin strip-shaped base material, and a step of placing the semiconductor element and the circuit board portion on the surface of a thin strip-shaped base material. a second step of connecting the wires to the terminals of the device; a third step of molding the sealant while sealing the connected semiconductor element with the sealant; and stamping the surface of the sealant after sealing; The present invention is characterized by comprising a fourth step of inspecting the semiconductor element and separating the sealed semiconductor element from the base material.
上記のような工程を備えることで、第１、第２及び第４
の工程は、ＩＣモジュールの大量生産を可能にする。第
３の工程は、封止剤を成形することにより製造されるＩ
Ｃモジュールの外形寸法を均一化しさらに、ＩＣモジュ
ールの早さを薄くする。By providing the above steps, the first, second and fourth
The process enables mass production of IC modules. The third step is the I manufactured by molding the sealant.
To make the external dimensions of a C module uniform and further to make the speed and thickness of an IC module thin.
さらに本発明のＩＣモジュール用基材は、半導体素子の
端子と接続される複数の第１の端子部と、前記端子部と
対となる複数の第２の端子部とを備えた回路基板部が分
離可能な状態で複数、帯状に集合したことを特徴とする
。Further, the IC module base material of the present invention includes a circuit board portion including a plurality of first terminal portions connected to terminals of a semiconductor element and a plurality of second terminal portions paired with the terminal portions. It is characterized by a plurality of strips assembled in a separable state.
上記のように構成することで、第２の端子部は、回路基
板部表面上に形成されろ。回路基板部表面上に第２の端
子部が形成されることは９、実装後のＩＣモジュールの
交換性を向上さける。By configuring as described above, the second terminal portion is formed on the surface of the circuit board portion. Forming the second terminal portion on the surface of the circuit board portion 9 improves the replaceability of the IC module after mounting.
［実施例コ
本発明の一実施例を示す第１図（ａ）ないし第１図（ｇ
）、第２図（ａ）及び第２図（ｂ）において、１は、例
えばガラスエポキン樹脂やポリイミド等の有機材料にて
なるテープであり、テープｌの側縁部１ｂには、テープ
１を等間隔ずつ移送する際に移送部（図示せず）のギア
の歯と係合する過大１ｄが複数個等間隔に空けられてい
る、薄い帯状の写真機用の撮影フィルム形状のものであ
る。又、テープ１の材料は耐熱性の高いものが好ましい
。テープ１の中央部にはＩ字形状又はチャンネル形状の
抜穴にてなる切欠部１ａが互いに接触しない様に適宜な
間隔を有して複数形成される。したがってテープｌの中
央部には、テープ１の側縁部１ｂと支持部ＩＣにて支持
される方形状の回路基板部２が複数個形成される。[Example] Figures 1(a) to 1(g) showing an example of the present invention
), FIG. 2(a) and FIG. 2(b), 1 is a tape made of an organic material such as glass epoxy resin or polyimide, and tape 1 is attached to the side edge 1b of tape 1. It is shaped like a thin strip of photographic film for a camera, and has a plurality of oversized portions 1d spaced at equal intervals, which engage with the gear teeth of a transfer section (not shown) when the film is transferred at intervals. Further, it is preferable that the material of the tape 1 has high heat resistance. In the center of the tape 1, a plurality of notches 1a formed by I-shaped or channel-shaped holes are formed at appropriate intervals so as not to contact each other. Therefore, a plurality of rectangular circuit board parts 2 are formed in the center of the tape 1, and are supported by the side edge part 1b of the tape 1 and the support part IC.
第２図（ａ）に示すように回路基板部２の集積回路素子
接続側には、中央部に集積回路素子を載置する部分であ
る方形状のアイランド２ａが形成され、アイランド２３
部の対向する２辺に平行な状態で金属にてなる複数のパ
ッド２ｂが、電気的に互いに絶縁されて一列に並んで形
成される。As shown in FIG. 2(a), a rectangular island 2a is formed in the center on the integrated circuit element connection side of the circuit board part 2, and the island 23 is a part on which the integrated circuit element is placed.
A plurality of pads 2b made of metal are formed in parallel to two opposing sides of the portion, and are electrically insulated from each other and lined up in a row.
第２図（ｂ）は、第２図（ａ）に示すテープｌの裏面を
示している。回路基板部２の対向する２辺から回路基板
部２の中央部に向い金属にてなる複数の外部接続端子２
ｃが互いに電気的に絶縁されて形成される。尚、回路基
板部２の裏面に形成される外部接続端子２ｃの配置形態
は、上述した例に限らず、第３図（ａ）に示すように回
路基板部２の４辺から形成されてらいいし、例えばＩＣ
カード用のＩＣモジュールとして第３図（ｂ）に示すよ
うに、回路基板部２の裏面全面に外部接続端子２ｃを形
成してもよい。尚、前述したパッド２ｂと、外部接続端
子２ｃとは第４図及び第５図に示すように１対ｌに対応
しているものである。又、第４図に示すように、製造方
法によっては、パッド２ｂと外部接続端子２Ｃとはテー
プｌの半導体素子接続側とテープｌの裏面とに形成され
ず、テープｌの裏面に形成される外部接続端子２Ｃの外
表面がテープｌの半導体素子接続側に露出しパッド２ｂ
となる場合らある。FIG. 2(b) shows the back side of the tape l shown in FIG. 2(a). A plurality of external connection terminals 2 made of metal are oriented from two opposing sides of the circuit board section 2 toward the center of the circuit board section 2.
c are electrically insulated from each other. Note that the arrangement form of the external connection terminals 2c formed on the back surface of the circuit board section 2 is not limited to the above-mentioned example, and may be formed from the four sides of the circuit board section 2 as shown in FIG. 3(a). For example, IC
As shown in FIG. 3(b) as an IC module for a card, external connection terminals 2c may be formed on the entire back surface of the circuit board section 2. The pads 2b and the external connection terminals 2c are in a one-to-one correspondence as shown in FIGS. 4 and 5. Further, as shown in FIG. 4, depending on the manufacturing method, the pad 2b and the external connection terminal 2C are not formed on the semiconductor element connection side of the tape l and the back surface of the tape l, but are formed on the back surface of the tape l. The outer surface of the external connection terminal 2C is exposed to the semiconductor element connection side of the tape l, and the pad 2b
There are cases where this happens.
以上のように構成された半導体素子接続側の回路基板部
２のアイランド２ａには第１図（ｂ）及び第１図（ｆ）
に示すように半導体素子３が載置される。The island 2a of the circuit board section 2 on the semiconductor element connection side configured as above is shown in FIG. 1(b) and FIG. 1(f).
A semiconductor element 3 is placed as shown in FIG.
そして第１図（Ｃ）及び第４図に示すように半導体素子
３の接続端子（図示せず）と回路基板部２の各パッド２
ｂとは金属にてなるワイヤ４を使用し公知のワイヤボン
ディング方式により接続される。As shown in FIG. 1(C) and FIG. 4, connection terminals (not shown) of the semiconductor element 3 and each pad 2 of the circuit board section
b is connected by a known wire bonding method using a wire 4 made of metal.
又、第１図（「）及び第５図に示すように、半導体素子
３の接続端子と前記パッド２ｂとは、金属にてなるバン
ブ５を介し公知のフリップチップ方式にて接続してもよ
い。Further, as shown in FIG. 1 ( ) and FIG. 5 , the connection terminal of the semiconductor element 3 and the pad 2b may be connected via a bump 5 made of metal by a known flip-chip method. .
次に第１図（ｄ）、第１図（ｇ）、第４図及び第５図に
示すように回路基板部２の半導体素子接続側に載置され
た半導体素子３と回路基板部２の樹脂封止部２ｄとは樹
脂にてなる封止剤６にて封止される。尚、封止剤６とし
ては熱硬化性又は熱可塑性の樹脂のどちらでも良い。尚
、製造されたＩＣモジュールが実装される際、ハンダ付
けが行なわれる場合があるので、封止剤６は、例えばエ
ポキシ樹脂のような耐熱性の高い樹脂が好ましい。尚、
ＩＣモジュールが樹脂接着による方法で実装されるなら
ば、封止剤６に対する耐熱性はさほど厳しくなくても良
い。Next, as shown in FIG. 1(d), FIG. 1(g), FIG. 4, and FIG. The resin sealing portion 2d is sealed with a sealant 6 made of resin. Note that the sealant 6 may be either thermosetting or thermoplastic resin. Note that since soldering may be performed when the manufactured IC module is mounted, the sealant 6 is preferably a resin with high heat resistance, such as an epoxy resin. still,
If the IC module is mounted by resin bonding, the heat resistance to the sealant 6 need not be so severe.
又、半導体素子３の封止剤６による封止方法としては、
半導体素子３の上方より封止剤６を半導体素子３へ滴下
し、金型にて成形する方法を使用する。この方法によれ
ば、製造されるＩＣモジュールの外形寸法は、製品毎に
均一化されるので、製造されたＩＣモジュールを回路基
板に実装する際、本発明の方法によるＩＣモジュールは
、省スペース及び取付は位置の設定等に有利である。又
、本発明のＩＣモジュールの製造方法によれば、樹脂封
止するのは半導体素子３及び樹脂封止部２ｄが設けられ
る回路基板部２の片面だけでよいので、製造されるＩＣ
モジュールの厚さを薄くすることができる。尚、樹脂封
止する際の空気を逃がす部分として第２図（ａ）に示す
ように樹脂封止部２ｄにはベント２ｅが設けられている
。Further, as a method of sealing the semiconductor element 3 with the sealant 6,
A method is used in which the sealant 6 is dropped onto the semiconductor element 3 from above the semiconductor element 3 and molded using a mold. According to this method, the external dimensions of the manufactured IC module are made uniform for each product, so when the manufactured IC module is mounted on a circuit board, the IC module according to the method of the present invention saves space and Mounting is advantageous for setting the position and the like. Further, according to the method for manufacturing an IC module of the present invention, only one side of the circuit board portion 2 on which the semiconductor element 3 and the resin sealing portion 2d are provided is sealed with resin, so that the manufactured IC
The thickness of the module can be reduced. Incidentally, as shown in FIG. 2(a), a vent 2e is provided in the resin sealing portion 2d to allow air to escape during resin sealing.
又、封止剤６の設置場所を除く回路基板部２の露出部２
ｒは、外気と接するので耐湿処理を施している。In addition, the exposed portion 2 of the circuit board portion 2 excluding the installation location of the sealant 6
Since r is in contact with the outside air, it is treated with moisture resistance.
次の工程では、半導体素子３等を封止した封止剤６の上
表面には、製品の型式等を示す捺印がなされ、半導体素
子３の製品検査がなされた後、回路基板部２と、テープ
ｌの側縁部ｔｂとを継いでいる支持部１ｃにて回路基板
部２はテープ１から切り離され、ＩＣモジュールとして
製品化される。In the next step, a seal indicating the product model etc. is stamped on the upper surface of the sealant 6 that has sealed the semiconductor element 3 etc., and after the semiconductor element 3 is inspected, the circuit board section 2 and the The circuit board portion 2 is separated from the tape 1 at the supporting portion 1c that joins the side edge portion tb of the tape 1, and is manufactured as an IC module.
以上のように、半導体素子の載置汝び半導体素子の封止
は、連続して搬送されるテープ上にて行なわれるので、
連続して作業工程を進めることができる。又、生産途中
の移送も前記テープを移動すればよく簡単である。した
がって本発明の方法によればＩＣモジュールを大量に生
産することができ、よってＩＣモジュールの単価も下げ
ることがてきる。As mentioned above, since the mounting and sealing of the semiconductor elements are performed on the tape that is continuously conveyed,
You can proceed with the work process continuously. Furthermore, transportation during production is simple, just by moving the tape. Therefore, according to the method of the present invention, IC modules can be mass-produced, and the unit price of the IC modules can therefore be reduced.
又、回路基板に実装後ＩＣモジュールの不良等でＩＣモ
ジュールを交換する場合、従来の方法によれば例えば第
６図（ｂ）に示すように銅箔がテープ上より延在し、こ
の延在している部分にて銅箔は回路基板に接続されてい
たので、交換時に前記銅箔が切れたりしてＩＣモジュー
ルの交換性は良くなかった。しかし、本発明の方法にて
生産されろＩＣモジュールは外部接続端子は第２図（ｂ
）に示すように回路基板部より突出していないので、交
換時に外部接続端子が切断するようなことはない。よっ
てＩＣモジュールの交換性は良い。In addition, when replacing an IC module due to a defect in the IC module after mounting it on a circuit board, according to the conventional method, the copper foil extends from the top of the tape as shown in FIG. 6(b), and this extension Since the copper foil was connected to the circuit board at the portion where the IC module was replaced, the copper foil would break during replacement, making it difficult to replace the IC module. However, the IC module produced by the method of the present invention has external connection terminals as shown in Figure 2 (b).
) As shown in (), since it does not protrude from the circuit board part, the external connection terminal will not be disconnected during replacement. Therefore, the exchangeability of the IC module is good.
具体的に示すと、例えば６４キロビツトの記憶容呈て２
８ピンの外部接続端子を有するＩＣモジュールを製造し
た場合の外形寸法、単価及び実装後の交換性について、
従来例であるＴＡＢ方法、ＣＯＢ方法の及びトランスフ
ァ成形方法と、本発明の方法とを比較してみる。まず外
形寸法については、ＴＡＢ方法によるＩＣモジュールは
、縦１１ｍ１ｉＸ 横＋ ９ ｍｍｘ厚さ１．ｏｍｍ、
ＣＯＢ方法によるものが縦１０ｍｍＸ横１５ｍｍＸ厚さ
１．０ｍｍ、トランスファ方法によるものが縦１１ｍｍ
Ｘｔ＆１９ｍｍＸ厚さ２ 、５ ｍｍ及び本発明の方法
によるものが縦１０ｍｍＸ横１５ｍｍＸ厚さ１．Ｏｍｍ
である。単価については、ＴＡＢ方法によるものが３５
０円、ＣＯＢ方法によるものが２７０円、トランスファ
成形方法によるものが３００円及び本発明の方法による
ものが２７０円である。交換性については、ＴＡＢ方法
によるＩＣモジュールは前述したように、堆しく、ＣＯ
Ｂ方法によるものは実装したＩＣモノニールごと封止剤
にて封止するので不可であり、トランスファ成形方法及
び本発明の方法によるものとは交換可能である。Specifically, for example, it has a memory capacity of 64 kilobits2.
Regarding the external dimensions, unit price, and replaceability after mounting when manufacturing an IC module with an 8-pin external connection terminal,
The conventional TAB method, COB method, and transfer molding method will be compared with the method of the present invention. First of all, regarding the external dimensions, the IC module made by the TAB method is 11 m x 1 x x 9 mm x 1. omm,
The one made by the COB method is 10 mm long x 15 mm wide x 1.0 mm thick, and the one made by the transfer method is 11 mm long.
Xt & 19 mm x thickness 2.5 mm, and the one made by the method of the present invention is 10 mm long x 15 mm wide x 1.5 mm thick. Omm
It is. Regarding the unit price, the one based on the TAB method is 35
0 yen, 270 yen for the COB method, 300 yen for the transfer molding method, and 270 yen for the method of the present invention. As for replaceability, as mentioned above, IC modules using the TAB method are expensive and CO
Method B is not possible because the mounted IC monolayer is sealed with a sealant, and it is interchangeable with the transfer molding method and the method of the present invention.
以上のことより、外形寸法の厚さの観点からではＴ Ａ
１３．方法、Ｃ０Ｉ３方法及び本発明の方法が良い。From the above, from the perspective of external dimension thickness, T A
13. The method, C0I3 method and the method of the present invention are preferred.
単価の観点からではＣＯＢ方法及び本発明の方法が良い
。交換性の観点からでは、トランスファ成形方法及び本
発明の方法が良いことか判る。したがってＩＣモジュー
ルの厚さ、単価及び交換性の総てに本発明の方法は優れ
ていることが判る。From the viewpoint of unit cost, the COB method and the method of the present invention are better. From the viewpoint of replaceability, it can be seen that the transfer molding method and the method of the present invention are better. Therefore, it can be seen that the method of the present invention is superior in all aspects of IC module thickness, unit cost, and replaceability.
［発明の効果］
以上詳述したように本発明によれば、テープ状の基材に
第１及び第２の端子を備え、堰（オと分離可能な複数の
回路基板部上に半導体素子を載置し、半導体素子と前記
回路基板部上の第１の端子とを接続し、半導体素子を■
載置した前記回路基板部の片面側のみ封止剤にて成形し
ながら、半導体素子を封止するので、製造されるＩＣモ
ジュールは、厚さが薄く、外形寸法が製品毎に均一とな
る。又、本発明のＩＣモジュールの製造方法は、テープ
状の基材に曳敗の回路基板部を設け、半導体素子が封止
された回路基板部は基材から容易に分離できるので、大
量生産が可能となる。又、大量生産が可能となるので生
産コストを低下させることができる。さらに第２の端子
は前記回路基板部表面上に固着形成されるので、実装し
たＩＣモジュールを交換する際第２の端子が損傷するこ
とはない。[Effects of the Invention] As detailed above, according to the present invention, a tape-shaped base material is provided with first and second terminals, and semiconductor elements are mounted on a plurality of circuit board portions that can be separated from a weir. the semiconductor element and the first terminal on the circuit board part are connected, and the semiconductor element is
Since the semiconductor element is sealed while molding only one side of the mounted circuit board part with a sealant, the manufactured IC module has a thin thickness and uniform external dimensions for each product. In addition, the method for manufacturing an IC module of the present invention provides a removable circuit board part on a tape-shaped base material, and the circuit board part in which the semiconductor element is sealed can be easily separated from the base material, making mass production possible. It becomes possible. Moreover, since mass production becomes possible, production costs can be reduced. Furthermore, since the second terminal is firmly formed on the surface of the circuit board, the second terminal will not be damaged when replacing the mounted IC module.
したがってＩＣモジュールの交換性が良くなる。Therefore, the exchangeability of IC modules is improved.
第１図（ａ）ないし第１図（ｇ）は、本発明のＩＣモジ
ュールの製造方法の一例を示す図、第２図（ａ）は、本
発明のＩＣモジュールの製造方法に使用する基（オを示
す平面図、第２図（ｂ）は第２図（ａ）の裏面図、第３
図（ａ）及び第３図（ｂ）は、本１発明の方法にて製造
されるＩＣモジュールの外部接続端子の配置例を示す図
、第４図及び第５図は、本発明の方法にて製造されるＩ
Ｃモジュールの横断面図、第６図（ａ）は、従来の製造
方法の一例を示す図、第６図（ｂ）は、従来のＩＣモジ
ュールの横断面図である。
第３図（０）
第４図
１・・・テープ、 ２・・回路基板部、２ｂ・・・
バッド、 ２ｃ・・外部接続端子、３・・・半導体素
子、・１ ワイヤ、
５・・バンプ、 ６・・・封止剤。
第５図1(a) to 1(g) are diagrams showing an example of the method for manufacturing an IC module of the present invention, and FIG. 2(a) is a diagram showing an example of the method for manufacturing an IC module of the present invention. Fig. 2(b) is a back view of Fig. 2(a),
Figures (a) and 3(b) are diagrams showing examples of the arrangement of external connection terminals of an IC module manufactured by the method of the present invention, and Figures 4 and 5 are diagrams showing examples of the arrangement of external connection terminals of an IC module manufactured by the method of the present invention. I manufactured by
FIG. 6(a) is a cross-sectional view of a C module, and FIG. 6(b) is a cross-sectional view of a conventional IC module. Figure 3 (0) Figure 4 1...Tape, 2...Circuit board part, 2b...
Bud, 2c...External connection terminal, 3...Semiconductor element, 1 wire, 5...Bump, 6...Sealing agent. Figure 5
Claims (2)
載置する第１の工程と、 前記半導体素子と回路基板部上の端子とを結線する第２
の工程と、 結線された半導体素子を封止剤にて封止しながら封止剤
を成形する第３の工程と、 封止後封止剤表面に捺印し、半導体素子の検査及び封止
された半導体素子を前記基材からの分離を行なう第４の
工程とを備えたことを特徴とするＩＣモジュールの製造
方法。(1) A first step of placing a semiconductor element on a circuit board section on the surface of a thin strip-shaped base material, and a second step of connecting the semiconductor element and terminals on the circuit board section.
a third step of molding the encapsulant while sealing the connected semiconductor element with the encapsulant; and a stamping on the surface of the encapsulant after sealing, and inspection of the semiconductor element and inspection of the encapsulant. and a fourth step of separating the semiconductor element from the base material.
部と、前記端子部と対となる複数の第２の端子部とを備
えた回路基板部が分離可能な状態で複数、帯状に集合し
たことを特徴とするＩＣモジュールの製造に使用するＩ
Ｃモジュール用基材。(2) A plurality of separable circuit board portions each having a plurality of first terminal portions connected to terminals of a semiconductor element and a plurality of second terminal portions paired with the terminal portions are arranged in a strip shape. I used for manufacturing an IC module characterized by aggregation of
Base material for C module.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63144448A JPH022095A (en) | 1988-06-10 | 1988-06-10 | Preparation of ic module and base material for ic module |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63144448A JPH022095A (en) | 1988-06-10 | 1988-06-10 | Preparation of ic module and base material for ic module |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH022095A true JPH022095A (en) | 1990-01-08 |
Family
ID=15362469
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63144448A Pending JPH022095A (en) | 1988-06-10 | 1988-06-10 | Preparation of ic module and base material for ic module |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH022095A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2740906A1 (en) * | 1995-11-07 | 1997-05-09 | Solaic Sa | Integrated circuit module for plastic card |
| FR2788882A1 (en) * | 1999-01-27 | 2000-07-28 | Schlumberger Systems & Service | Integrated circuit module for smart card |
| JP2007538298A (en) * | 2003-10-28 | 2007-12-27 | ジェムプリュス | Manufacturing method of electronic key provided with USB connector and electronic key obtained |
-
1988
- 1988-06-10 JP JP63144448A patent/JPH022095A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2740906A1 (en) * | 1995-11-07 | 1997-05-09 | Solaic Sa | Integrated circuit module for plastic card |
| FR2788882A1 (en) * | 1999-01-27 | 2000-07-28 | Schlumberger Systems & Service | Integrated circuit module for smart card |
| WO2000045434A1 (en) * | 1999-01-27 | 2000-08-03 | Schlumberger Systemes | Integrated circuit device, electronic module for chip card using said device and method for making same |
| US7208822B1 (en) | 1999-01-27 | 2007-04-24 | Axalto Sa | Integrated circuit device, electronic module for chip cards using said device and method for making same |
| JP2007538298A (en) * | 2003-10-28 | 2007-12-27 | ジェムプリュス | Manufacturing method of electronic key provided with USB connector and electronic key obtained |
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