JPH02189614A - Semiconductor circuit device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Summary of the Invention] Regarding a semiconductor circuit device in which two or more IC chips are mounted on the same substrate, the purpose of this invention is to prevent malfunction of the IC chips when power is turned on. Equipped with an independent IC chip, the IC
In semiconductor circuit devices that exchange signals between chips,
The second IC chip is configured to be operated later than the first IC chip when the power is turned on, and power is supplied from the power input terminal that directly supplies power to the first IC chip via the delay means. .

[Industrial application field]

The present invention relates to a semiconductor circuit device in which two or more independent IC chips are mounted on the same substrate.

cpu <central processing unit'), RAM (random
A semiconductor circuit device in which ICs (semiconductor integrated circuits) such as access memory) and peripheral circuits are formed on independent chips and mounted on the same support substrate will be put to practical use, for example, as a multi-chip IC card. It is said that In this case, in order to prevent malfunctions when the power is turned on, it is necessary to order the power-on of each chip.

[Conventional technology]

FIG. 3 shows an example of a conventional multi-chip IC card.
2 is an independent IC chip; 20 is a common support substrate (card); IC chip 1 is, for example, a CPU;
The chip 2 is an E2FROM (electrically writable/erasable programmable read-only memory) in which data is read and written by the CPU. Each chip 1.2 is provided with a power input terminal 4.5, a ground terminal 6, and input/output terminals 7-10 for data and the like.

In such an IC card, if the power-on order of the IC chip 2 is earlier than that of the C-chip 1, there is a possibility that an unexpected output before the IC chip 1 is power-on-reset may cause erroneous writing to the IC chip 2. For this reason and other reasons, conventionally, independent power input terminals 4 and 5 are provided to order the rise of the external power supply.

[Problem to be solved by the invention]

However, in order to order the start-up of the external power supply, it is necessary to provide a control circuit on the external power supply side, which has the disadvantage that it cannot be used with a power supply installed on a boat. In addition, multiple power supply input terminals 4.5 are required to receive the power supply Vcc of the same voltage.
Therefore, there is a drawback that the number of terminals increases as the number of chips increases.

The present invention internally orders the rise of the power supply, thereby eliminating the need for external control and reducing the number of power supply input terminals.

[Means to solve the problem]

FIG. 1 is a diagram showing the principle of the present invention. The difference from FIG. 3 is that the power input terminal 5 of the IC chip 2 is omitted, and instead, the IC The point is that power supplies V and cc are supplied to the chip 2. In addition, I.C.
Chips 1 and 2 and delay means 3 are representative of the same type of IC chips and delay means, if any.

[For production]

In FIG. 1, when the voltage of the power input terminal 4 is raised by an external power supply, the power supply Vcc of the IC chip 1 is immediately raised. However, the power supply Vcc of the IC chip 2 is
Therefore, it rises to the specified value after a predetermined delay time.

Therefore, there is no need for the external power supply to have a function to control the order in which the power is turned on, so a normal external power supply can be used. Also,
Since multiple chips can share a power input terminal with the same voltage, there is an advantage that fewer terminals are required. Of course, IC chip 2
The power rise of the IC chip 1 is slower than the power rise of the IC chip 1 (, I
This is after the C chip 1 has been power-on reset.
There is no fear that the IC chip 2 will malfunction such as erroneous writing due to the random output of the IC chip 1.

〔Example〕

FIG. 2 is a main circuit diagram showing an embodiment of the present invention, and shows an example of the delay means 3. In FIG. In this example, from power input terminal 4 to I
The wiring 21 leading to the power input terminal of the C chip 2 has a resistance R and a distributed capacitance C to constitute an integrating circuit with an appropriate time constant. The delay time due to this integration circuit is
The time difference (1°-1(1)) from rising at o to tl when the output reaches the specified value, can be arbitrarily set by the values of C and H.

This delay means may be combined with a transistor.

That is, the transistor is inserted into the wiring 21 connecting the power supply terminal of the IC chip 2 to the power supply input terminal 4, and the base current of the transistor is controlled by the output of the delay means shown in FIG.
After a predetermined delay, the transistor is turned on and the IC chip 2 is powered from the power input terminal 4. With this method, power consumption by the delay means 3 can be reduced.

〔Effect of the invention〕

As explained above, according to the present invention, in a semiconductor circuit device using two or more IC chips, it is possible to control the order in which power is applied to each IC chip without increasing the number of power input terminals, so that the circuit immediately after power is turned on can be controlled. Operation can also be ensured, which greatly contributes to improving the performance of such semiconductor circuit devices.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is an explanatory diagram of the principle of the present invention, FIG. 2 is an explanatory diagram showing an embodiment of the present invention, and FIG. 3 is a configuration diagram of a conventional multi-chip ■C card. In the figure, 1.2 is an IC chip, 3 is a delay means, is a power input terminal, and 20 is a board. applicant

Claims (1)

[Claims] 1. Two or more independent IC chips (1
. ), a semiconductor circuit device characterized in that power is supplied from a power input terminal (4) that directly supplies power to the first IC chip (1) via a delay means (3). .